cmp for tsv’scmpconsulting.org/wa_files/2011_6rhoades.pdf• tsv’s can be filled with any of...
TRANSCRIPT
CMP for TSV’s
Robert L. Rhoades, Ph.D.
Presentation for AVS Joint Meeting
June 2011
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Background
TSV Technology and Market Dynamics
CMP Processing for TSV’s (Examples)
Challenges and Issues
Summary
Outline
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Background
• Two-dimensional device scaling is increasingly difficult and fast
approaching fundamental limits of physics.
• 3D integration also faces substantial process and design issues, but
various approaches are now gaining traction as viable paths to
achieve many of the same performance improvements previously
pursued mostly through device shrinks.
• Timing for mainstream adoption of 3D is now. Several memory
intensive applications have already been on the market for a few
years, a few MEMS-based modules are also available, and stacked
logic+memory modules are being launched.
• One of the key technologies to enable 3D structures is TSV’s.
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CMP Applications
CMOS New Apps Substrate/Epi
Glass (oxide) Doped Oxides GaAs
Tungsten Nitrides GaN
Copper NiFe & NiFeCo InP
Shallow Trench Noble Metals CdTe & HgCdTe
Polysilicon Al & Stainless Ge and SiGe
Low k Polymers SiC
Cap Ultra Low k Ultra Thin Wafers Diamond & DLC
Metal Gates Direct Wafer Bond Si & Reclaim
Gate Insulators Through Si Vias SOI
High k Dielectrics 3-D Packaging Quartz
Ir & Pt Electrodes MEMS Titanium
Magnetics Nanodevices
Integrated Optics
2009 - Qty ≥ 36
As CMP applications continue to multiply …
optimized consumables, processes and
methods must be developed with lowest
possible risk and cost
1995 - Qty ≤ 2
CMOS
Glass (oxide)
Tungsten
2001 - Qty ≤ 5
CMOS
Glass (oxide)
Tungsten
Copper
Shallow Trench
Polysilicon
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3D Packaging Apps
Source: Yole Development 2007
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3D Scenerios
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Market Trend
7
Source: TechSearch International
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Role of CMP
• CMP is used in a damascene architecture to fabricate at least one side,
often both sides, of most TSV’s
• TSV’s can be filled with any of several conductive materials.
– Most common options are copper and polysilicon.
– Final choice depends on dimensions, operating voltage and current,
frequency, plus other integration factors.
• Vias can be completely filled or left partially hollow
– Post-CMP cleaning is a major concern with hollow vias
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Typical TSV Flow
Wafer Grind
Etch
(optional)
CMP
Stack
Grind
Thickness
Etch
Thickness
Polish
Thickness
SPC
Thickness
Control
Surface and
Topography
Parameters
Pattern/etch/fill
(front side)
Part of device
fabrication
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TSV Fill Materials
TSV Fill
Material
Deposition
Thickness
Demonstrated CMP
Polish Rate
Dishing / Recess
(Angstroms)
Copper 5 kA – 60 µm 1 kA/min – 8 µm/min 10 A – 0.3 µm
Polysilicon 4 kA – 30 kA 2 kA/min – 15 kA/min 300 – 1200 Ang
Tungsten 3 kA – 9 kA 3 kA;/min – 8 kA/min 150 – 300 Ang
NiFe or NiFeCo 1.5 µm – 8 µm 3 kA/min – 7 kA/min 600 – 4000 Ang
Pt 1.5 µm – 5 µm 1.5 kA/min – 5 kA/min 100 – 800 Ang
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Copper Vias
Source: IBM
• The most common via fill material
• Typical via sizes 5–100 µm and plating
thicknesses 3–40 um
• Cu recess below 0.4 um achieved for
multiple trials
• Leverages CMOS interconnect
technology (somewhat) but requires
substantial reoptimization
Flat across
Feature
2nd Example: Cu (stop on TEOS)
• Intended integration = Direct Wafer Bonding
• Goal of <200 A total topography
POST-CMP TOPOGRAPHY ACHIEVED
70-90 Angstroms
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Tungsten Vias
• Technology adapted from proven CMOS device integrations
• Typical via sizes are sub-micron but vias can be ganged in parallel for higher current
• Small via size required to avoid thick depositions of CVD tungsten (typically high tensile stress)
• TSV thickness also limited by aspect ratio
Edge
Center
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Pt Vias
• Some devices require high temperature processes,
such as annealing of piezoelectric layers
– RF switches, cantilever sensors, and acoustic transducers
• Fabricating TSV’s prior to MEMS (via-first approach)
requires materials that can withstand high annealing
temperatures needed for piezoelectric films (>600oC)
• Platinum is a potential candidate, but fabrication
techniques for Pt vias are not yet mature
13
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Process Flow (partial)
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+V+V
1.Etch vias
in SOI
substrate3-7 mm dia.
5 mm depth
2.Oxidize
silicon
(1 mm);
sputter
Ti/Pt seed (0.7 mm)
3.Deposit
resist
plating
template (3.5 mm)
4.Plate Pt
to fill vias;
remove
resist
5.CMP Pt
over-
burden,
stopping
on SiO2
6.Evaporate
electrodes,
spin coat
PZT (1mm),
anneal (700oC)
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CMP Slurry Screening
• CMP screening experiments
to determine removal rates
• Process targets:
• Pt (RR > 2000 Ang/min)
• Ti (RR > 2000 Ang/min)
• SiO2 (High selectivity)
• Good surface quality
• Slurry C met required
performance and was used
for further work
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SlurryPt Rate
(A/min)
Ti Rate
(A/min)
Tox Rate
(A/min)
Selectivity
(Pt:Ti)
Selectivity
(Ti:Oxide)
A 12 8 <1 1.5 > 8
B 104 1461 195 0.1 7.5
C 2980 3955 132 0.8 30.0
D 436 2108 777 0.2 2.7
0
1000
2000
3000
4000
5000
Slu
rry A
Slu
rry B
Slu
rry C
Slu
rry D
Rem
oval R
ate
(A
ng
/min
)
Pt Rate Ti Rate Oxide Rate
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Pt Vias
• Electroplated
Pt for via fill
• Tolerates high
temperatures
up to 700oC
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Photoresist template
Pt plating overburden
Pt plating overburden
resist
etched viaPlated Pt
Ti/Pt seedSiO2
SiO2
Plated Pt
Ti
Silicon
Additional evap Ti
adhesion layer
Via top view (SEM)Via top view
Pt
TiSiO2
Pre-CMP
Post-CMP
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TSV Improvements
Needed
• Design rule consistency / standardization
• Incoming variation at CMP
• Uniformity
• Selectivity control
• Plug recess/protrusion
• Throughput
• Repeatability
• Cost per unit operation (slurry, pad life, etc.)
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Design Rules
• Via size
– Determines etch aspect ratio and plating thickness
– Electrical requirements drive minimum size
• Via spacing / pattern density
– Wide variation causes CMP local uniformity issues
– High density of vias weakens mechanical strength
• Feature offsets and tolerances
– Direct impact on die-to-die or wfr-to-wfr alignments
• Via recess and allowed variation
– Design specs must be kept realistic with process capability
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Incoming Variation
• Plating thickness variation
– Especially for thicker depositions above 20um
• Etch depth variation
– Range of TSV exposure from opposite side
• TTV from grind or other thinning process
– Determines range of Si to be removed to expose
TSV’s and/or amount of protrusion after exposure
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CMP Variation
• Familiar Sources
– Slurry (pH, particles, etc.)
– Pads
– Conditioning disks
– Wear during pad life
– Test wafer vs product wafer
• Less obvious
– Contamination
– Distribution system
– Pumps & filters
– Slurry dispense location
– Source of H2O2
– Head rebuild technique
– DI water temperature
– Metrology instability (Are you
chasing a ghost?)
– Bake/anneal sensitivity
– Barrier metal grain structure
– Pattern density / layout
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Others?
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CMP Uniformity
• Clearing behavior at CMP driven by 2 factors:
CMP uniformity and deposition uniformity
• TSV is not generally as sensitive as interconnect … but
– Effects are exaggerated with very thick depositions and long
polish times (compared to interconnect)
– Customers prefer older/cheaper equipment in packaging area
which may not have as much control as fab tools
• Selectivity can absorb some variation, but often not
sufficient to make the process robust
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Selectivity Control
• Integration determines what materials are being
polished and what are stop layers
– Barrier metal is not universal
– Stop layer options: Barrier, oxide, Si, other?
• Selectivity is mostly driven by the slurry
• Custom formulations can be finely optimized, but
tunability allows broader industry solutions
• Each change in integration can have a huge impact on
CMP constraints for selectivity
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Recess/Protrusion
• Factors that drive recess/protrusion
– Selectivity among exposed materials
– Material integrity of core portion of TSV
– Overpolish time required to clear all areas of wafer
• Balance is required
– Too much recess Open contacts
– Too much protrusion Mechanical stress or poor bonding
in some integrations (not as critical for solder bumps)
• Overly tight constraints can easily lead to excess
development costs and difficulty meeting timelines
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Throughput
• Most TSV processes involve very thick films
– Leads to long polish times at CMP
• Suppliers are focused on high rate Cu slurries
– First generation about 1-1.5 um/min
– Second generation claiming 3-4 um/min
– Via recess can be a challenge at very high rates
• Multi-wafer tools can be an advantage
24
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Repeatability
• Critical in HVM
– Often overlooked or downplayed in development
• High rate slurries tend to be more vulnerable to
contaminants, mix ratios, etc.
• Endpoint can help absorb variations, but has a
few quirks as well
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Cost Factors
• Development Cost Factors
– Materials choices and availability
– Number of design cycles
– Speed of implementation
• Manufacturing Cost Factors
– Direct Consumables: Pads, slurries, pad life, etc.
– Plating thickness
– Throughput (drives # of tools and capital cost)
– Yield and scrap rate
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Development Costs
• Classic engineering tradeoff:
Speed, Low Cost, or Quality
(choose 2)
• Short product life means shorter
timeline for next gen
• Development $$ have to be
amortized over product life
Actions being taken by manufacturers to control development costs:
Extreme prioritization and minimize cycles of learning
Push early screening and optimization down to suppliers
Outsource non-critical functions or bring in outside resources
Alliances and consortia to share next gen development costs
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Summary
• Through Silicon Via Technology (TSV)
– Enabling many 3D integrations and growing rapidly
– Most TSV flows rely on CMP at least once, often twice
• Areas Needing Improvement
– Design rule consistency / standardization
– Incoming variation at CMP
– Uniformity
– Selectivity control
– Plug recess/protrusion
– Throughput
– Repeatability
– Cost per unit operation (slurry, pad life, etc.)
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THANK YOU !
• Many thanks to the following:
– Dorota Temple and Dean Malta of RTI, Inc. for Pt data
– Other customers who gave permission to use images and data
– Terry Pfau, Paul Lenkersdorfer, & Donna Grannis of Entrepix
• For additional information, please contact:
Robert L. Rhoades, Ph.D.
Entrepix, Inc.
Chief Technology Officer
+1.602.426.8668
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