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8/3/2019 CO2ndMID UandiStar

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1. "Locality of Reference" is related to:a. Register

b. Cachec. Primary Memory

d. Magnetic Tape

2. Expand CAMa. Cache Access Memory

b. Call Access Modec. Contents Addressable Memory

d. Cache Access Module

3. Associative Memory is likea. Primary Memory

b. Secondary Memoryc. Cache Memoryd. Auxiliary Memory

4. In the Memory Hierarchy, top to bottom (Registers to Tape)

a. Capacity Decreasesb. Capacity Increasesc. Speed Increasesd. Cost per bit Increases

5. In the Memory Hierarchy, top to bottom (Registers to Tape)

a. Cost per bit decreases

b. Cost per bit Increasesc. Speed Increases

d. Access Time Decreases

6. In the Memory Hierarchy, bottom to top (Tape to Registers)a. Speed Decreasesb. Access time Increasesc. Capacity Increases

d. Capacity Decreases

7. In the Memory Hierarchy, top to bottom (Registers to tape)a. Speed Increasesb. Speed decreases

c. Cost per bit Increasesd. Access time decreases

8. In the Memory Hierarchy, the following Memory has least capacitya. Registerb. Cache

c. Primary Memoryd. Magnetic Tape

9. In the Memory Hierarchy, the following Memory has maximum Access timea. Register

b. Cachec. Primary Memoryd. Magnetic Tape

0. In the Memory Hierarchy, the following Memory has least Access time

a. Register

b. Cachec. Primary Memory

d. Magnetic Tape

1. In the Memory Hierarchy, Speed of accessing is high for

a. Register

b. Cachec. Primary Memoryd. Magnetic Tape

2. In the Memory Hierarchy, Speed of accessing is low for

a. Registerb. Cache


3. In the following which is accesed sequentiallya. Registerb. Cachec. Primary Memory

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d. Magnetic Tape

4. In the Memory Hierarchy, Cost per bit is least fora. Registerb. Cachec. Primary Memory

d. Magnetic Tape

5. In the Memory Hierarchy, the Cost per bit is most fora. Registerb. Cache


6. 512 x 8 ROM indicates

a. 512 data, 8 address linesb. 512 address, 8 data lines

c. 520 address linesd. 520 data lines

7. The Static RAM consists ofa. Capacitors

b. Internal Flip Flops

c. Internal Cachesd. Filters

8. The Dynamic RAM consists ofa. Capacitors

b. Internal Flip Flopsc. Internal Caches

d. Filters

9. The decoder used for decoding 512 x 8 ROM consists of how many input lines?

a. 512b. 8

c. 9d. 520

0. The Principal technology used for main Memory is based on

a. Semi conductor ICsb. Conductor ICsc. Both Semi Conductor and Conductor ICs

d. Using Insulator

1. Refreshing is required fora. All RAMs

b. Only DRAMsc. Only SRAMs

d. Both SRAMs and DRAMs

2. Boot Strap loader requiresa. RAMb. ROM

c. Any Memoryd. Only Processor

3. By making programs and data available at a rapid rate, it is possible toa. Decrease the performanceb. Increase the performance

c. Save Memoryd. Reduce cost

4. The part of the computer system that supervises the flow of information between Auxiliary Memory and Main Memcalleda. Processor Management System

b. Data Management Systemc. Address Management Systemd. Memory Management System

5. Existence of two or more programs in different parts of the Memory Hierarchy at the same time is defined as:

a. Uni programmingb. Multi programmingc. Multi processingd. Uni processing

6. If Cache Access time is 100ns, Memory access time is 1000ns, if the hit percentage is 100 %, what is the Average a

timea. 100

b. 1000c. 1100



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d. 10

7. If both Cache Memory and Main Memory are updated for a write operation, the type of the Cache Memory is calleda. Write-backb. Write-throughc. Associative

d. TLB

8. If only Cache location is updated during a Write operation as long as there is no replacement, the type of the CacheMemory is calleda. Write-back

b. Write-throughc. Associatived. TLB

9. Replacing the block that has been not used for the longest period of time isa. FIFO

b. LRUc. MRUd. LFU

0. Replacing the page that entered the Memory at first is

a. FIFO

b. LRUc. MRUd. LFU

1. A faster and smaller Memory in between CPU and main Memory is

a. Primary Memoryb. Secondary Memory

c. Cache Memoryd. Auxiliary Memory

2. To compensate speed mismatch between main Memory and Processor, the Memory used isa. Primary Memory

b. Secondary Memoryc. Cache Memory

d. Auxiliary Memory

3. If Hit ratio is 0.8, the miss ratioa. 9.2b. 92 %

c. 0.2

d. 20 %

4. In the following, which is not a Cache Mapping technique

a. Associative Mappingb. Direct Mapping

c. Test-Associative Mapping

d. Set-Associative Mapping

5. In four-way Set-Associative mapping, the number of tags area. One

b. Twoc. Fourd. Sixteen

6. In the following, which is the fastest mapping techniquea. Direct Mapping

b. Associative Mappingc. Test-Associative Mappingd. Set-Associative Mapping

7. In Cache, the data stored isa. Most frequently used

b. Least frequently usedc. Never usedd. Segment with large data

8. The transfer of data between main Memory and Cache is

a. WORDb. BLOCKc. LINEd. CHARACTER

9. The transfer of data between Processor and Cache is

a. WORDb. BLOCK

c. FRAMEd. CHARACTER



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0. "Beladys Anomaly" does not occur ina. FIFOb. LRUc. MRU

d. Optimal replacement

1. In Paging technique, the logical address space isa. Divided into equal partsb. Divided into unequal parts

c. divided into two partsd. Either equal or unequal parts

2. The technique of Segmentation suffers which fragmentationa. Internal

b. Externalc. both Internal and Externald. Neither Internal nor External

3. "Paged Segmentation" hasa. Internal fragmentation

b. External fragmentationc. Zero fragmentationd. Neither Internal nor External

4. The time taken to access a particular track isa. Seek time

b. Latency timec. Access timed. Burst time

5. The time taken to access a particular sector isa. Seek time

b. Latency timec. Access timed. Burst time

6. For a magnetic tape, the access is

a. Random Accessb. Sequential Accessc. Both Random and Sequentiald. Rotational

7. For a magnetic disc, the access is

a. Direct Accessb. Sequential Accessc. Both Random and Sequential

d. Rotational

8. The technique of Paging suffers which fragmentation

a. Internalb. Externalc. both Internal and External

d. Neither Internal nor External

9. By using TLB in Paged segmentationa. Access time decreases

b. Access time increases

c. Speed decreasesd. Fragmentation decreases

0. Contents addressable Memory (CAM) is related toa. Page table

b. Associative Page tablec. Inverted Page tabled. Normal Page table

1. If there are sixteen bits in the Virtual Address format, the size of the Virtual Address isa. 16K words

b. 16 wordsc. 64 K words

d. 16M words

2. If the size of the Page is 1K for a Virtual Address space of 16K, the size of the Frame in main Memory isa. 16K

b. 8Kc. 4Kd. 1 K

3. Discs that are permanently attached to the unit assembly and cannot be removed by the occasional user are calleda. Floppy discs

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b. Hard discsc. External discsd. Flash Memory

4. A disk drive with a removable disk isa. Hard disk

b. Floppy diskc. Permanent diskd. Cache

5. In the following, which is not a Physical Memory

a. Primary Memoryb. Cache Memoryc. Flash Memory

d. Virtual Memory

6. Which Page Replacement technique is most efficient

a. FIFOb. LRUc. MRU

d. LFU

7. Page table contains

a. Starting address of Pageb. Page no., Frame no.c. Length of the page

d. Page no., Segment no.

8. Number of Printing Characters in ACSII code area. 128

b. 94c. 34

d. 8

9. Number of Non Printing Characters in ACSII code are

a. 128b. 94

c. 34d. 8

0. ASCII code uses how many bitsa. 5

b. 7

c. 8d. 9

1. The Cathode Ray Tube contains an electronic gun which can be deflecteda. Only horizontally

b. Only vertically

c. Both horizontally and verticallyd. Neither horizontally nor vertically

2. Input/Output devices connected to the computer are also called as

a. Modemsb. Routersc. Peripherals

d. Processors

3. Which of the following is not a Printer?

a. Inkjet printerb. Dot Matrixc. Laser Printer

d. Scanner

4. In the following which is sequentially accessed

a. Magnetic Discb. Magnetic Tapec. Flash Memory

d. Cache Memory

5. The command used to activate the peripheral and to inform it what to do isa. Control commandb. Status commandc. Data output command

d. Data input command

6. The command that causes the interface to respond by transferring data from the Bus into one of its registers isa. Control command

b. Status commandc. Data output command



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d. Data input command

7. The command used that causes the interface to receive an item of data from the peripheral and places it in its Buffregister isa. Control commandb. Status command

c. Data output commandd. Data input command

8. In Asynchronous data transfer, both sender and receiver accompany a control signal that is:a. Strobe

b. Hand Shakingc. Two wire controld. Single wire control

9. The circuit which provides the interface between computer and similar interactive terminal isa. USRP

b. UARTc. Flip Flopd. D-Flip Flop

0. The command used to test various status conditions in the interface and the peripheral is

a. Control command

b. Status commandc. Data output commandd. Data input command

1. In the following which mapping does not distinguish Memory address and I/O address

a. Memory mapped I/Ob. Isolated I/O

c. Independent I/Od. Interrupt driven I/O

2. In the following which mapping uses different address space for Memory and I/Oa. Memory mapped I/O

b. Isolated I/Oc. Independent I/O

d. Interrupt driven I/O

3. The rate at which Serial information is transmitted and is equivalent to the data transfer in bits per second isa. Baud rateb. Bit rate

c. Control rate

d. Strobe rate

4. In Daisy chaining, the number of interrupt request lines is (are)

a. nb. 2n

c. only one

d. changes

5. In Daisy chaining, the number of interrupt acknowledge lines is (are)a. n

b. 2nc. only oned. changes

6. In the following, which is not priority interrupt methoda. Polling

b. Daisy chainingc. Parallel priorityd. Direct Memory Access

7. In the following, which is efficienta. Programmed I/O

b. Interrupt initiated I/Oc. Direct Memory Accessd. All the equally efficient

8. In the following, which uses separate controller for data transfer

a. Programmed I/Ob. Interrupt initiated I/Oc. Direct Memory Accessd. Memory mapped I/O

9. In Polling, the drawback is

a. Cost is moreb. Complex hardware is required

c. Time consumingd. Maintenance is more



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0. Daisy Chaining isa. Software methodb. Hardware methodc. Both software and hardware

d. Neither software nor hardware

1. In the following, which is not a mode of transfera. Programmed I/Ob. Interrupt initiated I/O

c. Direct Memory Accessd. Memory mapped I/O

2. In Priority interrupt when two devices interrupt the computer at the same, the computer services the devicea. with larger length at first

b. with shorter length at firstc. with highest priority at firstd. with lowest priority at first

3. In Daisy chaining, device with highest priority is ina. First position

b. Middle positionc. Last positiond. Any position

4. Continuously monitoring I/O devices is done ina. Programmed I/O

b. Interrupt initiated I/Oc. Direct Memory Accessd. Memory mapped I/O

5. In the following, which is more time consuminga. Programmed I/O

b. Interrupt initiated I/Oc. Direct Memory Accessd. Memory mapped I/O

6. A block sequence consisting of a number of Memory words is transferred continuously while a DMA controller is ma

of Memory Bus. This isa. Pollingb. Daisy Chainingc. Burst transfer

d. Cycle Stealing

7. DMA controller transfer one data word at a time and transfers the control of the Bus to CPU. This isa. Pollingb. Daisy Chaining

c. Burst transferd. Cycle Stealing

8. In the following, which is a method related to DMA.a. Pollingb. Daisy Chaining

c. Parallel Priorityd. Cycle Stealing

9. For fast transfer of information between Magnetic Disc and Memory, which of the following is recommended

a. Programmed I/O

b. Daisy Chainingc. Pollingd. DMA

0. The DMA controller acts like

a. Primary Memoryb. CPUc. Cache Memoryd. Router

1. The number of basic I/O commands in IBM 370 computer IOP is

a. 50b. 6

c. 8d. 40

2. The number of basic I/O commands in Intel 8089 computer IOP is

a. 50b. 6c. 8

d. 40

3. The Intel 8089 I/O processor contains the IC package ofwww.UandiStar.org

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a. 64 pinsb. 40 pinsc. 16 pinsd. 32 pins

4. A Processor with Direct Memory Access capability that communicates with I/O devices is

a. Input Output Processorb. Data communication processorc. Data communication programmer

d. Input Output programmer

5. A processor that communicates with remote terminals over telephone and other communication media in a serialfashion is calleda. Input Output Processor

b. Data communication processorc. Data communication programmerd. Input Output programmer

6. The I/O processor in IBM 370 computer is calleda. Router

b. Channelc. Deviced. Modem

7. Let the time taken to process a sub-operation in each segment be 20ns. Assume That the pipeline has 4 segments executes 100 tasks in sequence. What is the Speed up of pipeline system?

a. 8000nsb. 3060nsc. 2060nsd. 6000ns

8. The _ _ _ _ _ _ _ _ _ _ architecture represents the organization of a computer containing a single control unit, a

processor unit and a memory unit.a. SIMDb. MISD

c. SISDd. MIMD

9. Total operations performed going through all the segments in the pipeline is called as _ _ _ _ _ _ _ _ _a. functionb. process

c. sequenced. task

0. One type of parallel processing that does not fit Flynn s classification is _ _ _ _ _ _ _ _ processing.a. array

b. vectorc. multid. pipeline

1. The sequence of instructions read from memory constitutes _ _ _ _ _ _ _ _a. data stream

b. execution streamc. instruction streamd. process stream

2. Most of the multi processors and multi computer systems can be classified in _ _ _ _ _ _ _ _ category.

a. MISDb. SIMDc. SISDd. MIMD

3. The behavior of a pipeline can be illustrated with _ _ _ _ _ _ _ diagrama. frequency-timeb. timingc. space-timed. dataflow

4. As the number of tasks increases, the speed up is equal to the number of _ _ _ _ _ _ in the pipeline

a. tasksb. segmentsc. suboperations

d. instructions.

5. Suppose the time delays of four segments are and the interface registers have a delay of tr=10ns. What must

the clock cycle time?

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c. 110nsd. 130ns

6. Each entry in the BTB consists of the address of a previously executed _ _ _ _ _ _ _ _ instruction and the _ _ _ _ _ instruction for that brancha. branch, target

b. branch, bufferc. target, branchd. buffer, branch

7. _ _ _ _ _ _ _ _ _ conflicts arise when an instruction depends on the result of a previous instruction

a. resourceb. branchc. segment

d. data dependency

8. When an overflow occurs, the mantissa of the sum or difference is shifted _ _ _ _ _ _ And exponent incremented b

_ _ _ _a. right, oneb. left, one

c. right, twod. left, two

9. A _ _ _ _ _ _ _ _ pipeline divides an arithmetic operation into suboperations for execution in the pipeline segmentsa. vectorb. arithmetic

c. instructiond. multiple

0. _ _ _ _ _ _ _ _ _ pipeline operates on a stream of instructions by overlapping phases of instruction cycle.

a. arithmeticb. instruction

c. vectord. multiple

1. The instruction fetch segment can be implemented by means of a _ _ _ _ _ _ buffera. LIFO

b. FIFOc. FILOd. LILO

2. The instruction stream queuing mechanism provides an efficient way for reducing _ _ _ _ _ _ _ _ _ _ for reading

instructions from memory

a. access timeb. seek timec. overlapping time

d. processing time

3. _ _ _ _ _ _ _ _ _ is a circuit that detects instructions whose source operands are destinations of instructions furthe

in the pipelinea. operand forwardingb. interlocks

c. delayed loadd. data decoder

4. The method used in most RISC processors is to rely on the compiler to redefine the branches so that they take effe

the proper time in the pipeline. This method is called _ _ _ _ _ _ _ _ _ _

a. delayed branchb. delayed loadc. delayed stored. delayed add

5. The RISC consists of only _ _ _ _ _ _ _ _ length instruction formata. variableb. fixedc. small numberd. large number

6. The data transfer instructions in RISC are limited to _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _ instructionsa. add, sub

b. mul, divc. load, store

d. in, out

7. Since all operands are in registers, there is no need for _ _ _ _ _ _ _ _ of operands from memorya. fetchb. decode

c. execute

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8. The concept of delaying the use of the data loaded from memory is referred to as _ _ _ _ _ _ _ _ _ _a. delayed branchb. delayed loadc. delayed store

d. delayed add

9. The compiler for a processor that uses delayed branches is designed to analyze the instructions _ _ _ _ _ _ _ _ _ _ brancha. before

b. afterc. before & afterd. later

0. A computer capable of vector processing eliminates the overhead associated with the time it takes to _ _ _ _ _ _ _

_ _ _ _ _ _ _ _ _ _ the instructions in the program loopa. fetch, decodeb. fetch, executec. execute, decode

d. fetch, store

1. A vector processor that uses an n-way interleaved memory can fetch _ _ _ _ _ _ _ _ _ _ _ operands from _ _ _ _ _ _ different modulesa. n, nb. n, m

c. 1, 1d. 1, 2

2. Matrix _ _ _ _ _ _ _ is one of the most computational intensive operations performed In computers with vectorprocessorsa. addition

b. subtractionc. transposed. multiplication

3. A computer with vector instructions and pipelined floating-point arithmetic operations is referred to as _ _ _ _ _ _

computera. minib. mainframec. super

d. micro

4. A measure used to evaluate computers in their ability to performs a given number of floating-point operations persecond is referred as _ _ _ _ _ _ _ _ _ _a. MIPS

b. KIPSc. FLOPS

d. BAUDS

5. _ _ _ _ _ _ _ _ _ _ processing deals with computations involving large matricesa. arithmetic

b. parallelc. pipelined. vector

6. Aerodynamics and space flight simulations uses _ _ _ _ _ _ _ _ _ _ processing

a. vectorb. arithmeticc. paralleld. pipeline

7. In _ _ _ _ _ _ _ memory, different sets of addresses are assigned to different memory modules

a. associateb. randomc. interleaved

d. multiple

8. A vector is an ordered set of _ _ _ _ _ _ _ _ _ dimensional array of data items

a. twob. threec. one

d. four

9. Instruction format for vector instruction is _ _ _ _ _ _ _ _ address instructiona. zerob. onec. two

d. three

0. One of the following _ _ _ _ _ _ _ _ _ system is an example for array processora. VAX



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b. PDP-11c. MPPd. ILLIAC-IV

1. Each processing element of SIMD will have _ _ _ _ _ _ _ _ _ memorya. global

b. sharedc. locald. temporary

2. An array processor consists of _ _ _ _ _ _ _ _ _ instructions and _ _ _ _ _ _ _ data organization

a. single, multipleb. multiple, singlec. single, single

d. multiple, multiple

3. The objective of the attached array processors is to provide _ _ _ _ _ _ _ _ capabilities to a conventional computer

a. high speedb. pipelinedc. parallel

d. vector manipulation

4. The function of the master control unit in SIMD processor is to _ _ _ _ _ _ _ _ _ _ _ the instruction

a. fetchb. decodec. execute

d. store

5. _ _ _ _ _ _ _ _ _ _ array processor is an auxiliary processor attached to a general purpose computera. attached

b. auxiliaryc. parallel

d. distributed

6. The attached processor is a _ _ _ _ _ _ _ _ machine driven by the host computer

a. front-endb. back-end

c. masterd. slave

7. Scalar and program controlled instructions are directly executed with in the _ _ _ _ _ _ unita. master control

b. memory

c. PEd. local memory

8. The system with the attached processor satisfies the needs for _ _ _ _ _ _ _ arithmetic applicationsa. complex

b. simple

c. scalard. vector

9. _ _ _ _ _ _ _ _ _ _ schemes are used to control the status of each PE during the execution

a. maskingb. blockingc. delayed

d. translation

0. The inter process communication mechanism used in loosely coupled system is _ _ _ _

a. pipesb. FIFOc. shared memory

d. message queues

1. Tightly coupled systems can tolerate a _ _ _ _ _ _ _ degree of interaction between tasks

a. nob. higherc. lower

d. minimal

2. Multiprocessing can improve performance by decomposing a program into _ _ _ _ _ _ _ executable tasksa. serialb. parallelc. multiple

d. several

3. _ _ _ _ _ _ _ _ technology has reduced the cost of computer components very much.a. SSI

b. MSIc. VLSI



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d. LSI

4. Multiprocessors are classified as multiple processor _ _ _ _ _ _ _ _ systemsa. SISDb. MIMDc. SIMD

d. MISD

5. _ _ _ _ _ _ _ _ _ architecture forms a computer networka. multiprocessorb. multi computer

c. single computerd. distributed computer

6. Each processor element in a _ _ _ _ _ _ _ _ _ system has its own private local memory

a. tightly coupledb. loosely coupled

c. time sharedd. multistage

7. The inter process communication mechanism used in tightly coupled system is _ _ _ _a. pipes

b. FIFO

c. shared memoryd. message queues

8. The _ _ _ _ _ _ _ _ _ _ interconnection is suitable for connecting small number of processorsa. cross bar

b. multiportc. multi stage

d. hypercube

9. The basic component of a multi stage network is a 2-input 2-output interchange _ _ _ _ _

a. crossbarb. connection point

c. switchd. hub

0. _ _ _ _ _ _ _ _ _ memory system employees separate buses between each memory module and each CPU

a. common busb. multiportc. crossbar

d. multistage switch

1. A three cube structure consists of _ _ _ _ _ _ _ nodesa. 1

b. 2c. 4

d. 8

2. _ _ _ _ _ _ _ _ _ consists of a number of points that are placed at intersections between processor buses and mempartsa. cross bar

b. multiportc. common busd. hypercube

3. _ _ _ _ _ _ _ _ _ is used to control the communication between a number of sources and destinationsa. cross bar

b. multiportc. commonbusd. multistage switch

4. The _ _ _ _ _ _ _ _ multiprocessor structure is a loosely coupled system with 2n processorsa. crossbar

b. multi portc. hypercubed. multistage switch

5. A single common bus system is restricted to transfer _ _ _ _ _ _ _ _ _ _ processor at a time

a. oneb. twoc. manyd. IOP

6. _ _ _ _ _ _ _ _ multiprocessor system consists of a number of processors connected through a common path to a

memory unita. common bus

b. multiportc. crossbar



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d. hypercube

7. The crossbar switch consists of _ _ _ _ _ _ _ _ _ _ _ _ devicesa. decoderb. encoderc. multiplexer

d. de-multiplexer

8. The IEEE 796 standard bus has _ _ _ _ _ _ _ _ data _ _ _ _ _ _ _ address and _ _ _ _ _ _ _ _ control linesa. 36,24,36b. 10,24,30

c. 16,24,26d. 16,20,20

9. _ _ _ _ _ _ _ _ _ _ _ _ must be performed to resolve multiple contention for the shared resources

a. arbitrationb. multiplexing

c. loopingd. controlling

0. The processor in a shared memory multiprocessor system request access to common memory through _ _ _ _ _ _ _a. system bus

b. internal bus

c. synchronized busd. asynchronus bus

1. The parallel bus arbitration technique uses _ _ _ _ _ _ _ _ priority encoders and decodersa. internal

b. maximumc. external

d. low

2. The _ _ _ _ _ _ _ _ _ _ _ _ _ algorithm gives the highest priority to the requesting device that has not used the bus

the longest intervala. polling

b. LRUc. FIFO

d. time slice

3. In _ _ _ _ _ _ _ _ bus , each data item is transferred during a time slice known to source and destination in advanca. serialb. parallel

c. synchronus

d. asynchronus

4. In serial arbitration procedure the device closest to the priority line is assigned _ _ _ _ _ _ _ priority

a. lowb. high

c. normal

d. no

5. The _ _ _ _ _ _ _ _ algorithm allocates a fixed length time slice of bus time to each processora. polling

b. LRUc. FIFOd. time slice

6. In the _ _ _ _ _ _ _ _ _ _ scheme , requests are served in the order receiveda. polling

b. LRUc. FIFOd. time slice

7. The _ _ _ _ _ _ _ _ _ _ sequence is normally programmable and as a result the selection priority can be altered undprogram control

a. pollingb. LRUc. FIFO

d. time slice

8. Out of the following which one is the hardware instruction to implement semaphorea. flagb. turnc. spin

d. test and set

9. To protect data from being changed simultaneously by 2 or more processors is called _ _ _ _ _ _ _ _ _ _a. protection

b. access matrixc. hiding



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d. mutual exclusion

0. _ _ _ _ _ _ _ _ _ _ _ _ _ is often used to indicate whether or not a processor is executing a critical sectiona. monitorb. spin lockc. semaphore

d. rendezbous

1. _ _ _ _ _ _ _ _ is the common communication mechanism used between processorsa. FIFOb. semaphore

c. shared memoryd. message queue

2. _ _ _ _ _ _ _ _ _ _ multiprocessor system memory is distributed among the processors and there is no shared mem

for passing informationa. tightly coupled

b. shared memoryc. loosely coupledd. specialized

3. A _ _ _ _ _ _ _ _ _ _ _ is a program sequence that once begun must complete execution before another processor a

the same shared resource

a. critical sectionb. entry sectionc. mutual exclusion

d. exit section

4. A scheme that allows writable data to exist in atleast one cache is a method that employees _ _ _ _ _ _ _ _ _ _ in icompiler

a. distributed local tableb. distributed global table

c. centralized local tabled. centralized global table

5. A memory scheme is _ _ _ _ _ _ _ _ _ _ _ _ _ _ if the value returned on a load instruction is always the value giventhe latest store instruction with the same address

a. conflictb. coherencec. concurrentd. coupling

6. The bus controller that monitors the cache coherence problem is referred as _ _ _ _ _ _ _

a. snoopy cache controllerb. split cache controllerc. direct cache controller

d. side cache controller

7. In _ _ _ _ _ _ _ _ mechanism both cache and main memory are updated with every write operation

a. write backb. write bothc. write through

d. write once

8. In _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ mechanism only the cache is updated and the location is marked so that it can be colater into main memory

a. write back

b. write bothc. write throughd. write once
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