coder and decoder in nfc device -...
TRANSCRIPT
2012/2/4 1
Coder and Decoder in NFC Device
王 心
2012/2/4 2
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 3
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 4
overview
CU
Decoder
DECMUXCRC
FIFO
Coder
CGM
PWM
CMP
RDM
2012/2/4 5
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 6
Code and modulate
Mode Speed Code Modulate Frequency Subcarrier
Target(A)/Initiator 106K bit/s Modified Miller ASK 100% fc/128
Target (A)/ Initiator 212K bit/s Manchester ASK 8%-30% fc/64
Target (A)/ Initiator 424K bit/s Manchester ASK 8%-30% fc/32
Target(P) 106K bit/s Manchester Load modulate
fc/16
Target(P) 212K bit/s Manchester Load modulate
fc/8
Target(P) 424K bit/s Manchester Load modulate
fc4
A—ActiveP—Passive
change clock frequency at different speed
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Modified Miller
SOF
logic 0 following 1 logic 0 following 0 or SOF logic 1
EOF following 1
EOF following 0
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Manchester
SOF (logic 1)
logic 1 logic 0
EOF
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Load modulate
BP
Demo
Ri
RFE
Magnetic Filed H
T
BB
Switch control
DATA
1 0
Subcarrier
Manchester Code
Subcarrier modulate
Load modulate
Switch
Target to Initiator
2012/2/4 10
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 11
coder
clkrstmoderate[1:0]rolesof_eneof_enst
signal
ack
datain
0
128/fc32/fc
1
0
128/fc64/fc
1
rate 00/01/10 106K/212K/424K
role 0/1 target/ initiator
mode 0/1 passive/active
Idle Sof
datain
sof_en
Code Eof
eof_en
Idle
ack
xxx bit0 bit1 bitn xxx
state
2012/2/4 12
Parity check in decoder
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity
No parity in short frame which has only 7 bits
Need to register the state of CU and the number of bit
byte structure in sdandard frame
SDD frame part1
SDD frame part2
use a counter to count thenumber of “1”If count[0]=Parity =>error
2012/2/4 13
Anti-Collision in decoder0
1
collision
need a collision flag to tell CUand register bit number
with different load modulation depth
with equivalent load modulation depth
2012/2/4 14
Clock interrupt in decoder
0 0 1101
xxxx 7'b11111110 0 5'b11111 0 5'b11111
yyyy xxxx 7'b1111111 5'b11111
0 xxx
5'b11111
Sequence_r1
Sequence_r2
Shift_en
2012/2/4 15
Decode strategy
Pre_data Sequence_r1 Sequence_r2 Current_data
sof 8'b00011111 1
sof 8'b00000111 0
1 8'b00000111 1
1 8'b00011111 0
0 8'b01111111 1
0 8'b00000111 0
2012/2/4 16
Interface definition of decoder
clkrstmoderate[1:0]role
sof_flageof_flag
st
dataout
collision
signal
parityc_bit
bety_cpli
Idle Sof
dataout
sof_flag
Decode Eof
eof_flag
Idle
collision
xxx bit0 bit1bit7
11xxx
state
bit8
parity
2012/2/4 17
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 18
Coder
106K Initiator to Target 101001101
106K Target to Initiator 101001101
2012/2/4 19
Decoder in initiator
Parity error
Collision
2012/2/4 20
Decoder in target
Parity error
Decode successfully
2012/2/4 21
Agenda
Overview Frame structure Design detail (problem and solution) Simulation result Conclusion
2012/2/4 22
Conclusion
Design the coder and decoder of NFC device witch operate in P2P mode
Decoder support anti_collision and parity Solve the problem of clock interrupt when
100% modulation depth used
2012/2/4 23
Thank you !
Q&A