codigod2

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.all;

ENTITY SUMA1 IS

PORT

(

cin : IN STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

cout : OUT STD_LOGIC ;

result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END SUMA1;

ARCHITECTURE SYN OF suma1 IS

SIGNAL sub_wire0 : STD_LOGIC ;

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);

COMPONENT lpm_add_sub

GENERIC (

lpm_direction : STRING;

lpm_hint : STRING;

lpm_representation : STRING;

lpm_type : STRING;

lpm_width : NATURAL

);

PORT (






);

END COMPONENT;

BEGIN

cout <= sub_wire0;

result <= sub_wire1(3 DOWNTO 0);

LPM_ADD_SUB_component : LPM_ADD_SUB

GENERIC MAP (

lpm_direction => "ADD",

lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",

lpm_representation => "UNSIGNED",

lpm_type => "LPM_ADD_SUB",

lpm_width => 4

)

PORT MAP (

cin => cin,

datab => datab,

dataa => dataa,

cout => sub_wire0,

result => sub_wire1

);

END SYN;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY RESTA1 IS

PORT

(






);

END RESTA1;

ARCHITECTURE SYN1 OF resta1 IS




GENERIC (


lpm_hint : STRING;


lpm_type : STRING;

lpm_width : NATURAL

);

PORT (






);

END COMPONENT;

BEGIN

cout <= sub_wire0;



GENERIC MAP (

lpm_direction => "SUB",




lpm_width => 4

)

PORT MAP (

cin => cin,

datab => datab,

dataa => dataa,

cout => sub_wire0,

result => sub_wire1

);

END SYN1;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY INC IS

PORT

(






);

END INC;

ARCHITECTURE SYN2 OF INC IS




GENERIC (


lpm_hint : STRING;


lpm_type : STRING;

lpm_width : NATURAL

);

PORT (






);

END COMPONENT;

BEGIN

cout <= sub_wire0;



GENERIC MAP (

lpm_direction => "ADD",




lpm_width => 4

)

PORT MAP (

cin => cin,

datab => "0001",

dataa => dataa,

cout => sub_wire0,

result => sub_wire1

);

END SYN2;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY DEC IS

PORT

(






);

END DEC;

ARCHITECTURE SYN3 OF DEC IS




GENERIC (


lpm_hint : STRING;


lpm_type : STRING;

lpm_width : NATURAL

);

PORT (






);

END COMPONENT;

BEGIN

cout <= sub_wire0;



GENERIC MAP (

lpm_direction => "SUB",




lpm_width => 4

)

PORT MAP (

cin => cin,

datab => "0001",

dataa => dataa,

cout => sub_wire0,

result => sub_wire1

);

END SYN3;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY MULT1 IS

PORT

(




);

END MULT1;

ARCHITECTURE SYN4 OF mult1 IS


COMPONENT lpm_mult

GENERIC (

lpm_hint : STRING;


lpm_type : STRING;

lpm_widtha : NATURAL;

lpm_widthb : NATURAL;

lpm_widthp : NATURAL

);

PORT (




);

END COMPONENT;

BEGIN


lpm_mult_component : lpm_mult

GENERIC MAP (

lpm_hint => "MAXIMIZE_SPEED=5",


lpm_type => "LPM_MULT",

lpm_widtha => 4,

lpm_widthb => 4,

lpm_widthp => 4

)

PORT MAP (

dataa => dataa,

datab => datab,

result => sub_wire0

);

END SYN4;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY DIV1 IS

PORT

(

denom : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

numer : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

quotient : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

remain : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END DIV1;

ARCHITECTURE SYN5 OF div1 IS



COMPONENT lpm_divide

GENERIC (

lpm_drepresentation : STRING;

lpm_hint : STRING;

lpm_nrepresentation : STRING;

lpm_type : STRING;

lpm_widthd : NATURAL;

lpm_widthn : NATURAL

);

PORT (





);

END COMPONENT;

BEGIN

quotient <= sub_wire0(3 DOWNTO 0);

remain <= sub_wire1(3 DOWNTO 0);

LPM_DIVIDE_component : LPM_DIVIDE

GENERIC MAP (

lpm_drepresentation => "UNSIGNED",

lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",

lpm_nrepresentation => "UNSIGNED",

lpm_type => "LPM_DIVIDE",

lpm_widthd => 4,

lpm_widthn => 4

)

PORT MAP (

denom => denom,

numer => numer,

quotient => sub_wire0,

remain => sub_wire1

);

END SYN5;

LIBRARY ieee;


LIBRARY lpm;

USE lpm.all;

ENTITY COMP1 IS

PORT

(



aeb : OUT STD_LOGIC ;

agb : OUT STD_LOGIC ;

alb : OUT STD_LOGIC

);

END COMP1;

ARCHITECTURE SYN6 OF comp1 IS




COMPONENT lpm_compare

GENERIC (


lpm_type : STRING;

lpm_width : NATURAL

);

PORT (




alb : OUT STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END COMPONENT;

BEGIN

aeb <= sub_wire0;

agb <= sub_wire1;

alb <= sub_wire2;

LPM_COMPARE_component : LPM_COMPARE

GENERIC MAP (


lpm_type => "LPM_COMPARE",

lpm_width => 4

)

PORT MAP (

datab => datab,

dataa => dataa,

aeb => sub_wire0,

agb => sub_wire1,

alb => sub_wire2

);

END SYN6;

library ieee;


entity MUT1 is

port

(

D: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

E: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

F: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

G: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

H: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

J: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

S00 :IN STD_LOGIC_VECTOR (2 DOWNTO 0);

SALMU :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

end MUT1;

architecture MULTI1 of MUT1 is

begin

PROcess(D,E,F,G,H,I,J,S00)

BEGIN

IF S00="000" THEN SALMU <=D;

ELSif S00="001" THEN SALMU <=E;

ELSif S00="010" THEN SALMU <=F;

ELSif S00="011" THEN SALMU <=G;

ELSif S00="100" THEN SALMU <=H;

ELSif S00="101" THEN SALMU <=I;

ELSif S00="110" THEN SALMU <=J;

END IF;

END PROcess;

end MULTI1;

library ieee;


entity bloque_arit is

port

(


A1 : in std_logic_vector (3 downto 0);

B1 : in std_logic_vector (3 downto 0);

S00 : in std_logic_vector (2 downto 0);

-- Output ports

sol : out std_logic_vector (3 downto 0);

cout0 : OUT STD_LOGIC;




remain : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);



alb : OUT STD_LOGIC

);

end bloque_arit ;

architecture aritm of bloque_arit is

component suma1

PORT

(






);

end component;

component resta1

PORT

(






);

end component;

component inc

PORT

(






);

end component;

component dec

PORT

(






);

end component;

component mult1

PORT

(




);

end component;

component div1

PORT

(





);

end component;

component comp1

PORT

(





alb : OUT STD_LOGIC

);

end component;

COMPONENT MUT1

PORT

(D: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

E: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

F: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

G: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

H: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

J: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

S00 :IN STD_LOGIC_VECTOR (2 DOWNTO 0);

SALMU :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END COMPONENT;

SIGNAL D,E,F,G,H,I,j : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

U1:SUMa1 port map(cin,A1,b1,cout0,D);

U2:RESTa1 port map(cin,a1,b1,cout1,E);

U3:INC port map(cin,a1,b1,cout2,F);

U4:DEC port map(cin,a1,b1,cout3,G);

U5:MULT1 port map(a1,b1,H);

U6:DIV1 port map(B1,a1,I,remain);

U7:COMP1 port map(a1,b1,aeB,agB,alB);

U8:MUT1 port map(D,E,F,G,H,I,j,s00,sol);

end aritm;

library ieee;

use ieee.std_logic_1164.all;

entity bloque_logico is

port

(

-- Input ports

AA : in std_logic_vector (3 downto 0);

BB : in std_logic_vector (3 downto 0);


-- Output ports

SOL_LOGIC : out std_logic_vector (3 downto 0)

);

end bloque_logico;

architecture logic of bloque_logico is

begin

process(AA,BB,S00)

begin

if (S00="000")then SOL_LOGIC <= AA and BB;

elsif(S00="001")then SOL_LOGIC <= not(AA and BB);

elsif (S00="010")then SOL_LOGIC <= AA or BB;

elsif(S00="011")then SOL_LOGIC <= not(AA or BB);

elsif (S00="100")then SOL_LOGIC <= AA xor BB;

elsif(S00="101")then SOL_LOGIC <= not(AA xor BB);

elsif(S00="110")then SOL_LOGIC <= not(AA);

elsif(S00="111")then SOL_LOGIC <= not(BB);

end if;

end process;

end logic;

library ieee;

use ieee.std_logic_1164.all;

entity MUT2 is

port

(

-- Input ports

ENT_A : in STD_LOGIC_VECTOR (3 DOWNTO 0);

ENT_B : in STD_LOGIC_VECTOR (3 DOWNTO 0);

S1 : IN STD_LOGIC;

-- Output ports

SAL : out STD_LOGIC_VECTOR (3 DOWNTO 0)

);

end MUT2;

architecture MUT22 of MUT2 is

begin

PROcess(ENT_A,ENT_B,S1)

BEGIN

IF S1='0' THEN SAL <= ENT_A;

ELSE SAL <= ENT_B;

END IF;

END PROcess;

end MUT22;

LIBRARY ieee;


entity ALUlab5 is

port

(


A : in std_logic_vector (3 downto 0);

B : in std_logic_vector (3 downto 0);


S11 : IN STD_LOGIC;

-- Output ports









alb : OUT STD_LOGIC

);

end ALUlab5;

architecture ALU of ALUlab5 is

COMPONENT BLOque_logico

port

(

-- Input ports

AA : in std_logic_vector (3 downto 0);

BB : in std_logic_vector (3 downto 0);


-- Output ports

SOL_LOGIC : out std_logic_vector (3 downto 0)

);

END COMPONENT;

COMPONENT bloque_arit

port

(


A1 : in std_logic_vector (3 downto 0);

B1 : in std_logic_vector (3 downto 0);


-- Output ports









alb : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT MUT2

PORT(

-- Input ports

ENT_A : in STD_LOGIC_VECTOR (3 DOWNTO 0);

ENT_B : in STD_LOGIC_VECTOR (3 DOWNTO 0);

S1 : IN STD_LOGIC;

-- Output ports

SAL : out STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END COMPONENT;

SIGNAL X,Y : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

V1:bloque_arit PORT MAP (CIN,A,B,S0,x,COUt0,cout1,cout2,cout3,remain,AeB,AgB,AlB);

V2:BLOque_logico PORT MAP (A,B,S0,y);

V3:MUT2 PORT MAP (X,Y,S11,sol);

end ALU;

codigod2

Documents