coe 308 term - 052 dr abdelhafid bouhraoua term - 052 dr abdelhafid bouhraoua

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COE COE 308 308 Term - 052 Term - 052 Dr Abdelhafid Bouhraoua Dr Abdelhafid Bouhraoua

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COE COE 308308COE COE 308308Term - 052Term - 052

Dr Abdelhafid BouhraouaDr Abdelhafid BouhraouaTerm - 052Term - 052

Dr Abdelhafid BouhraouaDr Abdelhafid Bouhraoua

InstructorInstructor

Dr Abdelhafid BouhraouaDr Abdelhafid Bouhraoua

Office Hours:Office Hours: Sat. Mon. Wed. 9:00 - 11:00 AMSat. Mon. Wed. 9:00 - 11:00 AM

Office Location:Office Location: Bldg 22 Office 137-3Bldg 22 Office 137-3

Phone:Phone: 21782178

Email:Email: [email protected] page:Web page: www.ccse.kfupm.edu.sa/~abouh

SyllabusSyllabus

Course ObjectivesCourse Objectives

• To introduce students to the techniques used To introduce students to the techniques used to enhance the performance of computer to enhance the performance of computer architecture including memory hierarchy, architecture including memory hierarchy, pipelining, and parallelism, pipelining, and parallelism,

• To introduce students to the trade-off analysis To introduce students to the trade-off analysis in the design of various aspects of Computer in the design of various aspects of Computer Architecture including Instruction Set Design, Architecture including Instruction Set Design, Memory Hierarchy, Instruction Level Pipeline, Memory Hierarchy, Instruction Level Pipeline, and Multiprocessingand Multiprocessing

Course Outcome (1)Course Outcome (1)

• Discuss how various architectural enhancements and Discuss how various architectural enhancements and instructions sets have evolved and their effects on instructions sets have evolved and their effects on system performance.system performance.

• Understand the design of arithmetic units and their Understand the design of arithmetic units and their impact on overall performance.impact on overall performance.

• Explain the effect of memory latency and bandwidth on Explain the effect of memory latency and bandwidth on performance.performance.

• Explain the use of memory hierarchy to reduce the Explain the use of memory hierarchy to reduce the effective memory latency, and understand the design effective memory latency, and understand the design tradeoffs in hierarchical memories and its impact on tradeoffs in hierarchical memories and its impact on performanceperformance..

• Describe the principles of memory management.Describe the principles of memory management.

Course Outcome (2)Course Outcome (2)

• Discuss how pipelining and parallelism can be applied Discuss how pipelining and parallelism can be applied to the design of scalar and superscalar processors, to the design of scalar and superscalar processors, and can perform speed-up analysis.and can perform speed-up analysis.

• Be able to identify the problems and hazards that arise Be able to identify the problems and hazards that arise in pipelined processors and identify their in pipelined processors and identify their corresponding solutions. corresponding solutions.

• Appreciate the problems caused by cache coherency Appreciate the problems caused by cache coherency in shared and distributed memories and understand in shared and distributed memories and understand the ways in which the problem can be overcomethe ways in which the problem can be overcome

• Describe the limitations imposed by interconnections Describe the limitations imposed by interconnections and memory on multiprocessing systems, and and memory on multiprocessing systems, and understand design tradeoffsunderstand design tradeoffs

TextbookTextbook

Computer Organization & Design – The Hardware/Software InterfaceComputer Organization & Design – The Hardware/Software InterfaceDavid A. Patterson and John L. Hennessy, Third Edition, Morgan Kaufmann, 2005David A. Patterson and John L. Hennessy, Third Edition, Morgan Kaufmann, 2005

Exams and AssignmentsExams and Assignments

5-6 5-6 Written Written AssignmentsAssignments

4-54-5 QuizzesQuizzes22 Major ExamsMajor Exams11 Final ExamFinal Exam

Grading Policy (1)Grading Policy (1)

Quizzes and AssignmentsQuizzes and Assignments 20 %20 %

ProjectProject 15 %15 %

Major Exam 1Major Exam 1 20 %20 %

Major Exam 2Major Exam 2 20 %20 %

Final ExamFinal Exam 25 %25 %

Lowest 2, 3 or 4 marks of the quizzes and assignments dropped

Grading Policy (2)Grading Policy (2)

• Assignments are to be submitted in class Assignments are to be submitted in class or by email in the specified due date.or by email in the specified due date.

• Late assignments will be accepted for five Late assignments will be accepted for five days after the due date and be penalized days after the due date and be penalized 10% per each late day10% per each late day

Lecture BreakdownLecture Breakdown

Introduction and PerformanceIntroduction and Performance 1.5 week1.5 week

Computer ArithmeticComputer Arithmetic 2 weeks2 weeks

MIPS Instruction SetMIPS Instruction Set 1 week1 week

Datapath and ControlDatapath and Control 2 weeks2 weeks

Pipeline Design TechniquesPipeline Design Techniques 3 weeks3 weeks

Memory System DesignMemory System Design 3 weeks3 weeks

I/O and BusesI/O and Buses 1 week1 week

MultiprocessorsMultiprocessors 2 weeks2 weeks

Ethics (1)Ethics (1)

• All assignments are individual and All assignments are individual and ONLYONLY individual work will be accepted. individual work will be accepted.

• Detected copies of assignments (written or Detected copies of assignments (written or programming assignments) will result in programming assignments) will result in ZEROSZEROS for the whole group (including the for the whole group (including the student who actually solved the problem)student who actually solved the problem)

Ethics (2)Ethics (2)

• Using unauthorized information or notes on an Using unauthorized information or notes on an examination, peeking at others work, or altering examination, peeking at others work, or altering a graded exam to claim more grades are severe a graded exam to claim more grades are severe violations of academic honesty. violations of academic honesty.

• Remember that if you Remember that if you CHEATCHEAT, you are cheating , you are cheating no one no one butbut yourself. yourself.

• Detected situations will result in failing grades in Detected situations will result in failing grades in the course, and depending on the severity of the the course, and depending on the severity of the situation, some cases may possibly end up in situation, some cases may possibly end up in SUSPENSIONSUSPENSION from the university. from the university.