COEN 180

SRAM

SRAM

High-speed Low capacity Expensive

Large chip area. Continuous power use to maintain

storage Technology used for making MM

caches

SRAM

Single cell stores single bit. 4T+2R design (old) 6T design

SRAM

4T+2R

SRAM Word line

Asserted: connects to complementary bit lines.

Resistor-Transistor pair divide voltage between Vcc and GND

T2 high resistance: A close to VCC

T2 low resistance A close to Gnd.

SRAM

A

T2 high impedance: A close to VCC

T3 enabled T3 low impedance B close to Gnd

T2 low impedance A close to Gnd. T3 disabled T3 high impedance B close to VCC

SRAM

A

B

SRAM

Two stable states. Asserted word line

sends complimentary values to the two bit lines. This is the stored bit. Bitline 0 contains bit Bitline 1 contains

inverse of bit

SRAM There is always a

current through one of the transistor-resistor pairs.

Use transistors instead of resistors to save energy.

However, transistors can use up more space.

SRAM

Cell consists of two lines of transistors, dividing the voltage between VCC and GND

Cross-coupled. T2 in high impedance

T5 in low impedance T2 in low impedance

T5 in high impedance

Assume T2 high impedance, T5 low impedance. Point A ~ VCC

T3 in low impedance and T6 in high impedance

Point B ~ GND T2 in high impedance, T5

low impedance. Stable State

SRAM

A

B

Assume T2 low impedance, T5 high impedance. Point A ~ GND T3 in high impedance and

T6 in low impedance Point B ~ GND T2 in low impedance, T5

high impedance. Stable State

SRAM

A

B

SRAM

6T cell is in two stable states.

If the word line is asserted, complementary values are placed on the two bit lines.

SRAM

Bit cells are arranged in a large memory array.

Address is divided into row address and column address.

SRAM Data access

Split address into row address (N bits) and column address (M bits).

Row address activates one of 2N word lines leading into the array.

This puts the contents of all 2M bit cells in that row onto the 2M column lines.

Each column line consists of two bit complementary bit lines.

Use a sense amplifier in order to remove any signal loss (because of capacitance of bit line).

Column decoder selects one of these bit lines and gates them into the I/O buffer.

SRAM

SRAM

Write access Everything as before. However:

Value in Read / Write Circuit overwhelms contents in the two bitlines.

This switches the state of the one selected bit cell.

SRAM Typical SRAM

array allows access to more than a single bit in parallel.

SRAM

SRAM

Faster: Faster chip technology Tighter chip technology Use different materials (GaAs) Increase voltages Cool circuit Change pinout to cut input / output

noise.

SRAM Faster

Can use input buffer to latch data. Access parameters:

Read-access time Propagation delay from the time when the

address is presented at the chip to the time data is available at the output.

Cycle time Minimum time between initiation of a read

operation and the initiation of another operation.