co_it_gate.pdf

IT DEPARTMENT GATE MATERIAL

COMPUTER ORGANIZATION

Question. 1

YEAR 2001 More than one word are put in one cache block to (A) Exploit the temporal locality of reference in a program (B) Exploit the spatial locality of reference in a program (C) Reduce the miss penalty (D) None of the above

SOLUTION Cache is the small memory which has a very less access time. So it is used for temporal locality of

reference whereas virtual memory is for spatial locality of reference. Hence (A) is correct option.

Question. 2 A low memory can be connected to 8085 by using (A) INTER (B) RESET IN (C) HOLD (D) READY

SOLUTION memory can be connected to 8085 by using READY signal. If READY is set then communication is

possible.Hence (D) is correct option.

Question. 3 Suppose a processor does not have any stack pointer register. Which of the following statements is true ? (A) It cannot have subroutine call instruction (B) It can have subroutine call instruction, but no nested subroutine calls. (C) Nested subroutine calls are possible, but interrupts are not. (D) All sequences of subroutine calls and also interrupts are possible

SOLUTION Stack pointer register holds the address of top of stack, which is the location of memory at which the


CPU should resume its execution after servicing some interrupt or subroutine call. So if SP register not available then no subroutine call instructions are possible. Hence (A) is correct option.

Question. 4 A processor needs software interrupt to (C) Test the interrupt system of the processor. (D) Implement co-routines. (E) Obtain system services which need execution of privileged instructions. (F) Return from subroutine. SOLUTION A CPU needs software interrupt to obtain system services which need execution of privileged

instructions. Hence (C) is correct opton.

Question. 5 A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to

non-privileged. (A) A hardware interrupt is needed.

(A) A software interrupt is needed. (B) A privileged instruction (which does not generate an interrupt) is needed. (C) A non-privileged instruction (Which does not generate an interrupt) is needed. SOLUTION A software interrupt is initiated by some program module which need some CPU services, at that time

the two modes can be interchanged. Hence (B) is correct option.

Question. 6 The process of assigning load addresses to the various parts of the program and adjusting the code and

date in the program to reflect the assigned addresses is called (A) Assembly (B) Parsing (C) Relocation (D) Symbol resolution


SOLUTION Load addresses are assigned to various parts of the program, the program can be loaded at any location

in memory. This location is added to all addresses in the code, to get correct references. This makes a code re-locatable. Hence (C) is correct option.

Question. 7 Which of the following requires a device driver ? (A) Register (B) Cache (C) Main memory (D) Disk

SOLUTION Device driver is the program which co-ordinates with CPU to regulate the devices. Register, cache &

main memory are directly connected to CPU. So only Disk from given options require device drivers. Hence (D) is correct option.

Question. 8 Which is the most appropriate match for the items in the first column with the items in the second

column (X.) Indirect Addressing (I.) Array implementation (Y.) Indexed Addressing (II.) Writing re-locatable code (Z.) Base Register Addressing (III.) Passing array as parameter

(A) (X, III) (Y, I) (Z, II) (B) (X, II) (Y, III) (Z, I) (C) (X, III) (Y, II) (Z, I) (D) (X, I) (Y, III) (Z, II) SOLUTION Indexed addressing is used for array implementation where each element has indexes. Base register is

used to re-locatable code, where starts from base address & then all local addresses as added to base

address. Indirect addressing is done when array is passed as parameter only name is passed. Hence (A) is correct option. Question. 9 Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR the

bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 X (2:1) and the

DEMUX is of size 8 X (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR


(Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction push r, where = A or B, has the specification

M [ SP] !r

SP ! SP 1 How many CPU clock cycles are needed to execute the push r instruction ? (A) 2 (B) 3

(C) 4 (D) 5

SOLUTION Push r Consist of following operations

M [ SP] !r SP ! SP 1

r is stored at memory at address stack pointer currently is, this take 2 clock cycles. SP is then decremented to point to next top of stack. So total cycles = 3 Hence (B) is correct option. Question. 10 Which of the following does not interrupt a running process ? (A) A device (B) Timer (C) Scheduler process (D) Power failure

SOLUTION A device can request interrupt service. A timer when finishes or power failure causes a running process


to stop. But a scheduler process doesnt do this. Hence (C) is correct option.

YEAR 2002

Question. 11 A device employing INTR line for device interrupt puts the CALL instruction on the data bus while (A) INTA is active (B) HOLD is active (C) READY is active (D) None of the above

LUTION INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal

& activates INTA signal, so another request cant be accepted till CPU is busy in servicing interrupt. Hence (A) is correct option.

Question. 12 In 8085 which of the following modifies the program counter ? (A) Only PCHL instruction (B) Only ADD instructions (C) Only JMP and CALL instructions (D) All instructions SOLUTION Program counter is the register which has the next location of the program to be executed next. JMP &

CALL changes the value of PC. PCHL instruction copies content of registers H & L to PC. ADD instruction after completion increments program counter. So program counter is modified in all

cases. Hence (D) is correct option.

Question. 13 In serial data transmission, every byte of data is padded with a 0 in the beginning and one or two 1s

at the end of byte because (A) Receiver is to be synchronized for byte reception (B) Receiver recovers lost 0s and 1 from these padded bits (C) Padded bits are useful in parity computation.


(D) None of the above

SOLUTION In serial data transmission the sender & receiver needs to be synchronized with each other. Receiver

should know when 1 byte of data has been sent. 0 & 1s which are padded tell the receiver to

synchronize. Hence (A) is correct option.

uestion. 14 Which of the following is not a form of memory ? (A) Instruction cache (B) Instruction register (C) Instruction opcode (D) Translation-a-side buffer SOLUTION Instruction register stores instruction, look-a-side buffer & instruction cache are also memory. But instruction opcodes are the opcodes related to an instruction which are not part of memory

hierarchy. Hence (C) is correct option.

Question. 15 In the C language (1) At most one activation record exists between the current activation record and the activation record

for the main. (2) The number of activation records between the current activation record and the activation record for

the main depends on the actual function calling sequence. (3) The visibility of global variables depends on the actual function calling sequence. (4) Recursion requires the activation record for the recursive function to be saved on a different stack

before the recursive fraction can be called. SOLUTION Activation record is the contiguous memory locations where the data needed by the program is kept so

at most one activation record exist between current activation record & the record for the main. Hence (A) is correct option.

Question. 16


In the absolute the addressing mode (A) The operand is inside the instruction (B) The address of the operand is inside the instruction (C) The register containing the address of the operand is specified

nside the instruction (D) The location of the operand is implicit

SOLUTION In absolute addressing mode, no need of giving operand, the operand are implicit, instruction itself has

knowledge of operands. Hence (D) is correct option.

Question. 17 The performance of a pipelined processor suffers if (A) The pipelined stages have different delays (B) Consecutive instructions are dependent on each other (C) The pipeline stages share hardware resources (D) All the above

SOLUTION Pipelining is a method to execute a program breaking it in several independent sequence of stages. In that case pipeline stages cant have different delays, no dependency among consecutive instructions

& sharing of hardware resources shouldnt be there. So option (D) is true Hence (D) is correct option.

Question. 18 Horizontal microprogramming t Does not require use of signal decoders t Results in larger sized microinstructions than vertical microprogramming t Uses one bit for each control signal t All of the above

SOLUTION


In horizontal microprogramming the instruction size is not large, & no

decoding is required. But 1 bit is used for all control signals. Hence (C) is

correct option.

YEAR 2003 Question. 19 For a pipelined CPU with a single ALU, consider the following situations 1. The j + 1 st instruction uses the result of j th instruction as an operand 2. The execution of a conditional jump instruction 3. The j th and j + 1 st instructions require the ALU at the same time Which of the above can cause a hazard? (A) 1 and 2 only (B) 2 and 3 only (C) 3 only (D) All the three SOLUTION Case 1 is here of data dependency, this cant be safe with single ALU so

read after write. Case 2 Conditional jumps are always hazardous they create conditional

dependency in pipeline Case 3 This is write after read problem or concurrency dependency so

hazardous All the three are hazardous.

Hence (D) is correct option.

Question. 20 Consider an array multiplier for multiplying two n bit numbers. If each

gate in the circuit has a unit delay, the total delay of the multiplier is (A) (1) (B) (log n) (C) (n) (D) (n2) SOLUTION The no. of gates used in n bit array multiplier (n X n) is 2n 1. So. if every single gate takes unit delay, then total delay 0(2n 1) = 0(n) It is of linear order Hence (C) is correct option.


Question. 21 Consider the ALU shown below If the operands are in 2s complement representation, which of the following operations can be

performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction

respectively)? (A) A + B, and A B,but notA + 1 (B) A + B,and A + 1,but notA B (C) A + B,but not A B,orA + 1 (D) A + B,and A B,andA + 1

SOLUTION This is the ckt to add two numbers in 2s complement form. K & C0 are set to 1. So A + B & A B using

bit adders can be done. Also since C0 = 1 & in case B 0, B1........ all are 0 then it gives A + 1. Hence (D) is correct option.

Data for Q. 22 & 23 are given below. Consider the following assembly language program for a hypothetical processor. A,B and C are 8 bit

registers. The meanings of various instructions are shown as comments.

MO

V B, # 0 ; B!0

MO

V C, # 8 ; C!8

Z: CMP C, # 0 ; compare C with 0 JZX ; jump to X if zero flag is set

SUB C, # 1 ; C!C1


RRC A, # 1 ; right rotate A through carry

; by one bit. Thus: if the

; initial values of A and the

; carry flag are a7 ....... a0 and c0

; respectively, their values

; after the execution of this

; instruction will be c0 a7 .....a1

JCY

; and a0 respectively.

;jump to Y if carry flag is set

JMP Z ; jump to Z

Y: ADD B, # 1 ; B!B+1

JMP Z ; jump to Z

X:

Question. 22 If the initial value of register A is A0, the value of register B after the

program execution will be (A) the number of 0 bits in A0 (B) the number of 1 bits in A (C) A0 (D) 8

SOLUTION Here value of B incremented by 1 only if carry flag is 1, carry is filled

using right rotation, so B will store the no. of is in A0. Hence (B) is correct option. Question. 23 Which of the following instructions when inserted at location X will

ensure that the value of register A after program execution is the same as

its initial value? (A) RRC A,# 1

(B) NOP ; no operation

(C) LRC A, # 1 ; left rotate A through carry flag by one bit


(D) ADD A, # 1


SOLUTION In the end of program execution to check whether both initial and final value of register A is A0, we need

to right rotate register A through carry by one bit. Hence (A) is correct option.

YEAR 2004

Question. 24 Which of the following addressing modes are suitable for program relocation at run time? 1. Absolute addressing 2. Based addressing 3. Relative addressing 4. Indirect addressing (A) 1 and 4 (B) 1 and 2 (C) 2 and 3 (D) 1,2 and 4

SOLUTION Program relocation at run time transfers complete block to some memory locations. This require as base

address and block should be relatively addressed through this base address. This require both based addressing and relative addressing mode. Hence (C) is correct option.

Question. 25 Consider a multiplexer with X and Y as data inputs and Z as control input.Z = 0 selects input X , and Z =1

selects input Y . What are the connection required to realize the 2-variable Boolean function f = T + R, without using any additional hardware? (A) R to X, 1 to Y, T to Z (B) T to X, R to Y, T to Z (C) T to X, R to Y, 0 to Z (D) R to X, 0 to Y, T to Z


SOLUTIO

N

We require f = T + R We have MUX equation

f = Z' x + zy Now if we make following ckt

Truth table

R T F Z

0 0 0 0

0 1 1 1

1 0 1 0

1 1 1 1

Hence (A) is correct option.

So X = R Y = 1 Z = T

f = T ' R + T

= (T + T ')(T + R) f = T + R


Data for Q. 26 & 27 are given below.

Consider the following program segment for a hypothetical CPU having

three user registers R1,R2 and R3.


Question. 26 Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting

from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after

executing the HALT instruction, the return address (in decimal) saved in the stack will be (A) 1007 (B) 1020

(C) 1024 (D) 1028

SOLUTION Byte addressable so 1 word require 4 bytes.

Instruction no. Size Address range

1 2 1000-1007

2 1 1008-1011

3 1 1012-1015

4 2 1016-1023

5 1 1024-1027 Next location 1028. CPU has executed the HALT instruction so next time the CPU will resume at next location i.e. 1028

which would be at the top of stack.

Hence (D) is correct option. Question. 27 Let the clock cycles required for various operations be as follows: Register to/from memory transfer: 3 clock cycles

Instruction Operation Instruction Size

(in words)

MOV R1,5000 ;R1Memory[5000] 2

MOV R2,R3 ;R2R2+R3 1

ADD R2,R3 ;R2R2+R3 1

MOV 6000,R2 ;Memory[6000]R2 2

HALT ;Machine halts 1


ADD with both operands in register: 1 clock cycle Instruction fetch and decode: 2 clock cycles per word The total number of clock cycles required to execute the program is (A) 29 (B) 24

(C) 23 (D) 20

SOLUTION The clock cycles are per block so if an instruction size is 2 then it requires

twice no. of clock cycles.

Instruction No. Size No. of clock cycles

1 2 3 X 2 + 2 8

2 1 1 X 3 + 2 5

3 1 1(add only) 1

4 2 3 X 2 + 2 8

5 1 2(fetch & decode) 2

Total 24

Hence (B) is correct option. Question. 28 Consider a small two-way set-associative cache memory, consisting of

four blocks. For choosing the block to be replaced, use the least recently

used (LRU) scheme. The number of cache misses for the following

sequence of block addresses is 8, 12,0, 12,8 (A) 2 (B) 3

(C) 4 (D) 5

SOLUTION


After than 12 & 8 are referred but this does not cause any miss So no. of miss = 3 This stars ()) shows the misses. Hence (B) is correct option.

Question. 29 The microinstructions stored in the control memory of a processor have a width of 26 bits. Each

microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X),

and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of

words? (A) 10, 3, 1024 (B) 8, 5, 256

(C) 5, 8, 2048 (D) 10, 3, 512

SOLUTION MUX has 8 states bits as input lines so we require 3 select inputs to select & input lines. No. of bits in control memory next address field

= 26 13 3

= 10 10 bit addressing, we have 210 memory size. So X, Y size = 10,3,1024 Hence (A) is correct option. Question. 30 A hard disk with a transfer rate of 10 M bytes/second is constantly


transferring data to memory using DMA. The processor runs at 600 MHz.

and takes 300 and 900 clock cycles to initiate and complete DMA transfer

respectively. If the size of the transfer is 20 Kbytes, what is the percentage

of processor time consumed for the transfer operation? (A) 5.0% (B) 1.0%

(C) 0.5% (D) 0.1%

SOLUTION

Transfer rate = 10 MB ps

Data = 20 KB

Time = 20 X210 = 2 X 103

10 X 220

= 2 ms

Processor speed = 600 MHz

= 600 cycles/sec.

Cycles required by CPU = 300 + 900

For DMA = 1200

So time =

1200

= .002 ms

600 X 106

% = .002 X 100

2

= 0.1%

Hence (D) is correct.

Question. 31 A 4-stage pipeline has the stage delays as 150, 120, 160 and 140

nanoseconds respectively. Registers that are used between the stages have

a delay of 5 nanoseconds each. Assuming constant clocking rate, the total

time taken to process 1000 data items on this pipeline will be (A) 120.4 microseconds (B) 160.5 microseconds (C) 165.5 microseconds (D) 590.0 microseconds SOLUTION

Delay = 5 ns/stage Total delay in pipline.


= 150 + 120 + 160 + 140 = 570 Delay due to 4 stages. Stage 1 delay 1 stage 2 delay 2 stage 3 stage 4 5 X 3 = 15

Total = 570 + 15 = 585

Total time =

1000 data items 585 ns

= 165.5 microseconds. Hence (C) is correct option

YEAR 2005

Question. 32 Which one of the following is true for a CPU having a single interrupt request line and a single interrupt

grant line? (A) Neither vectored interrupt nor multiple interrupting devices are possible (B) Vectored interrupts are not possible but multiple interrupting devices are possible (C) vectored interrupts and multiple interrupting devices are both possible (D) vectored interrupt is possible but multiple interrupting devices are not possible SOLUTION CPU has single interrupt request and grant line

Here multiple request can be given to CPU but CPU interrupts only for highest priority interrupt so

option (A) & (D) are wrong. But here in case of single interrupt lines definitely vectored interrupts are not possible. Hence (B) is correct option.


Question. 33 Normally user programs are prevented from handing I/O directly by I/O

instructions in them. For CPUs having explicit I/O instructions, such I/O

protection is ensured by having the I/O instructions privileged. In a CPU

with memory mapped I/O, there is no explicit I/O instruction. Which one

of the following is true for a CPU with memory mapped I/O? (A) I/O protection is ensured by operating system routine(s) (B) I/O protection is ensured by a hardware trap (C) I/O protection is ensured during system configuration (D) I/O protection is not possible

SOLUTION In memory mapped I/0 the complete system (memory + I/0 ports) hold the

same set of addresses. They are considered to be the part of that memory

only. This management is done by OS only. Hence (A) is correct option.

Question. 34 What is the swap apace in the disk used for? (A) Saving temporary html pages (B) Saving process data (C) Storing the super-block (D) Storing device drivers

SOLUTION Swap space is the memory pre allowed to store processs data. This can be

compared with virtual memory. The data required to complete process is

kept here. Hence (B) is correct option.

Question. 35 Increasing the RAM of a computer typically improves performance

because (A) Virtual memory increases


(B) Larger RAMs are faster


(C) Fewer page faults occur (D) Fewer segmentation faults occur

SOLUTION Due to increase in RAM size all the pages required by CPU are available in RAM so page fault chance

are less, so virtual memory access chances are less and latency is reduced for secondary memory. Hence

(C) is correct option.

Question. 36 Consider a three word machine instruction

ADD A [R0],@B The first operand (destination) A [R0] uses indexed addressing mode with R0 as the index register.

The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses

residing at the second and the third words, respectively. The first word of the instruction specifies the

opcode, the index register designation and the source and destination addressing modes. During

execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is (A) 3 (B) 4

(C) 5 (D) 6

SOLUTION ADD A [ R 0],@B This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A [ R0] here R0

is index register which has starting address of index then this index has the block address. This whole

operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So

overall 1 + 3 + 2 = 6 machine cycles. Hence (D) is correct option.


Question. 37 Match List-I with List-II and select the correct answer using the codes

given below the lists:

List-I List-II

A. A [1] = B [j]; 1. Indirect addressing

B. while [* A ++]; 2. Indexed addressing

C. int temp=*x ; 3. Auto increment

Codes:

A B C

(A) 3 2 1

(B) 1 3 2

(C) 2 3 1 S 1 2 3 SOLUTION

LIST-I (i) A [1] = B [ J]; (ii) While [) A ++] (iii) int temp=) X

A2 B3 C1

Hence (C) is correct option.

Question. 38

LIST-II

2 Indexed addressing here the

indexing is used 3. Auto increment the memory

locations is A are automatically

incriminated. 1. Indirect addressing here temp

is assigned the value of int type

stored at the address contained

in X

Consider a direct mapped cache of size 32 KB with block size 32 bytes.

The CPU generates 32 bit addresses. The number of bits needed for cache

indexing and the number of tag bits are respectively


(A) 10,17 (B) 10,22


(C) 15,17 (D) 5,17 SOLUTION Cache is direct mapped.

Size of Cache = 32 KB = 25 X 210 B = 215 Bytes.

Require 15 bits for cache addressing so CPU address has tag and index No. of tag bits = 32 15 = 17

From 15 Cache addressing bits consist of blocks & words. Each block has 32 words (bytes) So require 5

bit. Index = block + word Block = 15 5 = 10

So, 10, 17 Hence (A) is correct option.

Question. 39 A 5 stage pipelined CPU has the following sequence of stages IF-Instruction fetch from instruction memory. RD-Instruction decode and register read, EX- Execute:ALU operation for data and address computation, MA-Data memory access-for write access the register read at RD stage it used, WB-register write back. Consider the following sequence of instruction:

I 1 : LR0,Locl; R0


(A) 8 (B) 10

(C) 12 (D) 15

SOLUTION

Order of phase in instruction cycle.

IF " A 3" E X MA " WB

1 2 3 4 5 6 7 8 9 10

R 0 ! M [ LOC] IF RD EX MA WB

R 0 ! R 0 + R0 IF RD EX MA WB

R 2 ! R 2 R0 IF RD EX MA WB

R 0 ! R 0 + R0 cant start before 3 since R0 has not been read by I1.

R 2 ! R 2 R0 cant start before 6th since I2 has not executed

R 0 ! R 0 + R0 till 5th cycle

Total cycles = 10 Hence (B) is correct option.

Question. 40 A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 sec.

The byte transfer time between the device interface register and CPU or

memory is negligible. What is the minimum performance gain of

operating the device under interrupt mode over operating it under program

controlled mode? (A) 15 (B) 25

(C) 35 (D) 45 SOLUTION

Data transfer rate = 10000 B/sec Total data = 25 X 103

Rate = 104 Performance gain = 10

254 X 100

= 25%


Hence (B) is correct option. Question. 41 Consider a disk drive with the following specification 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is

operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory;

similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle.

Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during

DMA operation is (A) 10 (B) 25

(C) 40 (D) 50

SOLUTION

Disk revolutions = 3000 PM or 50 RPS At a time can read in

One revolution = 512 KB = 219 )

Tracks read/sec 22 50

= 50 X 217 per sec.

Interrupt = .2621 sec

Percentage gain = .26211 X 100

, 26%

Hence (B) is correct option.

Data for Q. 42 & 43 are given below Consider the following data path of a CPU


The, ALU, the bus and all the registers in the data path are of identical

size. All operations including incrementation of the PC and the GPRs are

to be carried out in the ALU. Two clock cycle are needed for memory read

operation-the first one for loading data from the memory but into the

MDR.

Question. 42 The instruction add R0,R1 has the register transfer in terpretation R0


PC


The minimum number of CPU clock cycles needed during the execution cycle of this instruction is (A) 2 (B) 3


Rn ! PC + 1 PC = M [ PC] Program outer is itself a register so incremented in 1 cycle. Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles.

So total 1 + 2 = 3 cycles. Hence (B) is correct option.

Question. 44 A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the

following is a legal program counter (all values in decimal)? (A) 400 (B) 500


Size of instruction = 24 bits. Since each instruction require 243 = 3 bytes & start address is 300 so the address for this range can be multiple of 3 only so 600. Hence (C) is correct option.

YEAR 2006 Question. 45 A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes

wide. Consecutive c-bute chunks are mapped on consecutive banks with warp-around. All the k banks

can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access

may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by

accessing all the k banks in parallel. Each iteration requires decoding


the bank numbers to be accessed in parallel and this takes k /2 ns. The

latency of one bank access is 80 ns. If c = 2 and k=24, then latency of

retrieving a cache block starting at address zero

from main memory is (A) 92 ns (C) 172 ns SOLUTION

Size of Cache block = 64 B No. of main memory banks K = 24

Size of each bank C = 2 bytes.

So time taken for < access. T = decoding time + latency time T = K/2 + latency

= 12 + 80 = 92 ns.

But since C = 2 for accesses. 2

X 92 = 189 ns.

Hence (D) is correct option

Question. 46 A CPU has five-stages pipeline and runs at 1GHz frequency. Instruction

fetch happens in the first stage of the pipeline. A conditional branch

instruction computes the target address and evaluates the condition in the

third stage of the pipeline. The processor stops fetching new instructions

following a conditional branch until the branch outcome is known. A

program executes 109 instructions out of which 20% are conditional

branches. If each instruction takes one cycle to complete on average, then

total execution time of the program is (A) 1.0 second (B) 1.2 seconds (C) 1.4 seconds (D) 11.6 seconds SOLUTION Given that 80% of 109 instruction require single cycle i.e. no conditional

branching & for 20% an extra cycle required.

(B) 104 ns

(D) 184 ns


Time taken by 1 cycle = 109 sec.


Total time = 109 b 10080 X 109 + 100

20 X 2 X 109l

= 109 X 109 b 54 + 25 l

= 65 = 1.2 seconds. Hence (B) is correct option.

Question. 47 Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction bbs reg, pos,

labbel jumps to label if bit in position pos of register operand reg is one. a register is 32 bits wide and

the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following

emulation of this instruction on a processor that does not have bbs implemented. temp!reg and mask Branch to label if temp is non-zero The variable temp is a temporary register. For correct emulation the variable mask must be generated by (A) mask! 0x1 > pos (C) mask! pos (D) msdk! 0xf SOLUTION Given instruction bbs reg, pos, Label

Here pos bit decided whether to jump to label. So all other bits in temp set to 0. Temp ! reg and mask.

So of temp is not zero branch to label. So shifting left over.

Mask ! 0 X 1


size but direct mapped. The size of an address is 32 bits in both cases A2-

to-1 multiplexes has latency of 0.6 ns where a k-bit comparator has a

latency of k /10ns. The hit latency of the set associative organization is h1

while that of the direct mapped one is h2.

Question. 48 The value of h1 is (A) 2.4ns (B) 2.3ns (C) 1.8ns (D) 1.7ns SOLUTION 2 way set-associative Cache.

Size 32 KB

2 way so 16 KB sets.

Require 14 bits for 214 B

Block size = 32 Byte.

= 5 bits.

No. of blocks14 5 = 9

Tag index

h1 = 18

10 + 0.6 ns

= 2.4 ns.


Question. 49 The value of h2 is (A) 2.4ns (B) 2.3ns


(C) 1.8ns (D) 1.7ns SOLUTION Similarly to previous question. The CPU address is same but Direct coaching require for 32 KB 15 bits.

Which would be 10 + 5 = 17

17 10 5

h2 = 17

10 + 0.6

= 2.3 ns Hence (B) is correct option.

Data for Q. 50 & Q. 51 are given below. A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two dimensional

array of size 512X512 with elements that occupy 8-bytes each. Consider the following two C code

segments, P1 and P2, P1 : for (i=0;i


(A) 0 (B) 2048

(C) 16384 (D) 262144

SOLUTION Given loop P1 accesses array A row wise & P2 access column wise.

M1 = ?

Cache Capacity = 215 B. 1 element = 23 B

Total elements 512 X 512 Total data = 512 X 512 X 8 B =

221 B

Block size = 128 B

1 block can have = 1288 = 16 elements So total blocks require =

512 X 512 16

= 1638 blocks Since the memory is initially empty so all blocks are required at least

once. So, M1 = 16384 Hence (C) is

correct option.

Question. 51 The value of the ratio M1/M2 is (A) 0 (B) 1/16

(C) 1/8 (D) 16

SOLUTION

Now M2 = ?

In the case (P2 loop) the array is accessed column wise, so even the block

brought for A [0][0] A[0][15] would not be used for second column wise

access i.e. A[1][0] So new block need to swap, similarly for A[3][0] & So

on. This would continue for every element, since memory is contiguous.

So M2 = 512 X 512 = 262144


& M1 = 16384 = 1 M2 262144 16 Hence (B) is correct option.

YEAR 2007

Question. 52 Consider a 4-way set associative cache consisting of 120 lines with a line size of 64 words. The CPU

generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and

WORD fields are respectively (A) 9,6,5 (B) 7,7,6

(C) 7,5,8 (D) 9,5,6

SOLUTION 4 way set associative cache

Size = 128 X 64 words But for 4 sets

128 X 64 = 32 X 64 4 For 32 lines we require 5 bits. For 64 words we require 6 bits.

Indexing = 6 + 5 = 11 bits. Tag = 20 11

= 9 bits

9 5 6 Hence (D ) is correct option. Question. 53 Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of

data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits

required to specify a particular sector in the disk are respectively (A) 256 Mbytes, 19 bits (B) 256 Mbyte, 28 bits (C) 512 Mbytes, 20 bits (D) 64 Gbyte, 28 bits


SOLUTION

Surface = 6 Tracks = 16 X 128

Sectors = 16 X 128 X 256 = 2 4 X 2 7 X 28 = 219

So 19 lines are required to address all sectors. Bytes = 219 X 512 B = 219 X 29 B = 228 = 256 MB Hence (A) is correct option.

Question. 54 Consider a pipelined processor with the following four stages IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Bank The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock

cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle

and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the

pipelined processor. What is the number of clock cycles taken to complete the following sequence of

instructions?

ADD R2, R1, R0 R2!R1+R0

MUL R4, R3, R2 R4!R3*R2

SUB R6, R5, R4 R6!R5R4

(A) 7 (B) 8

(C) 10 (D) 14 SOLUTION Order of instruction cycle-phases. IF " ID " EX " WB We have 3 instructions.

1 2 3 4 5 6 7 8

R 2 ! R 1 ! R0 IF ID EX WB

R 4 ! R 3 ! R2 IF ID EX EX EX WB


R 6 ! R 5 ! R4 IF ID - - EX WB

Represent wait in pipeline due to result dependently. Clock cycles require = 8 Hence (B) is correct option.

Data for Q. 55, 56 & 57 are given below. Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

Instruction Operation Instruction size

(no. of words)

MOV R1,(3000) R1!M[3000] 2

LOOP:

MOV R2,R1 R2!M[R3] 1

ADD R2,R1 R2!R1+R2 1

MOV (R3),R2 M(R3]!R2 1

INC R3 R3!R3+1 1

DEC R1 R1!R1-1 1

BNZ LOOP Branch on not zero 2

HALT Stop Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The

content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the

memory location 100. All the numbers are in decided.

Question. 55 Assume that the memory is word addressable. The number of memory references for accessing the data

in executing the program completely is (A) 10 (B) 11

(C) 20 (D) 21


SOLUTION

1st memory reference R1 ! M 3000 and then in the loop which

^h runs for 10 times there are 2 memory reference every iteration.

10 X 2 = 20

Total 20 + 1 = 21

R2 ! M [ R3]

M [R3] ! R2 Hence (D) is correct option

Question. 56 Assume that the memory is word addressable. After the execution of this program, the content of memory

location 2010 is (A) 100 (B) 101

(C) 102 (D) 110

SOLUTION Program stores results from 2000 to 2010. It stores 110, 109, 108......100 at 2010 location. DEC R1 Hence (A) is correct option.

Question. 57 Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the

execution of the instruction INC R3, what return address will be pushed on to the stack? (A) 1005 (B) 1020

(C) 1024 (D) 1040

SOLUTION Now byte addressable memory so 1 word i.e. 4 bytes require 4 addresses.

MOV (R3), R2 1 1016-1019

INC R3 1 1020-1023

DEC R1 1 1024-1027

Instruction Words Location


Interrupt occurs during execution of INC R3, So CPU will complete the execution of this instruction and then

Push the next address 1024 to the stack, so after interrupt service the program can be resumed from next

instruction. Hence (C) is correct option.

Data for Q. 58 & Q. 59 are given below. Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache

consisting of 32 lines of 64 bytes each is used in the system. A 50 X 50 two-dimensional array of bytes is stored

in the main memory stating from memory location 1100H.Assume that the data cache is initially empty. The

complete array is accessed twice. Assume that the contents of the data cache do not change in between the two

accesses.

Question. 58 How many data cache misses will occur in total? (A) 48 (B) 50


Size of main memory 216 bytes. Size of Cache = 32 X 64 B = 211 B Size of array = 2500 B

Array is stored in main memory but cache is empty. Size of Cache = 2048 B So no. of page faults = 2500 2048 = 452

For second access = 452 X 2 = 904 Total = 1356


MOV R1, (3000) 2 1000-1007

MOV R2, R1 1 1008-1011

ADD R2, R1 1 1012-1015


Question. 59 Which of the following lines of the data cache will be replaced by new

blocks in accessing the array (A) line 4 to line 11 (B) line 4 to line 12 (C) line 0 to line 7 (D) line 0 to line 8 SOLUTION

No of page faults = 452

One line has 64 B

So the line at which these page faults will finish. = 45264 , 7

So 0 to 7 line Hence (C) is correct option.

YEAR 2008 Question. 60 For a magnetic disk with concentric circular track, the latency is not

linearly proportional to the seek distance due to (A) non-uniform distribution of requests (B) arm starting and stopping inertia (C) higher capacity of tracks on the periphery of the platter (D) use of unfair arm scheduling policies. SOLUTION Tracks on magnetic disks are concentric a seek is from me sector to other

may or maynt be in different tracks. This seek distance is not proportional to latency since the tracks at

periphery has higher diameter so high in capacity to store data. Hence (C)

is correct option.

Question. 61 Which of the following is/are true of the auto increment addressing mode? 1. It is useful in creating self relocating code 2. If it is included in an Instruction Set Architecture, then an


additional ALU is required for effective address calculation 3. The amount of increment depends on the size of the data item

accessed. (A) 1 only (B) 2 only (C) 3 only (D) 2 and 3 only SOLUTION In auto increment addressing mode the address where next data block to be stored is generated automatically

depending upon the size of single data item required to store. So statement 3 is correct. Statement says that this mode is used for self relocating code, but this is false since self relocating code, takes

always some address in memory. Statement 2 is also incorrect since no additional ALV is required. Hence (C) is correct option.

Question. 62 Which of the following must be true for the RFE (Return from Expectation) instruction on a general purpose

processor. 1. It must be a trap instruction 2. It must be a privileged instruction 3. An exception can not be allowed to occur during execution of an RFE instruction. (A) 1 only (B) 2 only (C) 1 and 2 only (D) 1, 2 and 3 only SOLUTION RFE (Return From Exception) is a privileged trap trap instruction which is executed when exception occurs, so

an exception is not allowed to execute. Hence (D) is correct option.

Question. 63 For inclusion to hold between two cache level L1 and L2 in a multilevel cache hierarchy, which of the following

are necessary? 1. L1 must be a write-through cache 2. L2 must be write-through cache


3. The associativity of L2 must be greater that of L1 4. The L2 cache must be at least as large as the L1 cache (A) 4 only (B) 1 and 2 only (C) 1, 2 and 4 only (D) 1, 2, 3 and 4 SOLUTION Level 1 (L1) & Level 2 (L2) cache are placed between CPV & they can be

both write through cache but this is not necessary. Associativity has no

dependence but L2 cache must be at least as large as L1 cache, since all

the words in L1 are also is L2. Hence (A) is correct option.

Question. 64 Which of the following are NOT true in a pipe lined processor? 1. Bypassing can handle alll Raw hazards. 2. Register renaming can eliminate all register carried WAR hazards. 3. Control hazard penalties can be eliminated by dynamic branch

prediction. (A) 1 and 2 only (B) 1 and 3 only (C) 2 and 3 only (D) 1,2 and 3

SOLUTION In a pipelined processor by passing cant handle all the row hazards.

Registers carried WAR doesnt have register naming as proper solution. And control hazard penalties are eliminated by delayed branching not by

dynamic branch prediction. So all are false. Hence (D) is correct option.

Question. 65 The use of multiple register windows with overlap causes a reduction in

the number of memory accesses for 1. Function locals and parameters 2. Register saves and restores


3. Instruction fetches (A) 1 only (B) 2 only (C) 3 only (D) 1,2 and 3 SOLUTION Multiple register windows with overlap causes a reduction in the number of memory accesses for instruction

fetching. Hence (C) is correct option.

Question. 66 In an instruction execution pipeline, the earliest that the data TLB (Translation Look aside Buffer) can be

accessed is (A) before effective address calculation has started (B) during effective address calculation (C) after effective address calculation has completed (D) after data cache lookup has completed SOLUTION TLB is used during effective address calculation in an instruction execution pipeline. Hence (B) is correct option.

Data for Q. 67, 68 & 69 are given below. Consider a machine a 2-way set associative data cache of size 64 kbytes and block size 16 bytes. The cache is

managed using 32 bit virtual addressed and the page size is 4 kbytes. A program to be run on this machine

begins as follows: Double APR[1024]]1024] int i,j ; /*Initalize array APR to 0.0*/ for (i = 0;i < 1024;i ++) for (j = 0;k < 1024;j ++) APR[i][j] = 0.0; The size of double 8 bytes. Array APR is in memory stating at the beginning of virtual page 0 # FF000 and

stored in row major order. The cache is initially empty and no pre-fetching is done. The only


data memory references made by the program are those to array APR.

Question. 67 The total size of the tags in the cache directory is (A) 32 kbits (B) 34 kbits

(C) 64 kbits (D) 68 kbits

SOLUTION

Virtual (CPU) address has = 32 bits

2 way set associative cache size = 64 KB

Size of 1 set = 32 KB

Require 15 bits for indexing.

So Tag = 32 15 = 17

Size of block = 16 bytes

= 4 bits are required

Index = block + word

Block = 15 4 = 11

17 11 4

CPV address Size of tags = There are 217 bytes of tags in every set of cache. So

total = 17 X 2 X 1024 = 34 KB.


Question. 68 Which of the following array elements has the same cache index as APR

[0][0]? (A) APR[0][4] (B) APR[4][0] (C) APR[0][5] (D) APR[5][0] SOLUTION Elements stored in row major order. Two elements should have same

cache index (15 bits) & their tags may be different (17 bits). SoAPR[%][

%] the MSB 17 bits will be changed.


APR[%][ %] APR[%][1]............... APR[2][%]................................ APR[4][%]................................

So on. This is virtual memory storage. So 15 LSB of APR [%][ %] & APR [%][ %] are same so same index APR [%] & APR [4] 17 MSB are different

so tags differ. Hence (B) is correct option.

Question. 69 The cache hit ratio for this initialization loop is (A) 0% (B) 25%

(C) 50% (D) 75%

SOLUTION

Cache hit ratio =

No. of hits

Total accesses

=

1024 = 1 = 0.5

1024 + 1024

2

or = 50%


Data for Q. 70 & 71 are given below. Delayed branching can help in the handling of control hazardous Question. 70 For all delayed conditional branch instruction, irrespective of weather the condition evato true or false, A (A) the instruction following the conditional branch instruction in memory is executed (B) the first instruction in the fall through path is executed (C) the first instruction in the taken path is executed


(D) the branch takes longer to execute that any other instruction


SOLUTION Delayed branching for conditional instructions, irrespective of whether the

condition evaluates to true or false, the first instruction in the fall through

path would be executed this prevent from hazardous control transfer. Hence (B) is correct option. Question. 71 The following code is to run on a pipe lined processor with one branch

delay slot 11: ADD R2 ! R7+R8 12: SUB R4 ! R5 R6 13: ADD R1 ! R2+ R3 14: STORE Memory [R4] ! R1

BRANCH to Label if R1==0 Which of the instruction 11,12,13 or 14 can legitimately occupy the delay

slot without any other program modification? (A) 11 (B) 12

(C) 13 (D) 14

SOLUTION In pipelining result of 1 instruction is used for the next in pipeline. Delay

slot will be occupied by the next instruction in the fall through path. The

branching instruction R1 == 0 goto Label X.

So in delay slot I2 will be there.


YEAR 2009

Question. 72 How many 32KX1 RAM chips are needed to provide a memory capacity

of 356-bytes ? (A) 8 (B) 32

(C) 64 (D) 128


SOLUTION

Memory capacity of 1 RAM = 32 K bits Total Memory required = 256 K bytes No. of RAM = 256 X K X 2

3 X bits 32 X K X bits

Chips required = 28 X25 23

= 26 = 64


Question. 73 A CPU generally handles are interrupt by executing an interrupt service routine (A) As soon as an interrupt is raised (B) By checking the interrupt register at the end of fetch cycle (C) By checking the interrupt register after finishing the execution of the current instruction (D) By checking the interrupt register at fixed time intervals

SOLUTION An interrupt is a signal delivered to CPU, which tells to stop its normal service routine & execute interrupt

service routine. This interrupt service routine is checked as soon as CPU receives the interrupt but since CPU working unit is an

instruction so CPU can switch to ISR only after execution of current instruction. Hence (C) is correct option.

Question. 74 Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in

stages S1, S2, S3, S4 is shown below:

S1 S2 S3 S4

I1 2 1 1 1

I2 2 3 2 2

I3 2 1 1 3


I4 1 2 2 2

What is the number of cycles needed to execute the following loop? for (i = 1to 2){I1; I2; I3; I4;}

(A) 16 (B) 23

(C) 28 (D) 30

SOLUTION We can see a single iteration of given for loop according to the cycles

required.

Cycle S1 S2 S3 S4 Completion

1 I1

2 I1

3 I2 I1

4 I3 I2 I1

5 I3 I2 I1 I1

6 I4 I2

7 I3 I2

8 I4 I2

9 I4 I3 I2

10 I4 I2 I2

11 I4 I3

12 I3

13 I3 I3

14 I4

15 I4 I4

No. of cycle of 2 iteration = 2 X 15 =

30


Question. 75 Consider a 4 way set associative cache (initially empty) with total 16

cache blocks. The main memory consists of 256 blocks and the request for


memory blocks is in the following order :


0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155 Which one of the following memory block will NOT be in the cache if LRU replacement policy is used ? (A) 3 (B) 8

(C) 129 (D) 216 SOLUTION 4 way set associative so 16 block will be divided in 4 sets of 4 blocks each. We apply (Address mod 4) function to decide set.

0 48 0 mod4 = 0 )

Set 0

4 32 255 mod4 = 3 )

8 8

1 mod4 = 1 )

216 92 4 mod4 = 0 )

1 1 3 mod4 = 3 )

Set 1

133 133 8 mod4 = 0 )

129 129

133 mod4 = 1 )

73 73 159 mod4 = 3 )

216 mod4 = 0 )

Set 2

129 mod4 = 1 )

63 mod4 = 3 )

8 mod4 = 0 )

255 155 98 mod4 = 0 )

Set 3

3 3 32 mod4 = 0 )

159 159

73 mod4 = 1 )

63 63 92 mod4 = 0 )

155 mod4 = 3 )

All ) are misses S1 is the first stage & S2 is second. In the second stage 216 is not present in

Cache Hence (D) is correct option.

Common Data for Question 76 & 77


A hard disk has 63 sectors per track, 10 platters each with 2 recording


surfaces and 1000 cylinders. The address of a sector is given as a triple

c , h, s , where c is the cylinder number, h is the surface number and s is

the sector number. Thus, the 0th sector is addressed as 0,0,0 , the 1st

sector as 0,0,1 , and so on.

Question. 76

The address 400,16,29 , corresponds to sector number:

(A) 505035 (B) 505036

(C) 505037 (D) 505038

SOLUTION Each cylinder has 10 platters or 20 recording surfaces or

63 X 20 sector = 1260 sectors.

Each recording surface has 63 sectors. So < 400,16,297 =< c , h, s >

400 X 1260 + 16 X 63 + 29

50503

7 Hence (C) is correct option.

Question. 77

The address of 1039th sector is

(A) 0,15,31 (B) 0,16,30

(C) 0,16,31 (D) 0,17,31

SOLUTION 1 cylinder has 1260 sectors So address for 1039th sector.

C = 0

Each surface has 63 sectors.

Total surface here = 103963 = 16 surfaces

Remainder here 31 sectors So < 0, 16, 31 >.


YEAR 2010 Question. 78 A main memory unit with a capacity of 4 megabytes is build using 1M X 1 bit DRAM chips. Each DRAM

chip has 1K rows of cells with 1 K cells in each row. The time taken for a single refresh operation is 100

nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is (A) 100 nanoseconds (B) 100)210nanoseconds (C) 100)220nanoseconds (D) 3200)220nanoseconds SOLUTION

Size of main memory = 4 MB 1 DRAM size = 1 Mb No. of chips required =

4 X M X 8 X b 1 X M X b

= 32

1 DRAM has 1 K rows 1 ROW has 1 K cells

Total cells in 1 DRAM = K2 = 220 In 32 DRAM = 32 X 220 Cells 1 cell refresh take 100 ns.

So total refresh time = 32 X 100 X 220 ns = 3200 X 220 ns.


Question. 79 A-5 stage pipelined processor has Instruction Fetch. (IF), Instruction Decode (ID), Operand Fetch (OF),

Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle

each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction. The PO stage takes 1

stake clock cycle for ADD and SUB instructions 3 clock cycles for MUL instruction, and 6 clock cycles for

DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles

needed to execute the following sequence of instructions ?


Instruction Meaning of instruction

I0 : MUL R 2, R 0, R1 R 2 ! R 0)R1

I1: DIV R 5, R 3, R4 R 5 ! R 3 /R4

I2 : ADD R 2, R 5, R2 R 2 ! R 5 + R2

I3 : SUB R 5, R 2, R6 R 5 ! R 2 R6

(A) 13 (B) 15

(C) 17 (D) 19 SOLUTION The order of operations IF " ID " OF " PO " WO

Figure

Here A = (R 3 /R 4) + R 2, R6

So we can see that all the instruction can be executed in 17 clock cycles

using piplining.


Question. 80 The program below uses six temporary variables a, b, c , d, e, f a

= 1 b = 10 c = 20 d = a + b

e = c + d

f = c + e

b = c + e

e = b + f

d = 5 + e Assuming that all operations take their operands from register, what is the

minimum number of registers needed to execute this program without spilling ?

(A) 2 (B) 3


(C) 4 (D) 6


SOLUTION Replacement

R1 R2 R3

a b c

d b c

d e c

f e c

f b c

f e c

f e d So all the operations done using 3 registers only. Hence (B) is correct option.

Common Data for Questions 81 & 82 A computer system has an L1 and L2 cache, an L2 cache, and a main memory unit connected as shown below.

The block size in L1 cache is 4 words. The block size is L2 cache is 16 words. The memory access times are 2

nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unity respectively.

Question. 81 When there is a miss in L1 cache and a hit in L2 cache, a block is transferred form L2 cache to L1 cache. What is

the time taken for this transfer ? (A) 2 nanoseconds (B) 20 nanoseconds (C) 22 nanoseconds (D) 88 nanoseconds

SOLUTION Each block is L2 Cache is 4 times L1 Cache. So far 1 block miss in L1 Cache the block from L2 to L1 will be

transferred, but L2 block has size 16 words & L1 data bus of 4 words, so 4L2 & 4L1 access are


required. 4 X 2 + 4 X 20 8 + 80 88 ns


Question. 82 When there is a miss in both L1 cache and L2 cache, first a

block is transferred from memory to L2 cache, and then a

block is transferred from L2 cache to L1 cache. What is the

total time taken for these transfers ? (A) 222 nanoseconds (B) 888 nanoseconds (C) 902 nanoseconds (D) 968 nanoseconds SOLUTION Miss in both L1 & L2. Cause main memory to transfer that

block in both cache. 1 block of Main memory has 16 words but data bus of L2

has only 4 words. So 4 access of Main memory & 4 access

of L2 Cache required to update L2 4 X 20 + 4 X 200

80 + 800 = 880 ns

Now L2 updates L1, this takes 4 access to L1 & 4

access to L2 4 X 2 + 4 X 20 8 +

80 = 88

ns Total

time =

880 +

88 = 968 ns

Hence (D) is correct option. YEAR 2013

92. Consider an instruction pipeline with five stages without any branch prediction:


Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program

consisting of 12 instructions I1 ,I2 ,I3 ,......I12 is executed in this pipelined

processor. Instruction I4 is the only branch instruction and its branch target is I9 . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

(A) 132 (B) 165 (C) 176 (D) 328 Ans: (C) Exp: Total clock slots taken are 16. Each slot will take maximum of

{5, 7, 10, 8 ,7} =10.

Hence total slots for all the

instructions=

DIGITAL DESIGN YEAR 2001 Question. 1

Given the following Karnaugh map, which one of the following represents

the minimal sum-of-Products of the map ?


(A) xy + y' z (B) wx' y' + xy + xz (C) w' x + y' z + xy (D) xz + y


SOLUTION

There are 2 quads. y' z + yx So xy + y' z Hence (A) is correct option.

Question. 2

Consider the following circuit with initial state Q 0 = Q1 = 0. The D flip-flops are positive edged

triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C ; the clock of C $ 40 nanosecond. Which one is the

correct plot of Y


SOLUTION Consider the following circuit with initial state Q 0 = Q1 = 0. The D flip-

flops are positive edged triggered and have set up times 20 nanosecond

and hold times 0. Consider the following timing diagrams of X and C ; the clock period of C

$ 40 nanosecond. Which one is the correct plot of Y ?

Figure Question. 3 The 2s complement representation of ( 539)10 is hexadecimal is (A) ABE (B) DBC (C) DE5 (D) 9E7

SOLUTION


Binary of 539 = 1000011011


Binary :0010 0001 1011

2's comp :1101 1110 0101

Hexadecimal D E 5

(DES)16 Hence (C) is correct option. Question. 4 Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac ' + bc).

Which of the following is true ? (A) f = x1' + x2 (B) f = x1' x2 + x1x2' (C) f = x1x2 + x1' x2' (D) f = x1 + x2

SOLUTION

Output of any 2:1 MUX = ac' + bc Here output of MUX 1.

g = ax 1' + bx1

Output of MVX 2 (E) = gx 2' + x 1 x2 (F) = (ax 1' + bx 1) x 2' + x 1 x2 (G) = ax 1' x 2' + bx 1 x 2' + x 1 x2

Given a = 1, b = 0 (H) = x 1' x 2' + x 1 x2

Hence (C) is correct option. Question. 5 Consider the circuit given below the initial state Q 0 = 1,Q 1 = Q2 = 0. The state of the circuit is given by the value 4Q 2 + 2Q 1 + Q0


Which one of the following is the correct state sequence of the circuit ?

(A) 1, 3, 4, 6, 7, 5, 2 (B) 1, 2, 5, 3, 7, 6, 4

(C) 1, 2, 7, 3, 5, 6, 4 (D) 1, 6, 5, 7, 2, 3, 5

SOLUTION

Initially Q0 Q1 Q2 Value 4Q 2 + 2Q 1 + Q0

Clk 1 0 0 1

1 0 1 0 2

2 1 0 1 5

3 1 1 0 3

4 1 1 1 7

5 0 1 1 6

6 0 0 1 4


YEAR 2002

Question. 6


Minimum sum of product expression for f (w, x, y, z) shown in Karnaugh-

map below is


(A) xz + y' z (B) xz' + zx'

(C) x' y + zx' (D) None of the above

SOLUTION

There are 2 quads possible xz' + x' z Hence (B) is correct option.

Question. 7 The decimal value of 0.25 (E) is equivalent to the binary value 0.1 (F) is equivalent to the binary value 0.01 (G) is equivalent to the binary value 0.00111..... (H) cannot be represented precisely in binary.


SOLUTION Given decimal no. 0.25

Binary = ? .25 # 2 = .5 .5 # 2 = 1 (.01)2

Hence (B) is correct option. Question. 8 The 2s complement represent representation of the decimal value 15 is (A) 1111 (B) 11111

(C) 111111 (D) 10001

SOLUTION Given ( 15)10 Binary of 15 = (01111)2

2s complement of 15 would represent ( 15).

01111 (10001)2 Hence (D) is correct option. Question. 9 Sign extension is a step in (G) floating point multiplication (H) signed 16 bit integer addition (I) arithmetic left shift (J) converting a signed integer from one size to another.

SOLUTION Sign extension is the operation in computer arithmetic of increasing no. of

bits of a binary no., while preserving sign and value done by appending

MSBs. In the floating point multiplication to bring the no. in desired no.

of significant digits sign extension is done. Hence (A) is correct option.


Question. 10 In 2s complement addition, overflow (D) Relational algebra is more powerful than relational calculus (E) Relational algebra has the same power as relational calculus. (F) Relational algebra has the same power as safe relational calculus. (G) None of the above.

SOLUTION

In 2s complement addition, overflow occurs when the carries from sign bit & previous bit doesnt

match. So overflow cant occur when a positive value is added to some negative value. Hence (B) is correct option.

Question. 11 Consider the following logic circuit whose inputs are functions f1, f2, f3 and output is f

Given that

f1 (x, y, z) = (0,1,3,5)

f2 (x, y, z) = (6,7), and

f (x, y, z) = (1,4,5)

f3 is

(A) (1,4,5) (B) (6,7)

(C) (0,1,3,5) (D) None of the above

SOLUTION f1 (x, y, z) = (0,1,3,5)


= x' y' + y' z + x'

z f2 (x, y, z) = (6,7)

= xy f (x, y, z) = (1,4,5)

= xy' + y' z

f (x, y, z) = f1 f2 : f3 (E) f1 : f2 + f3 (F) xy (x' y' + y' z + x' z) + (xy' + y' z)

f3 = xy' z + xy' z' + xy' z + x' y' z f3 = (1,4,5)

Hence (A) is correct option. Question. 12

Consider the following multiplexor where 10, 11, 12, 13 are

four data input lines selected by two address line combinations

A1A0 = 00,01,10,11 respectively and f is the output of the multiplexor. EN is the Enable input.


The function f (x, y, z) implemented by the above circuit is (A) xyz' (B) xy + z

(C) x + y (D) None of the above

SOLUTION

A1 A0 EN (MUX) work

0 0 1 do not

0 1 0 (MUX) Work

1 0 1 do not

1 1 0 So MUX is ENABLED only if A0 = 0 So output should have Z'. Consider xyz' option (A) A, A0 = 1 0 gives correct answer. Hence (A) is correct option.

Question. 13 Let f (A, B) = A' + B. Simplified expression for function f (f (x + y, y), z) is (A) x' + z (B) xyz (C) xy' + z (D) None of the above

SOLUTION

f (x + y, y) = (x + y)' + y & x + y + y f (f (x + y, y), z) = x + y + y + z & (x + y : y ) + z

[(x + y) : y ] + z


[xy + yy ] + z

xy + z

Hence (C) is correct option. Question. 14 What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after

executing the following 8085 program ? MIV H, 5DH

MIV L, 6BH

MOV A, H ADD L (A) AC = 0 and CY = 0 (B) AC = 1 and CY = 1 (C) AC = 1 and CY = 0 (D) AC = 0 and CY = 1

SOLUTION

Program is to add 2 nos kept in H & L, result of addition is stored in A.

(5D) 16 + (6B)16 &

is the carry so CY = 0

(E) is auxillary carry AC = 1


Question. 15 The finite state machine described by the following state diagram

yx and x stands for

with A as starting state, where an arc label is 1-bit input and y stands for 2-bit output.


(A) Outputs the sum of the present and the previous bits of the input. (B) Outputs 01 whenever the input sequence contains 11 (C) Outputs 00 whenever the input sequence contains 10 (D) None of the above. SOLUTION

Previous input Present i/p Output

0(A) 0(A) 00

0(A) 1(B) 01

1(B) 0(A) 01

1(B) 1(C) 10

1(C) 1(C) 10

1(C) 0(A) 01

So output is always sum of the present and previous bits of input. Hence (A) is correct option. YEAR 2003 Question. 16 Assuming all numbers are in 2s complement representation, which of the following number is

divisible by 11111011? (A) 11100111 (B) 11100100

(C) 11010111 (D) 11011011 SOLUTION

We cant judge the nos in 2s complement first we need to convert them


in decimal Given no. 11111011"00000101=5


(A) 11100111 " 00011001 = 25 (B) 11100100 " 00011100 = 28 (C) 11010111 " 00101001 = 41 (D) 11011011 " 00100101 = 37

From all only option (A) is divisible by 5.

Shortcut : To convert 2s complement no. directly into original binary, we

should complement all the digits from MSB till the last one (1). Keep the

last 1 from the LSB as it is. Observe in the example.

Question. 17 The following is a scheme for floating point number representation using

16 bits.

Let s, c and m be the number represented in binary in the sign, exponent,

and mantissa fields respectively. Then the flouting point number

represented id )( 1)2 (1 + m # 2 9)2e31, if the exponent 111111 0 otherwise

What is the maximum difference between two successive real numbers representable in this system?

(A) 240 (B) 29

(C) 222 (D) 231 SOLUTION e has 6 bits so max value can be

26 1 = 63 when e = 111111 But given e =Y 111111

So max e = 62 = 111110 Two consecutive number will have same exponent but difference in

mantissa by 1. Difference would be

( 1)2 (1 + (m + 1)2 9)262 31 ( 1)2 (1 + m # 2 9)262 31 231 # 29 = 222



Question. 18 A 1-input, 2-output synchronous sequential circuit behaves as follows. Let zk , nk denote the number of 0s and 1s respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. 1. nk nk = 2. In this case, the output at the k -th and all subsequency clock ticks is 10. 2. nk zk = 2. In this case, the output at the k -th and all subsequent clock ticks is 01. What in the minimum number of states required in the state transition graph of the above circuit? (A) 5 (B) 6

(C) 7 (D) 8 SOLUTION The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output

for particular inputs decide states.

i/p op 1 op 2 State

0 0 0 Intial

0 0 1 n K z K = 2

0 1 0 z K n K = 2

0 1 1 Not applicable

1 0 0 Initial

1 0 1 n K z K = 2

1 1 0 z K n K = 2

1 1 1 is correct Using 3 bits we require 23 1 = 7 states here.


Question. 19 The literal count of a boolean expression is the sum of the number of times each literal appears in the

expression. For example, the literal count of (xy + xz) is 4. What are the minimum possible literal

counts


of the product-of-sum and sum-of-product representations respectively of

the function given by the following karnaugh map? Here, denotes dont care (A) (11,9) (B) (9,13)

(C) (9,10) (D) (11,11)

SOLUTION

Considering product of sum & sum of product separately.

Sum of product Product of sum

= wy + w' y' + z' wx' + xyz' = (y' + z')(z' + y)(w' + z')

12 34 567 8910 (x + z + w)

Literal count =10

Lateral count =9



In SOP the K-map is solved for 1 & POS K-map solved for 0


Question. 20 Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays 1 = 2ns and 2 = 4ns as shown

in the figure. both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and

wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition

(s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns?

(A) 1 (B) 2

(C) 3 (D) 4 SOLUTION Due to delays S1 = 2 & S2 = 4 the transitions would occur at time 1, 2 & 4.

Time Input (A) Output (B)

0 1 0

I 1 1 0 Transition

II 2 1 0 Transition

III 4 0 1 Transition So total 3 transitions Hence (C) is correct option.

YEAR 2004 Question. 21

The Boolean function x' y' + xy + x' y is equivalent to


(A) x' + y' (B) x + y (C) x + y' (D) x' + y

SOLUTION x' y' + xy + xy' x'(y + y') + xy (A + A') = 1

x' + xy (A + AB) = (A + A) : (A + B) (x' + x) : (x' + y)

1 : (x' + y) x' + y


Question. 22 In an SR latch made by cross-coupling two NAND gates, if both S and R

inputs are set to 0, then it will result in (A) Q = 0,Q' = 1 (B) Q = 1,Q' = 0 (C) Q = 1,Q' = 1 (D) Indeterminate states

SOLUTION SR latch both S and R when 0 leads to invalid state. Transition table for SR flip flop.

S R Q(Next state) i 0 Invalid so Q=Q=1 change

0 1 1

1 0 0 1 1 previous state

For S=R=0 Q=Q=1


Question. 23 If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and

y are (A) 8, 16 (B) 10, 12

(C) 9, 13 (D) 8, 11

SOLUTION

(73)x = (54)y

7x + 3 = 5y + 4

(x', y) 7x + 3 5y + 4

8, 16 59 84

10, 12 73 64

9, 13 64 69

8, 11 59 59 Hence (D) is correct option.

Question. 24 What is the result of evaluating the following two expressions using three-digit floating point arithmetic

with rounding? (113.+111.)+7.51

113.+(111.+7.51)

(A) 9.51 and 10.0 respectively (B) 10.0 and 9.51 respectively

(C) 9.51 and 9.51 respectively (D) 10.0 and 10.0 respectively

SOLUTION

Expression 1

(113.0 + ( 111.) + 7.51

(113.0 111.0) + 7.51

2.0 + 7.51

9.51

10 rounded off Expression 2 113.0 + ( 111.0 + 7.51) 113.0 + ( 103.49) 113.0 103.00 10.0 rounded off Hence (D) is correct option


Question. 25 A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1

by 0001,...9 by 1001. A combinational circuit is to be diesigned which

takes these 4 bits as input and outputs 1 if the digit $ 5, and 0 otherwise. If

only AND, OR and NOT gates may be used, what is the minimum number

of gates required? (A) 2 (B) 3

(C) 4 (D) 5 SOLUTION CKT takes 4 bits as the input so K-Map will have 4 variable so 16 options

are available.

1 digit = 5 0 otherwise Here for 0 to 4 we have 0 output, from 5 to 9 1 output & for 10 to 15 dont

care. 1 octed & 2 pounds. a + bd + bc

a + b (d + c) Two OR gates

One AND gate

Total 3 Hence (B) is correct option.

Question. 26 Which are the essential prime implicates of the following Boolean

function?

f (a, b , c ) = a' c + ac ' + b ' c


(A) a' c and ac' (B) a' c and b ' c


(C) a' c only (D) ac' and bc'

SOLUTION

f (a, b , c) = a' c + ac ' + b ' c Making min terms a' bc + a' b' c + abc ' + ab' c ' + a' b' c + ab' c Since b ' c gives no new

term. So a' c & ac' are only essential prime implicants. Solution detailed method Tabulation method Since b ' c gives no new term. So a' c & ac' are only essential prime implicants. Solution detailed method

Tabulation method f (a, b , c ) = /m(1,3,5,6,4) Figure Figure 3 & 6 have only 1 cross they are in a' c & ac' Question. 27 Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-

1-0, as shown below

To complete the circuit, the input X should be (A) Q2' (B) Q2 + Q1

(C) (Q1 5 Q2)' (D) Q1 5 Q2

SOLUTION Counter counts the no. of signal inversion change of states. Sequence input is 0 2 3 1

0


Binary 00 10 11 01 00 to generate signals if we XOR gate then it outputs 1 if both are

different. So output sequence would be. 0 1 0 1 0 & the sequence would be counted.

So. X = Q 1 5 Q2 Hence (D) is correct option. Question. 28 A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT,

NAND, NOR gates only. Assuming that all the inputs are available in both complemented and

uncompensated forms and the delay of each gate is one time unit, what is the overall propagation

delay of the adder? Assume that the carry network has been implemented using two-level AND-OR

logic. (A) 4 time units (B) 6 time units (C) 10 time units (D) 12 time units

SOLUTION Carry of any higher order bit is dependent upon previous order bit addition generated carry.

C out = g 0 + p0 C in

P3 P2 P1 P0 g 3 g 2 g 1 g0

c 3 c 2 c 1 c0

c3 g 3 + P3 g 2 + P3 P2 g 1 + | P3 P2 P1 g 0 + P3 P2 P2 P0 C in This is 4 bit look

ahead adder equation total gate delay

= 1 + 1 + 2 + 2

= 6 Hence (B) is correct option. Question. 29 Let A = 11111010 and B 0000 1010 be two 8-bit 2s complement numbers. Their product in 2s

complement is (A) 1100 0100 (B) 1001 1100

(C) 1010 0101 (D) 1101 0101

SOLUTION


A and B are in 2s complement form.

A = 11111010

Binary = 00000110 = 6 2s complement represent ve number So A = 6

B = 00001010 MSB is 0 so +ve no. decimal 10.

B = 10

A # B = 6 # 10

= 60 Binary of 60 = 00111100

2s complement 11000100 Hence (A) is correct option.

YEAR 2005

Question. 30

Consider the following circuit.

Which one of the following is TRUE? (A) f is independent of X (B) f is independent of Y

(C) f is independent of Z (D) None of X, Y, Z is redundant


SOLUTION

f = X : Y : Y : Z

= X : Y + Y : Z = X : Y + Y : Z

For redundant check we need to draw K map to min terms. XY (Z + Z ) + (X + X ) : YZ XYZ + XY Z + XYZ + X YZ XY + YZ + XZ Hence (D) is correct option.

Question. 31 The range of integers that can be represented by an a bit 2s complement

number system is

(A) 2 n 1 to (2n1 1) (B) (2 n 1 1) to (2n1 1)

(C) 2n 1 to 2n1 (D) (2 n 1 + 1) to (2n1 1)

SOLUTION n bit 2s complement system must have corresponding bit binary system. But to implement +ve & ve nos. Both

we require MSB to be sign bit.

So maximum magnitude can be 2n1 1 suppose we take n = 4.


Using 4 bits. 1 1 1 1,. . . . . .0 0 0 0, . . . . .01 1 1

7 +7 This would be the range.

So (2 n1 1) to + (2 n1 1) Hence (B) is correct option.

Question. 32 The hexadecimal representation of 6578 is (A) 1AF (B) D78

(C) D71 (D) 32F SOLUTION

(657)8 = (?)16 Making binary S S = 0 0 010101111 (IAF)

A BBC 16 Hence (A) is correct option.

Question. 33 The switching expression corresponding to

f (A, B, C , D) = /(1,4,5,9,11,12) is (A) BC' D' + A' C ' D + AB' D (B) ABC' + ACF + B' C ' D (C) ACD ' + A' BC' + AC' D' (D) A' BD + ACD ' + BCD'

SOLUTION

f (A, B, C , D) = /(1,4,5,9,11,12) Drawing K map for min terms.


BC D + A C D + AB D So min terms are

BC D + A CD + AB D Hence (A) is correct option. Question. 34 Consider the following circuit involving a positive edge triggered D -FF.

Consider the following timing diagram. Let Ai represent the logic level on

the line A in the i th clock period.

Let A represent the complement of A. The correct output sequence on Y

over the clock perids 1 through 5 is (A) A0 A1 A1 ' A3 A4 (B) A0 A1 A2 ' A3 A4 (C) A1 A2 A2 ' A3 A4 (D) A1 A2 ' A3 A4 A5

SOLUTION We need to calculate equation for D input.

(A) = (A i X')' (X' Q')' = A i + X + X + Q

(B) = A i ' + X + Q Drawing truth table for ckt

Clock X Q0 = 0 Q1 = 1 Ai Y


0 1 0 1 A0' A0'

1 1 0 1 A1' A0'

2 0 0 1 A2' A1'

3 1 0 1 A3' A1'

4 1 0 1 A4 ' A3'

5 0 0 1 A5' A4 '

Hence (A) is correct option. Question. 35 The following diagram represents a finite state machine which takes as input a binary number from the

least significant bit

Which one of the following is TRUE? (I) It computes 1s complement of the input number (J) It computes 2s complement of the input number (K) It increments the input number (L) It decrements the input number

SOLUTION The transition table for the diagram

Present state Input Next state Output

Q0 0 Q0 0

Q0 1 Q1 1

Q1 0 Q1 1


Q1 1 Q1 0 So the FSM takes input from LSB side it doesnt change state till the first 1 comes from LSB side, after

that it complement all the bits. This is logic for 2s complement. Hence (B) is correct option.

Question. 36 Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0, Q1. Let

the initial state be 00. The state transition sequence is (A) 00 " 11 " 01 (B) 00 " 11

A BBBBBBBC A BBBC

(C) 00 " 10 " 01 " 11 (D) 00 " 11 " 01 " 10

A BBBBBBBBBBC A BBBBBBBBBBC

SOLUTION

Truth table for DFF

CP D Qn+1 Action

0 X Qn No change

1 0 0 Reset

1 1 1 Set D here AX + X' Q' Truth table for ckt


and so on. Hence (D) is correct option.

Data for Q. 37 & 38 are given below. Solve the problems and choose the correct answers. Consider the following floating point format Mantissa is a pure fraction is sign-magnitude form. Question. 37 The decimal number 0.239 # 213 has the following hexadecimal representation without normalization and rounding off (A) 0D 24 (B) 0D 4D (C) 4D 0D (D) 4D 3D

SOLUTION Sign bit 0

Exponent = 13 Excess 64 = 13 + 64 = 77 = 1001101

Binary of 239


We have 8 bits for Mantissa 0 0 1 1 1 1 0 1 So the floating point format.


0 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1

0 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1

4 D 3 D Hence (D) is correct option.

Question. 38 The normalized representation for the above format is specified as

follows. The mantissa has an implicit 1 preceding the binary (radix) point.

Assume that only 0s are padded in while shifting a field. The normalized

representation of the above number (0.239 # 213) is (A) 0A 20 (B) 11 34 (C) 4D D0 (D) 4A E8 SOLUTION

Given no. .239 # 213

Normalized form of binary. Binary " .239 = (00111101)2

Normalized = 1.11101 # 210

- Proceeding implicit 1

So 8 bit mantissa 11101000S

padding Excess 64 exponent

1 0 0 1 0 1 0 = 74

Sign bit = 0

Floating Point Format

0 1001010 11101000

0100 1010 1110 1000

4 A E 8

GAE8 Hence (D) is correct option.


YEAR 2006

Question. 39 You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes

only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops)

will delay the phase of f by 180c ?

SOLUTION

We require phase shift of 180 in f In ckt (B) the negation of signal f & clock delays signal f by 180.


So phase shift occurs. Hence (B) is correct option.

Question. 40 Consider the circuit below. Which one of the following options correctly represents f (x, y, z)?

+ xy

(A) xz + xy + yz (B) xz + yz

(C) xz + xy + yz (D) xz + xy + yz

SOLUTION

MVXI

Selects X when Z = 0

Y' when Z = 0

MVX II

Selects (XZ' + Y' Z) when y = 0

X when y = 0 so (XZ' + YZ) Y' + XY

Simplifying = xz' y' + zy' y' + xy

= xz' y' + xy (z + z') + zy' = xz' y' + xyz + xyz' + zy'(x + x') = xz' y' + xyz + xyz' + xy' z + x' y'

z

= y' z + xy' z + xyz' + xyz + xyz'[a + a = a] = y' z + xz'(y + y') + xy (z + z') = y' z + xz' + xy



Question. 41 Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c, the carry in, the function that represents the

carry generate function when these two numbers are added is (A) a2 b2 + a1 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0 (B) a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b21 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0 (C) a2 + b2 + (a2 5 b2)[a1 + b1 + (a1 5 b1)(a0 + b0)] (D) a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 a1 a0 b2 b0 + a0 b2 b1 b0

SOLUTION

a2 a1 a0 b2 b1 b0 C

0 0 0 0 0 0 0

0 0 1 0 0 1 1

0 1 0 0 1 0

0 1 0 0 1 1

1 0 1 1 0 0

1 0 0 1 0 1

1 1 1 1 1 0

1 1 0 1 1 1 Case I These are the possible value of a 2 a 1 a0 & b 2 b 1 b0 when a2 = 1

c = 1 Case II b2 = 1 c = 1 so a 2 + b2 Case III If any 1 of a2 or b2 is 1 a 2 5 b2

then if a1 = 1 c = 1 b1 = 1 c = 1 so a 2 5 b 2 [ a 1 + b1]

Case IV If any of a2 or b2 is 1 & any of a2 or b1 is 1 then if a0 = 1 c = 1 or if b0 = 1 then c = 1 so overall. a 2 + b 2 + [(a 2 5 b 2){a 1 + b 1 + (a 1 5 b 1)(a 0 + b0)}]


Question. 42 Consider a boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a

time. If the function happens to be true for two input vectors i1 +< w1, x1, y1, x1 > and i2 +< w2, x2, y2, z2

>


, we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = /(5,, 711,12,13,15). Which of the following cube covers of f will ensure that the required property

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