color slides soce 3 3

March 3, 2004

®

SoC Encounter™: Continuous Convergence(Flat and Hierarchical)

Version 3.3

3/3/04 2SoC Encounter

SoC Encounter Course

� This course is flow-based. It draws heavily on Tcl commands to implement the design.

� In this course, it is assumed that you know how to use the Encounter engine and have some basic knowledge of the features of the Encounter platform.

� In this course, you will execute all the major steps required tocomplete the design flow from gate level through place and route.

� You will fix signal integrity and timing problems using parasitic data extracted with the Fire & Ice® extractor.

� You will run power analysis and view the IR drop in your design.


Course Objectives

In this course, you will

� Explore high-level and hierarchical design planning and virtual prototyping.

� Run Amoeba and block placement.

� Route the design with Trial Route.

� Estimate parasitics and run delay calculation.

� Create clock trees.

� Run delay calculation.

� Optimize timing.

� Run final route.

� Extract parasitics.

� Run crosstalk analysis.

� Run power analysis.


Course Agenda

Day 1

� Introduction to the SoC Encounter Environment

� Logical Synthesis and Scan Insertion

� Silicon Virtual Prototyping

� Hierarchical Floorplan Generation

� Detailed Block Implementation

Day 2

� Top-Level Implementation

� Chip Assembly and Sign-Off

� Chip Finishing

� Timing and Signal Integrity Closure

� IPO and Physical Optimization

� Postmask ECO Flow


Customer Support and Documentation

PCR R&D

CustomerSupport

Service Request

SourceLink® OnlineCustomer Support

http://sourcelink.cadence.com� Search the solution database and the entire site. � Access all documentation. � Find answers 24x7. � Submit a service request online.

� Track a service request (SR).

Quick access to support for questions, advice, or status checks. Support is available from 7:00 a.m. to 7:00 p.m., CST.

1- 877- CDS 4911 (1- 877- 237- 4911)If your request does not require that you send data for someone to analyze, then call the hotline.

If you don’t find a solution on the SourceLink site, you can send email or call customer support. E-mail

[email protected] can send a service request by e-mail. Include details and data or pointers to the data to illustrate the problem.

[email protected]

You can send a service request by e-mail. Include details and data or pointers to the data to illustrate the problem.

If your problem requires more than customer support, then a product change request (PCR) is initiated.

March 3, 2004

®

Introduction to SoC Encounter

Module 1


Cadence Products at a Glance

Sign-off Extraction and Power Analysis

WRoute

Hierarchical partitioning

Virtual prototyping /Placement (Block/Cell)

Signal IntegritySign-off Analysis

NanoRoute

Physical Optimization

RTL/Datapath/Low Power Synthesis BGXPKS

PKS

SE-Ultra SE-DSM

SE-PKS

SE-PKS

Fire & Ice QXC, VoltageStorm

Celtic Analyzer

Ensemble (+ standalone synthesis)Encounter

FirstEncounter

Ultra

NanoRouteUltra

NanoEncounter

SoCEncounter

RouteAccelerator


The SoC Encounter Window

Floorplanning Icons

Design Views

DesignDisplay Area

Auto Query of Objects

Pull-Down Menus

Toolbar Icons

Satellite Window

Display colors


SoC Encounter Design Flow

Optimized NetlistMapped Constraints

Final NetlistRouted Database

RTL Design DataInitial Constraints

Logic Synthesis andScan Insertion(BuildGates)

Hierarchical Virtual Prototyping and

Physical Implementation Environment

(SoC Encounter)

Chip Finishing(VCE)

Design Entry


SoC Encounter Design Flow

Silicon Virtual Prototyping

Hierarchical Floorplan Generation

Detailed Block Implementation

Top-Level Implementation

Chip Assembly and Sign-Off

Logic Synthesis/Scan Insertion

Design Entry

Chip Finishing

BuildGates

SoC Encounter

Virtuoso/VCE

March 3, 2004

®

Logic Synthesis and Scan Insertion

Module 2


Logic Synthesis and Scan Insertion

BG/PKS

Third Party

RC

Optimize/Map Netlist

Design-For-Test Configuration

Scan Insertion

Preplacement Optimization

Netlist Generation

Constraint Generation

Scan DEF Generation

RTL Design Entryand Constraint Definition


RTL

Constraints

Netlist MappedConstraints

ScanDEF

CustomWLM Floorplan

JTAG/BIST GenerationCustom WLMs can be

generated by the Encounter engine.

If you use PKS for preplacement

optimization, then provide the floorplan.

TechnologyLibraries


Logic Synthesis and Scan Insertion Steps

Input Files� RTL design data

� Timing constraints

Steps� Optimize and Map the Design

An RTL description of a design can contain a mixture of high-level statements, gate-level netlists, and custom blocks.

Use RTL Compiler (RC) tool to optimize and map the RTL. RTL Compiler is the next generation synthesis tool for multimillion-gate designs.

� DFT Configuration

Test synthesis is performed prior to and during optimization.

� Scan Insertion

The tool which inserts the scan components into the design will also output a scan order file. This file contains the order in which scan components need to be connected.


Logic Synthesis and Scan Insertion Steps (continued)

� Preplacement Optimization

Preplacement optimization is run before place-and-route to produce a more optimized netlist which is more likely to meet timing after place-and-route. You can use custom wire load models in subsequent runs of optimizations to use more realistic models than the generic wire load models which are typically used in the initial stages of synthesis.

� Scan DEF Generation

The Scan DEF file (scanDEF) is a subsection of the DEF file format. It is used to describe the scan chain configuration and the set of reorderable scan chains present in the netlist.

� JTAG/BIST Generation

JTAG (boundary scan) and BIST (built-in-self-test) components are used to isolate manufacturing defects in chips. JTAG/BIST generation is performed with third party tools.


Logic Synthesis and Scan Insertion (continued)

Output Files

� Optimized gate-level netlist

� Mapped constraints

� Scan order DEF file

March 3, 2004

®


Module 3



SoC Encounter

Optional



Chip Assembly and Sign-off



Netlist

Timing and Clock

Constraints

IOPlacement

Specify/Refine FloorplanAdd/Delete/Modify

� Module guides

� Fences (shaping/sizing)

� Blockages (place/routing)

� Assign block locations

� Power plan

I/O, P/G Placement, or Flip Chip

JTAG Placement

CTE TA (no net loading)*

Trial Routing/Extraction/CTE

Amoeba Placement***hardmacros and cells

Scan Chain Reordering

No

Power Analysis


IPO

Clock Tree Synthesis


Power Planning (rings/stripes)

* Check constraints.

***Depending on design size, you can use floorplanning mode or ClusteringPlace for increased capacity.

VendorFloorplan

Timing/RoutingIssues

Power Issues

Timing Issues

Timing IssuesClock Issues

Floorplan / Fences

Timing/CTSConstraints

To Hierarchical Floorplan

Implementation

Block Placement**

** Place top-level modules and blackboxes.(Used in an all-block design)


Virtual Prototyping Steps

To create a virtual prototype, complete the following procedure:

� Run timing analysis.

Analyze timing with the Common Timing Engine (CTE) using zero net loading to determine whether the initial design meets timing requirements.

� Place I/O, power, and ground pads.

During this step, you have the option of reading a file that contains coordinates for pad placement or pad ordering information. You must include power and ground pads in the I/O file.

� Place JTAG cells.

Specify and place JTAG cells near the I/O cells. Once placed, they will not be moved in subsequent placement runs.

� Place the blocks in the design if you have an all-block or channelless design methodology.

You can use the Encounter block placer or manually place blocks.


Virtual Prototyping Steps (continued)

Specify and Refine the Floorplan

� Defining Module guides and fencesDefine the initial placement guides for key modules. Guides tell the placer to place a specific module’s cells near the guide location. Alternatively, fences can be used. After a fence is created, components that belong to the fence will not be allowed to go outside the fence boundary.

� Shaping and Sizing Fences Refine the shape and size of fences to align the fences manually, using relative placement to preserve relationships between fences and to keep fenced areas in specific locations. Correct the aspect ratio and size of the fenced areas. As an alternative, you can run the automatic block placer. The goal of this step is to make sure that when blocks are committed later in the process, you can successfully implement the blocks individually, and the design as a whole.

� Adding Placement and Routing BlockagesAdd placement or routing blockages to clear routing channels in congested areas. For example, if there is heavy congestion around the corner of a block, add a placement blockage to relieve the congestion in that area.



Refining the Floorplan

� Adjust block placement locations.

Adjust block placement manually, if necessary.

� Power plan.

Optionally, define Multiple Supply Voltages (MSV), and define the power rings and power stripes. You can save the power plan to a file after achieving a satisfactory initial structure. Typically, you do this step only if you use a predefined power structure in the design.



� Run Amoeba placement. Use the Amoeba placer to place cells in the design. The placer places cells according to module guide and fence constraints. Running placement and analyzing the congestion lets you quickly gauge the feasibility of the design in meeting timing and placement density goals.

� Reorder scan chains.

Refine the initial scan-chain order based on Amoeba placement results. Although changes made at this step are not used after the initial floorplanning, this step is still recommended for reducing wire length for a more accurate analysis of congestion. Refine the initial scan-chain order based on the most recent Amoeba placement results.

� Run power planning. Define the power rings and power stripes.



� Run trial routing.

Use the trial router to route the design. Examine the congestion map and the report to identify congested areas. Use the prototyping option of Trial Route to gauge the routability of the design.

� Extract RCs. Extract parasitic resistance and capacitance (RC) values to calculate delays based on the wire lengths determined by trial routing.

� Analyze timing to find timing violations.

Although timing at this stage is likely to have many violations, you can still discover useful information. Analyze the timing to determine how to alter the floorplan.



� Define clock tree constraints, such as insertion delay and skew limits.

Synthesize the clock tree. Analyze the clock tree reports to determine if timing constraints have been met. At this stage, netlist changes are not passed forward. A clock tree is generated to determine clock and timing issues with the current floorplan.

� Run trial routing, extract parasitics, and analyze timing.

Run trial routing. Perform parasitic extraction to determine net RCs. Analyze the timing to determine whether the initial design meets timing requirements. If it does not, then rearrange the module guides. If timing issues remain after several floorplan iterations, you might need to change the RTL.

� Run in-place optimization (IPO).

Run in-place optimization, which adds buffer cells, resizes gates, and fixes design rule violations. Although netlist changes made at this stage are not kept, in-place optimization is necessary for assessing potential timing issues with the current floorplan.



� Run trial routing, extract parasitics, and analyze timing.

If timing issues remain after several floorplan iterations, you might need to change the logical netlist. If no satisfactory floorplans are found, you might have to alter the RTL of the design.

� Analyze power.

Perform power analysis. Note that the power plan will be refined in the next procedure.

� Save the floorplan.

Save the floorplan file to pass to Floorplan Refinement.


Virtual Prototyping Commands

� Use the loadConfig command to load the configuration file into the SoC Encounter environment.

� The setCteReport command sets the report format to the Common Timing Engine (CTE).

� When you run the buildTimingGraph command with the -ignoreNetLoad option, you ignore the loading due to nets.

� The reportTA command generates a timing analysis report.

� Use the specifyJtag and placeJtag commands to specify and place the Jtags in the design.


Virtual Prototyping Commands (continued)

� Place the critical blocks in the design using the placeInstancecommand. Instead of the placeInstance command, use the Move icon to move blocks and instances to the core area.

� Use the addRing and addStripe commands to create the power rings and stripes around the core area and power rings around the blocks.

� Use the amoebaPlace command to place the cells and the blocks which have not been preplaced. The -timingdriven option places the cells in timing-driven mode and requires a constraints file. Otherwise, the cells will be placed in congestion mode.

� Next, you create floorplan guides, which you might later convert to fences. The command to create guides is createGuide.

� After placement, you can run trial route and extraction using the trialRoute and extractRC commands. View the congestion map to determine if there are any hot spots in your design that might lead to routing problems downstream.


Virtual Prototyping Commands (continued)

� If there are timing violations, you can run In-Place Optimization using setIPOMode and fix the violations using fixSetupViolation.

� After fixing setup violations, run clocktree synthesis. First specify the clock tree synthesis file, and run clock tree synthesis using the ckSynthesis command.

� After checking setup and hold time with the actual clock (instead of the ideal clock) you can run power analysis to analyze the power consumption and IR drops in the design, using the updatePower and displayRailAnalysisResults commands.

� Finish the virtual prototyping stage by saving the design and the floorplan with the saveFPlan and saveDesign commands.


Lab Exercises

Lab 1-1 Virtual Prototyping

March 3, 2004

®


Module 4


Hierarchical Floorplan Generation Flow

Physical Partition Definition

Commit Partitions

Detailed BlockImplementation

Top-LevelImplementation

Block LEF(s)

Block TLF(s)

Top-LevelNetlist

FloorplanPlacement

BlockNetlist

BudgetedConstraints

Floorplan/Placement

SoC Encounter

InitialNetlist

Trial Routing

Save Partitions

Pin Optimization

Time Budget

Push Down Power

Partition Clockand TimingConstraints

FencedFloorplan

Amoeba Placement

Timing or Congestion Problem

SVP




SiliconVirtual Prototyping


Power Analysis

Parasitic Extraction/CTE TA

Parasitic Extraction/TA

Power Routing

IPO with -honorPartition

Trial Route (use -honorPartition)

BoundaryVoltages

LEF Generation

TLF/STAMP Generation

TimingProblems

PowerProblems


Inputs to Hierarchical Floorplan Generation

The following information is needed for this stage:

� Initial netlist

� Timing and block constraints

� Fenced floorplan


Hierarchical Floorplan Generation Steps

� Define the physical partitions.

� Change fences to partitions.

� Run Amoeba placement.

� Run timing-driven placement based on the partitions you defined. This will place the remaining cells at the top level of the design.

� Run trial routing, extract parasitics, analyze timing.

� Route signals based on partitions, and examine the congestion map. If congestion is acceptable, proceed to extract parasitics. If congestion is unacceptable, refine the floorplan by beginning with detailed block placement.

� Extract parasitic RC values to calculate delays based on the wire lengths determined by trial routing.

� Analyze timing using CTE to determine whether the floorplan, based on the partitions you chose, meets timing constraints. If timing constraints are met and congestion is acceptable, commit the partitions. If they are not met, go back and refine the floorplan.


Hierarchical Floorplan Generation Steps (continued)

� In-Place Optimization (IPO)

� To create the best budgets for the blocks, the design is run through IPO to optimize the timing. The IPO option -neverAddPort will run IPO without creating any additional module ports. Use this option to avoid changes to the block port lists at this stage.

� Run trial routing, extract parasiitics, analyze timing.

� The design is routed, extracted and timed again.

� Route power.

� Power is routed to the blocks and the components.

� Analyze power.

� Power analysis must be done prior to partitioning so that power budgets can be created for the partitions.



� Commit Partitions

� Make a final decision on the partitions to implement as separate blocks. Committing partitions creates fences, which constrain the module to a specific location without making a final commitment to the location.

� Committing partitions automatically does the following:

� Optimizes pins.� For each block, the pin optimization places pins along the edges of the block.

The pin optimizer uses trial routing to determine the optimal pin placements.

� Creates the timing budget. � Distributes timing delays: latch-to-pin within modules and pin-to-pin between

modules.

� Pushes power into blocks.� Pushes stripes and rings down into the blocks. The blocks inherit the power

structure from the top-level floorplan.



� Save Partitions

� When the partitions are saved, a directory for each block is created. Its netlist, floorplan, and budgeted constraints are saved in the directory. The cell placements within the partitions can optionally be saved as well.

� A directory is also created for the partitioned top level. The top-level netlist, floorplan, and updated constraints are saved into it. In addition, a simple timing model (STAMP) and LEF model is generated to represent each block that is instantiated in the netlist.


Hierarchical Floorplan Generation Commands

In addition to the commands in the Silicon Virtual Prototyping stage the following commands are used in Hierarchical Floorplan Generation:

� The createPartition command changes the guides to fences for the specified module of a hierarchical design.

� The createPtnCut creates partiton cuts so that core rows are cut out from the partition area at the top level.

� The partitionPlace command runs a two-phase placement to better handle the partition flow to assign pins more accurately and reduce the routing congestion.

� After committing the partitions, save the partitions using the savePartition command. Saving the partitions saves the timing and LEF models in the partition directory.


Results of Hierarchical Floorplanning

The following data is generated for top-level floorplan implementation:

� Block LEFs

� Block timing models

� Top-level netlist

� Top-level block placement

� Top level timing constraints

The following data is generated for detailed block implementation:

� Block netlist

� Floorplan and placement information

� Budgeted timing constraints

� Boundary Voltages


Lab Exercises

Lab 2-1 Implementing the Hierarchical Floorplan

March 3, 2004

®


Module 5


Detailed Block Implementation Flow

DifficultTiming

Physical OptimizationFlow

Encounter

NanoRoute

Celtic

Sign-off extractor

Optional Step

Equivalence Checker

Sign-off Power GridAnalysis

From Hierarchical Floorplan Generation

Floorplan/Placement

BudgetedConstraints

BlockNetlist

SI Closure

OA

DEF

SPEF

Netlist

GDSIINoiseModel

To Top-Level ImplementationTimingModel

LEF

PowerModel

To Chip Assembly and

Signoff

* SoCE Detailed extraction with -assumeMetalFill.

Timing-Driven Placement


Trial Route/ Parasitic Extract/CTE

High Effort IPO


Trial Route/Parasitic Extract/CTE

Extraction*TD Route with SI awareness

Timing/SI Closure Flow

Congestion Optimization

Slew Balancing

High Effort IPO


Power Grid Analysis

Noise Model Generation

Output DEF, GDS or OA,Netlist and Spef

Timing Model Creation

Equiv. Check

IPO

Skew Clock Post CTS


Inputs to Block Implementation

� Block netlist

� Timing and clock constraints for the block

� Floorplan and placement information

� Boundary voltage for VoltageStorm® power analysis


Block Implementation Steps


After starting a new session in the block directory, read in the block netlist and floorplan. Use the constraints from Hierarchical Floorplan Generation and place the block in timing-driven mode.

� Reorder scan chains.

Reorder scan chains to relieve routing congestion.

� Run trial routing, extract parasitics, and run timing analysis.

The block is routed and extracted. Then, the timing of the block is analyzed. For blocks with very difficult timing, you might have to run PKS (physical synthesis) to optimize and restructure the netlist.


Block Implementation Steps (continued)

� Run high-effort in-place optimization (IPO).

� Run congestion optimization. Running the congOpt command affects placement and has the benefit of preventing downstream signal integrity (SI) issues.

� Balance slews. Balancing slews is a part of the flow that prevents SI problems by upsizing or downsizing components that are close to each other. This process minimizes the effect of aggressor on the victim due to differences in their slew rates.

� Run high effort IPO again.

� Synthesize the clock trees in the block. Select the option to generate a Macro model for the block when synthesizing the clock tree. The information in the Macro model file contains the insertion delay for the block that will be used later when implementing the top level.

� Run trial routing, extract parasitics, and run timing analysis. The block is trial routed, extracted, and the timing is again analyzed, this time with propagated clocks.



� Run high-effort in-place optimization (IPO).

When you run IPO with the -highEffort option, physical synthesis optimization commands run on paths with timing closure challenges.

� Do a useful skew analysis and implementation for paths whose timing is hard to close with IPO.

Post-CTS useful skew performs time-borrowing by inserting buffers/inverter pairs or

resizing cells on clock nets.

� Run trial routing, extract parasitics, and run timing analysis.

� Run routing with signal integrity options.

The NanoRoute tool will use soft spacing as a method to prevent long wire from running next to each other, thus reducing the possibility of crosstalk effects.

� Run extraction.

� Go to the timing/signal integrity closure subflow.



� Run power analysis. Assuming that the netlist is clean, use the Encounter engine to run a power analysis, and then use the VoltageStorm power analyzer to run an IR drop analysis. At this point, the block is essentially complete and the rest of the steps involve creating various representations of the block to use during top-level implementation and chip assembly.

� Create an Echo model. To create an Echo noise model for the block, run the CeltIC tool in the Encounter engine or in standalone mode.



� Generate LEF, DEF, GDS/OA, netlist, and SPEF. The Encounter tool can directly generate a GDSII representation of the block. In addition, it can also create an OpenAccess (OA) database for the block. The database can be read by the Virtuoso Chip Editor (VCE) during chip assembly in place of the GDSII. A block power model, consisting of a power grid model and a power consumption value, can be created to represent the block during top-level power analysis.

� Create a timing model. Create a detailed and characterized TLF or .lib blackbox timing model of the block. The STAMP model that was created during partitioning in the hierarchical floorplan generation was only a simple one-dimensional representation of the block and contained no load- or slew-dependent timing information.

� Run an equivalence check. Because the netlist has been modified, run a formal verification tool to ensure that the changes that were made did not change the logic or the functionality of the netlist.


Block Implementation Commands

� To fix setup violations, use the IPO command fixSetupViolation.

� If there are hold violations, fix them by running fixHoldViolation.

� If timing does not converge using the IPO commands in –highEffortmode, run the runPhySyn command on the design.

� Report and optimize leakage power by running reportLeakagePowerand optLeakagePower.

� Optimize the clock tree for the block and save the clock tree macro model using the ckSynthesis command and the -macromodel option. The saved macro model will be used later in top-level clock tree synthesis.

� Add filler cells using the addFiller command.

� Use NanoRoute to route the critical nets first, and then route the remaining nets. The globalDetailRoute command runs NanoRoute.


Block Implementation Commands (continued)

� Add metal fill using the addMetalFill command. Verify the geometry, connectivity and antenna to make sure that the addition of filler cells and metal fill did not violate any design rules. The verification commands are verifyConnectivity, verifyGeometry and verifyProcessAntenna.

� Fix block-level crosstalk violations using fixCrosstalk.

� Extract the block by using the Fire & Ice® runQX command.

� Generate the .lib or TLF timing model and the OpenAccess database for the block using the genTlfModel and oaOut commands.


Output of Block Implementation

The result is a placed and routed block.

The output files are:

� DEF file

� Verilog® netlist

� LEF file

� SPEF file

� OpenAccess database

� Timing Model

� Power Model

� Noise Model

� GDSII file


Lab Exercises

Lab 3-1 Detailed Block Implementation

March 3, 2004

®


Module 6


Inputs to Top-Level Implementation


� Floorplan and hard block placements

� Top-level constraints





High effort IPO

CTS

High effort IPO

Trial Route/Parasitic Extract/TA

Skew clock post-CTS

Extraction*

Timing-Driven Placement

Import Block Model Data

Repeater Insertion

Congestion Optimization

Slew Balancing

Trial Route/Parasitic Extract/TA

TD Route with SI awareness

Hier Timing/SI Closure Flow

Hier Power Grid Analysis

Output top-level DEF, GDS or OpenAccess,

Netlist and SpefEquivalence Check

DifficultTiming

Physical Synthesis

* SoCE Detailed Extraction with –assumeMetFill

To Chip Assemblyand Sign-Off

OA

DEF

SPEF

Netlist

GDSII

SI Closure

SI Analysis and Repair

TimingModels

NoiseModels

AntennaModels

From Hierarchical Floorplan Generation

From Block Implementation

Top LevelNetlist

PowerModels

Floorplan Constraints

IPO Useful Skew pre-CTS

Encounter

NanoRoute

Celtic

Sign-off extractor

Optional Step

Equivalence Checker



Top-Level Implementation Steps� Import the Block LEF files.

Update the configuration file to import the block LEFs.


Run placement on the top level, leaving block placement fixed.

� Re-order the scan chains.

The placed scan chains at the top level are re-ordered to relieve routing congestion.

� Run trial routing, extraction, and CTE timing analysis.

The top level is routed and extracted. The timing is analyzed. Use a sign-off extractor to extract top-level parasitics. Signal integrity and timing optimization are done simultaneously by the Encounter engine. Leakage power is also optimized by resizing gates in this step.

� Run high effort IPO.

� Insert repeaters.

Repeaters are inserted after crosstalk prevention has been implemented.

� Run congestion optimization.

� Balance slews.


Top-Level Implementation Steps

� Run high-effort in-place optimization (IPO). Run high-effort IPO with restructuring to fix setup and hold violations.

� Run Useful Skew Pre-CTS.

� Run clock tree synthesis.

� Do trial routing, extract parasitics, and analyze timing. The design is trial routed, extracted, and timing is again analyzed – this time with propagated clocks.

� Run high-effort IPO.

� Do clock skew. Do a useful clock skew post CTS.

� Run trial routing, extraction and timing analysis

� Run routing with signal integrity.

The NanoRoute tool runs signal integrity and timing-aware detailed routing. This tool is integrated natively into the Encounter executable and runs from the same in-memory data structures.


Top-Level Implementation Steps (continued)

� Extract the design.

Extract the design using either the Encounter detailed extraction or the Cadence® Fire & Ice® QX extractor. Both are available in the Encounter cockpit.

� Run the timing optimization and signal integrity subflow.

� Run a hierarchical power grid analysis.

Run power and an IR drop analysis using the Encounter or VoltageStorm® tools. The VoltageStorm tool requires an additional license.

� Generate top-level GDSII/OpenAccess, DEF, Verilog® netlist, and SPEF.

At this point, the top level is essentially complete. An OpenAccess (OA) database and GDSII file can be created for the top level. The database can be read by DFII during chip assembly instead of the GDSII.

� Run an equivalence check.


Example of Repeater Rule fileCommand

insertRepeater {-rule ruleFile | -template} [-selNet selNetFile] [-excNet excNetFile]

Example Rule File

# Buffer Drive Strength Cell Max Wirelength Total Cap

# Name Microns pF

SetBufferDrivingStrength BUFX16 1200 2.5

SetBufferDrivingStrength BUFX20 1500 3.0

SetInvertorDrivingStrength INVX20 1500 3.0

# Block Output Drive Strength (Optional to customize)

SetCellDrivingStrength alu 50 0.5

SetCellDrivingStrength rpt_blk 2500 5.0

# Block Input Load (Optional to overwrite timing library values)

SetCellReceiverLoad alu 50 0.05

SetCellReceiverLoad rpt_blk 50 0.05

# Default Block Drive Strength

SetDefaultDrivingStrength 2000 4.0


Output of Top-Level Implementation

The result is the placed and routed design and these outputs:

� Top-level GDSII


� Top-level SPEF

� Top-level DEF

� Top-level OpenAccess database


Lab Exercises

Lab 4-1 Top-Level Implementation

March 3, 2004

®


Module 7



To Chip Finishing

TimingConstraints

Full-Chip Timing Simulation

From Block ImplementationFrom Top-Level

Implementation

Stitch Stitching SPEFor Flat SPEF

BlockOA’s

Top-LevelDEF

Top-LevelSPEF

Top-LevelNetlist

Top-LevelGDSII

BlockGDSII

Full-ChipSDF

BlockSPEFs

Full-ChipSPEF

Top-Level OA

BlockDEFs

BlockNetlists

Flatten (unpartition)

Full-Chip Power Grid Analysis

Full-Chip Parasitic Extraction

Full-Chip Timing Analysis

Full-Chip SI Analysis

Use SignalStorm for delay calculation.

Encounter

Celtic

Sign-off extractor

Optional Step

NC Verilog








Inputs to Chip Assembly and Sign-off

At this stage, you bring together the top-level and block-level design information to flatten the design and to run a final analysis.

Inputs

� Top-level DEF

� Block-level DEF


� Timing constraints

� Block netlist

� Full-chip DEF


Chip Assembly and Sign-Off Steps

� (Optional) Flatten the design.

Flatten the design by merging the top-level and block-level DEF files.

� Run a full-chip power analysis.

Use the VoltageStorm® tool to perform a power analysis.

� Extract full-chip parasitics (optional).

Use the Fire & Ice® QX extractor to run a flat extraction to derive all parasitics,including potentially undetected coupling between routing at the top-level and in the blocks. Either a 64-bit full-chip parasitic extraction can be performed on the flattened design, or the SPEFs from the top level and the blocks can be stitched together for 64-bit timing and SI analysis.


Chip Assembly and Sign-off Steps (continued)

� Run a full-chip timing analysis.

Use the Encounter engine in CTE mode to analyze the timing. You can run either a full-chip extraction on the flattened design, or stitch the SPEFs from the top level and the blocks together for timing and signal integrity analysis.

� Run a full-chip crosstalk analysis.

In the Encounter engine, read the SPEF file generated by the extractor, the top-level netlist, the timing constraints file, and the netlists for all the blocks. Use the CeltIC tool to run a full-chip crosstalk analysis.

� Generate a full-chip OpenAccess database.

Generate the OpenAccess database files using the oaOut command.

� Generate a full-chip SDF file (optional).

If the methodology calls for dynamic simulation in the sign-off process, an SDF file can be produced to feed the NC-Verilog® simulator.

� Run a full-chip timing simulation (optional).

Run a full-chip timing simulation if possible.


Chip Assembly and Sign-Off Commands

� If the design is hierarchical, one of the main steps at this stage is to flatten the database.

To flatten the database, you need to unpartition the design using the flattenPartition command.

� You can then run extraction, delay calculation, SI analysis, and power analysis on the flat design.


Outputs of Chip Assembly and Sign-off

The outputs of chip assembly and sign-off include:

� Full-chip Verilog netlist

� Top-level GDSII

� Block-level GDSII

� Full-chip OpenAccess database

March 3, 2004

®

Chip Finishing

Module 8


From Chip Assemblyand Sign-Off

Layout Finishing/Editing

Physical Verification

Import Top and Block GDSIIImport Top and Block OA DBs

Chip Finishing

RTMGDS

Errors?Yes

Import Std Cell GDSII/OA

Need to import eitherOA DBs or GDSII

* ModifiedOA DB

*Non ConnectivityModifying edits

* Modified OpenAccess database can be read back into SoC Encounter.

BlockOA’s

Top-LevelGDSII

BlockGDSII

Top-Level OA

Restore OpenAccess Design

Verify/Extract/TA

Assura

Encounter

VCE

Optional Step


Inputs to Chip Finishing

Import one of the following formats into Virtuoso® Chip Editor (VCE) or a layout editing tool to complete the flow:

� Top-Level GDSII and Block-Level GDSII

� Top-Level OpenAccess database and Block-Level OpenAccess database

� Full-Chip OpenAccess database


Chip Finishing Steps

� Import the GDSII layouts for the standard cells into a DFII database.

� Import the OpenAccess databases or GDSII files for the top level and for the blocks, or import the full-chip OpenAccess database.

� Run layout finishing.

Layout finishing steps include adding scribe lines, adding fiducials, adding alignment marks, and adding test fixtures.

� Run physical verification.

After the layout finishing steps are complete, run a sign-off-level physical verification with Assura to look for any design rule violations. If any are found, they can be corrected in Virtuoso® and the layout finishing steps might need to be redone. When the design passes error free, then masks can be generated and the chip fabricated.


SoC Encounter VCE Flow Steps

� Library Creation for VCE

� Use the lefin program (the DFII version of lef2oa) needs to create correct techfile information and abstract cellviews for VCE.

� Complete your design in SoC Encounter.

� Save the floorplan file.

� Needed when restoring design in SoC Encounter.

� Output an OpenAccess database from the Encounter environment.

� Open the OpenAccess database in VCE.

� Edit the database in VCE.


SoC Encounter VCE Flow Steps (continued)

� Save the OpenAccess database in VCE.

� Import a design in SoC Encounter.

� Restore floorplan from the previous Encounter session.

� Clear floorplan to remove any special routing (power, ground, signal).

� Load the OpenAccess database from VCE into SoC Encounter to update wiring and placement.

� Use the Encounter commands for verification, timing analysis, and other tasks.

� Repeat loop as required.

� You can produce a GDSII stream from either VCE or SoC Encounter.� Usually VCE is used, because the GDSII stream file needs to include

scribe info and other data that typically does not exist in the Encounter database.


Lab Exercises

Lab 5-1 Chip Assembly and Sign-Off

March 3, 2004

®

Timing and Signal Integrity Closure

Module 9


SI Analysis

Timing Analysis Setup/Hold

Extracted Design w/Metal Fill Assumed in Extraction

Timing and Signal Integrity (SI) Closure Flow

Add Filler Cells (postroute)

Detailed Extraction

Fix Crosstalk

Wire Editing

Add Metal Fill

SI-Aware ECO Route

Fill Notch

Encounter

NanoRoute

Sign-off extractor

Celtic

IPO fixSetupViolations

IPO fixHoldViolations

Verify Metal Density

Verify Geom./Conn./Ant.

Timing Analysis Setup/Hold

SI Analysis


Timing and Signal Integrity Closure Steps� Run timing analysis to determine if there are violations in your design.

� Run in-place optimization and fix setup and hold violations.

Set the IPO mode using the setIPOMode command. You can set the mode to -highEffort, which will automatically call synthesis optimization transforms to meet timing.

Use fixSetupViolation and fixHoldViolation to fix timing violations in your design.

SyntaxinitECO ipo.txt fixSetupViolation endECO

Bracketing the IPO commands with the initECO and endECO commands will log the changed components in the ipo.txt file.

� Run a signal integrity-aware ECO route using NanoRoute.

� Run a signal integrity (SI) analysis.

� Fix crosstalk.

Use the fixCrosstalk command in signoff mode to run the CeltIC™ and NanoRoute™

tools to iteratively analyze and fix the signal integrity violations in the design. Fixing crosstalk involves fixing glitches and also the delay due to noise.


Timing and Signal Integrity Closure Steps (continued)

� Add filler cells. � Adding filler cells after routing will not cause DRC violations in the design because

the tool will analyze potential violations before selecting the appropriate filler cells from the physical library.

� Use the addfiller command to add filler cells to your design.

� Add metal fill. � Use the addMetalFill command with the -layer option.

� Fill notches. � Filling notches at this stage is necessary to prevent errors downstream in tools

which check masks for notches and gaps.

� Verify metal density.

� Verify geometry, connectivity, and antenna. � The verifyConnectivity, verifyGeometry and verifyProcessAntenna commands

generate markers and error logs of the DRCs in the design.



� Extract the design using the Fire & Ice® QXC tool. Assume metal fill for the extraction.

� Run a signal integrity-aware ECO route using the NanoRoute tool.

� Run a timing analysis and fix setup/hold times.

Command Syntax for IPO and Timing ClosuresetIPOMode –high

fixSetupViolation

fixDRCViolation

fixHoldViolation



Signal Integrity Closure Commands

� The fixCrosstalk command performs an incremental or signoff SI analysis, repair, and RC extraction based on the options that you specify.

� The fixGlitchViolation command creates a violation file for SoC Encounter to fix.

� The fixNoiseDelay command fixes the delta delay caused by noise.This command takes timing into consideration.

March 3, 2004

®

IPO and Physical Optimization

Module 10


Physical Optimization FlowFrom Block or Top-

Level Implementation

Encounter

NanoRoute

PKS

Sign-off extractor

Optional Step

Equivalence Checker

Create Path Groups

Pre-Clock Optimization


TD Global Route

Useful Skew Optimization

IPO

Setup/Hold Fixing

StandalonePKS

Placement Constraints

Run through SoCE/PKS Interface

Full PKSOptimizationCapabilities

Netlist

TD Global Route

IPO

RoutedDEF SPEFOptimized

Netlist

To Block orTop-Level

Implementation


Physical Optimization Flow (continued)

Encounter

NanoRoute

PKS

Sign-off extractor

Optional Step

Equivalence Checker

From Block or Top-Level Implementation

Create Path Groups

Pre-Clock Optimization


TD Global Route

Useful Skew Optimization

IPO

Setup/Hold Fixing

StandalonePKS

Placement Constraints

Run through SoCE/PKS Interface

Full PKSOptimizationCapabilities

Netlist

TD Global Route

IPO

RoutedDEF SPEFOptimized

Netlist

To Block orTop-Level

Implementation


Optimization Transforms

Full set of logical synthesis transforms are available in conventional synthesis, including:

� Restructuring

� Cloning

� Buffering

� Resizing

Each optimization is incrementally placed, routed, and timed.

� Allows millions of logical and physical tradeoffs against highly accurate timing.

� If placement is not possible, logic change is rejected.

LEF,.lib,.alf, .tlf

DEF/PDEF

RTL/Gate-LevelNetlist

TimingConstraints

PKS

Parsing, Structuring, Mapping

accept/reject

Timeusing Steiner Route

Initial Placement

Optimization Transformsrestructure, clone, resize, buffer, etc.

Incremental Placement

101066

Placement Legalization


Group Paths

� By default, PKS optimization works on one path at a time. The path worked on is the one with worst slack. Hence if a path is over constrained, the remaining paths are not optimized.

� Group path command distributes paths into different groups, and the path with the worst slack in each group is now optimized.

� All paths originally start in the default group (default).

� Translator will now automatically translate Synopsys group_paths command to the BuildGates equivalent Tcl command.

Example

set_path_group –name IO –from [find –input]


Physical Optimization Steps

� Create the path groups.

� Path groups are recommended to isolate specific areas of the design. This helps to assist in uncovering areas that are prone to closure issues and allows the optimizer to close timing on the rest of the design.

� Run preclock optimization.

� Run pre-CTS useful skew.

� Run clock tree synthesis.

� Synthesize the clock tree. Analyze the clock tree reports to determine if constraints have been met.

� Run a useful skew optimization.


Physical Optimization Steps (continued)

� Run timing-driven global routing.

� Global routing creates the route plan for the detail router. The extraction and timing analysis at this stage will provide you with an accurate picture of what to expect after detail routing.

� Do in-place optimization (IPO) if there are timing errors.

� Run the design through IPO to optimize the timing.

� Rerun global routing.

� Because the netlist has been modified, the route plan has to be re-created.

� Rerun in-place optimization, if there are violations.


IPO Strategies

IPO has two major phases:

� Global optimization phase (also known as weed-whacking)

� Transforms are applied to all violating nets/instances in a global pass.

� Critical path fine tuning phase (high effort only)

� Transforms are applied to a small critical range of the violating nets/instances

IPO refines placement, runs trial route, runs extraction, and updates timing at the end of each major step.

� Uses incremental trial route for better run times.

� Only nets touched by IPO are rerouted.


Optimizing Setup Timing

In SoC Encounter, IPO has three effort levels:

� Low effort This level performs changes, such as buffering long nets or resizing cells. This step is extremely fast and needs to be used at the prototyping stage.

� Medium effort This level triggers more optimization process than -lowEffort does, and further optimizes the most critical paths. Its target is to get an accurate estimation of the design performance or to close timing on less challenging designs.

� High effort You need to use this level to reach timing closure for challenging designs. It turns on all the physical synthesis optimization transforms.

Syntax

setIPOMode -highEffort


Optimizing Setup Timing (continued)

There are two separate commands for Setup optimization.

� Setup timing optimization after placement

� setIPOMode -highEffort

� fixSetupViolation

� Setup timing re-optimization � setIPOMode -highEffort

� optCritPath

After each individual optimization step, fixSetupViolation performs placement legalization, routing, extraction, and timing updates.


Fixing Setup Using IPO

* = Not by default

After each optimization step, placement legalization, routing, extraction, and timing update are performed.

Use Model

Use fixSetupViolation after placement.

Use optCritPath for re-optimization. reclaimArea

Critical PathsOptimization usingPhysical Synthesis

transforms

Downsize

Buffer insertion

Resize

Resize

Useful Skew *

Reclaim Area

setIPOMode -reclaimArea

setIPOMode -usefulSkew

setIPOMode -highfixSetupViolation

setIPOMode –low/-mediumfixSetupViolation

optCritPath


Downsizing/Resizing

� Initial global pass downsizes gates without worsening violations.

� For medium and high effort, initial resizing does the following:

� What-if analysis for all candidates to be resized without committing the resizes

� Order resize moves in decreasing order of gain

� Commit resize moves in above order, invalidating neighboring moves for each committed move

� Iterate until number of moves found or slack improvement is negligible or maximum # of pass (10) is reached

� Combinational and sequential resizing are done separately.

� A global sizing pass is run to improve DRVs.

� In high effort, second global sizing does a greedy input-to-output pass with more accurate delay updating to guarantee no slack worsening.


Buffering

For each violating net, from input to output,

� The tool chooses a wire topology

� TrialRoute topology

� Topology based on physical clustering (similar to CTS)

� Quick buffering is done for each topology assuming certain capacitive load per buffer.

� The topology with the fewer number of levels of buffers is chosen.

� Buffering prefers trialRoute topology in case of tied results.

� Buffering determines which segment is not bufferable due to no-new-port, and dont-touch constraints.


The optCritPath Command

� Each step operates on a 5% critical range of the violations.

� The optCritpath command optimizes the critical paths and stops when target slack is met or when timing cannot be optimized further.

� It tries to improve the worst negative slack and you must use it each time you want to re-optimize a netlist.

pinswapdeleteBuffer

resizeaddBuffer

resize

Boolean restruct

moveInstances

topoMap

remapCone

mergeInverter

remapGate

setIPOMode -highEffort


Design Rules Violation Fixing

� DRV fixing is done during fixSetupViolation, and the remaining DRVs can be cleaned using the fixDRCViolation command.

� The fixDRCViolation command will loop up to three times to fix the DRV. Use -maxIter <value> to specify the number of loops allowed.

� To check if DRVs are cleaned, use the isDRVClean command.

Reports 0 or 1.

� An extra pass of DRV fixing is run in global optimization phase (weed-whacking).

To report the DRV, use:

reportTranViolation/reportCapViolation/reportFanoutViolation

Use bufferMultiDriverNet to fix all DRV on multidriver nets.


Optimization Guidelines

� Creating a clean footprint file is important.

� No or bad footprint definitions leads to less than optimal IPO results.

� Use the checkFootPrint command after making a footprint file.

� Steps to making a footprint file:

� Generate a footprint file.

� Modify this file to specify the buffer, inverter, and delay cell footprints to separate the cells that you don’t want to use.

� Load the footprint file.

� The IPO process will also respect the set_dont_use attribute.


Optimization Guidelines (continued)

After running IPO, you must examine the remaining violating paths or DRV for the following possibilities:

� Be sure that the Worst path can meet your target slack.

� Use Path Group to further optimize the design.

� If there are remaining DRVs, then call fixDRCViolation.

� Check routability numbers from TrialRoute.

� Check the congestion map to see if worst paths are going throughlocal congestion hot spots.

� If there are congestion issues, then run placement in congestion-driven mode followed by IPO.

� If there are timing issues, try IPO on a design that has been placed using the -timingdriven option.

March 3, 2004

®

Postmask ECO Flow

Module 11


Making Postmask Changes to the Design

Reasons for Making Changes

� Base layers of the design have been taped out and you have foundlogic errors. At the same time, you need to preserve the poly and diffusion layers that are already taped out.

To fix the errors, you need to

� Route to pre-existing spare-cells.

� Change only metal and via layer masks by rerouting to spare cells.

You can create

� A new netlist with minor logical changes based on the old netlist

or

� A new ECO file


Procedure: Postmask ECO with a New Verilog File

To prepare for postmask changes spare cells could have been added to the netlist prior to generating a mask.

There are two ways in which spare cells are added to the design:

� Spare cells are added to the original Verilog netlist.

� Spare cells are identified with this command:

specifySpareGate –inst mySpareInst

� Spare cells are added using a previous spare.eco file:

� ADDHIERINST mySpareInst mySpareCellName

� ADDINST mySpareInst/mySpareAnd_1 AND2

� ATTACHTERM mySpareInst/mySpareAnd_1 IN1 VSS

� ATTACHTERM mySpareInst/mySpareAnd_1 IN2 VSS

� followed by loadECO spare.eco


Postmask ECO with a New Verilog File Read old Verilog® floorplan, placement, routes files into the Encounter engine.

Compare current netlist to new Verilog netlist to create an ECO file.

ecoCompareNetlist -verilog new.v -outFile oldchip.eco

� The ECO file has all changes required to make the current netlist match the new netlist.

� Physical-only cells like filler cells are ignored.

Load the ECO file to update the current netlist to match the new netlist.

loadECO -useSpareCells -suffix _SPARE oldchip.eco

� Instances that only appear in the old Verilog netlist are implicitly deleted by leaving them in place and changing the name (i1/i2/i3 to i1/i2/i3_SPARE). The dangling inputs are attached to GND.

� New instances are placed by using the nearest matching sparecell with the same cell.

� New ports are created on Verilog modules as needed.

� Routing on deleted nets is removed.

� Error messages are output for any unplaced cells.


Postmask ECO with a New Verilog File (continued)

� Incremental route with NanoRoute/WRoute

� Antenna diodes are disabled because poly/diffusion cannot be modified.

� Routers automatically detect opens and shorts, and incrementally route any nets that are incomplete or have violations.

� The old Verilog netlist after ECO might be slightly different from the new Verilog netlist.

� The auto-generated ports and nets probably have different names.


Postmask ECO with a New Verilog File Example Tcl Script

# Read old Verilog netlist into Encounter

loadConfig oldchip.conf

# Read old floorplan, special routes, placements and routing

defIn oldchip.def

# Compare the current old netlist to the new Verilog netlist

ecoCompareNetlist -verilog new.v -outFile oldchip.eco

# Load the ECO file to incrementally update the current netlist to match the new netlist

loadECO -useSpareCells -suffix _SPARE oldchip.eco

# Write out changed Verilog netlist if desired

saveNetlist oldchip_after_eco.v

# Incremental route

setNanoRouteMode routeInsertAntennaDiode false

globalDetailRoute


Comparing Netlists

� The following command compares the currently loaded netlist with a different netlist file:

ecoCompareNetlist {-verilog <file.v> |

-def <file.def>} -outFile <file.eco>

� The ecoCompareNetlist command uses instance names and net names for matching.

� An ECO file (file.eco), or change list, is generated.

� The file has all the changes needed to differentiate the current netlist from the external netlist.

� The file.eco contains the loadECO syntax.

� The Verilog file must already be uniquified.


The loadECO Command and Spare Cell Support

You can use the following command to support spare cells in the design:loadECO[-useSpareCells | -useGACells <GACoreSite>]

[-suffix <suffix>] <file.eco>

-useSpareCells

� For a newly added instance, spare cells are chosen by looking for a spare cell that matches the new cell type and is closest to the pins connected to the new instance.

�When an instance is deleted, it is really renamed as a spare cell� i1/i2/i3 becomes i1/i2/i3_SPARE

� If a net is deleted, any routing attached is deleted

� If a net is modified, any routing attached is not affected

-suffix <suffix>� Suffix to append to new spare cells, default “_SPARE”

-useGACells <GACoreSite>

� Same as –useSpareCells except for GACoreSite type cells.

� New GACoreSite type cells are left unplaced.

� Deleted GACoreSite cells are really deleted.

March 3, 2004

®

Blackbox What-If Timing Analysis

Appendix A


What-If Timing Analysis

The design cycle can start:

� Without blackbox timing models

� With preliminary blackbox timing models (soft IPs)

You can use What-If commands for a powerful and interactive budgeting at the top level of the design.

What-If Timing Analysis:The capability allowing on-the-fly modifications of blackbox timing arcs along with subsequent STA.


Timing Model Normalized

setBlackBoxClockLatencyClock insertion delay to internal registers7

setBlackBoxDriveTypeDriver type Driver input slew Total driver output net capacitance (optional)

4

5

6

setBlackBoxSeqDelaySequential delay from the clock input port to the data outputport, including driver delay

3

setBlackBoxTimingCheckTiming check, delay from the clock input port to the data input port

2

setBlackBoxCombDelayCombinational delay from an input port to an output port, including the driver delay

1

CommandData Type#

6

1

45

2 37

5 4

6


What-If Graphical User Interface


Application Examples

Top-Down Flow

� You can define a preliminary timing model and the constraints of a blackbox in its environment at the top level.

� You can refine timing models and constraints of soft IPs, taking into account a new top-level design environment.

Starting Block Implementation Before Top STA

� After importing the netlist of a blackbox, you can refine its timing budget.

� Run a top-level STA using a timing model from block synthesis. Then, check the model and generate a new set of SDC constraints if needed.

March 3, 2004

®

SoC Encounter Support for TSMC Reference Flow

Appendix B


Crosstalk Prevention Using Encounter

� Placement and optimization stage

� Set max transition to prevent weak victims.

� Avoid the strong aggressors created by sharp transition.

� Postplacement stage

� First Encounter: slew balance and congestion removal

� Routing stage

� NanoRoute: global routing, track assignment, and detail routing with crosstalk prevention

� Prevention effects

� Routing is more effective than placement in crosstalk prevention.

� Target for reducing crosstalk violations is 50% or more per iteration.


Crosstalk Repair Using Encounter

CeltIC — First Encounter — NanoRoute — CeltIC loops

� NanoRoute fixes glitch violations.

� First Encounter fixes timing violation.

Most crosstalk glitches and timing violations are fixed in 3 iterations.

Manual script is used to fix remaining violations.

� High-strength victim nets

� Wire spacing

� Buffer insertion

� Low-strength victim nets

� Cells are sized up.


Encounter Supports Design for Manufacturability in Reference Flow

Design for manufacturability (DFM) provides increased visibility into the manufacturing process.

DFM addresses nanometer challenges, including:

� Uniform density and thickness

� Via placement

� Signal electromigration

� Dynamic IR drop

� LEF spacing and blockage modeling enhancements

� Routing rule support in NanoRoute tool

� Reliability enhancements (such as double cut vias)

DFM is incorporated through design rules, tech files, and scripts.


Redundant Via Insertion Methodology

For Yield Improvement, NanoRoute supports redundant via insertion for TSMC 130 nm and 90 nm technologies.

0.05 µ

(c)

0.05 µ

0.005 µ

0.005 µ

(b)

0.05 µ

0.05 µ

(a)

0.005 µ

0.005 µ

0.08 µ

0.08 µ

(d)

0.08 µ

0.005 µ0.08 µ

0.005 µ

(f)

0.005 µ

0.05 µ

(e)

0.05 µ

(a) (b)(d)(f)

(c)

March 3, 2004

®

Partitioning

Appendix C


Partition Menu

Specify Partition...Specify Black BoxCreate Feedthroughs…Assign Black Box PinsShow Wire CrossingEstimate Routing Channel…Partition…Unpartition…Check Pin AssignmentChange Partition View Changes design view between

chip level and partitions.

Displays Trial Route feedthrough wires that are crossing over a selected partition.

Flattens the partition.

Design Partition FloorPlan Place Clock Route …

Creates the partitions.


Blackbox Options

A blackbox is a special application of the partition.

� Create a LEF file for the hierarchical instance (module, submodule, or block) and enter the file name in the Design Import form.

� After importing the design, dark blue colored blackbox guides appear with the blocks.

� Complete floorplanning with the blackbox.

� Use the command, specifyBlackBox <partitionName> <hierInstanceName>.

� Use the Specify Partition form for blackboxes as well as for partitions.

� You can resize the blackbox. Apply the resizeBlackBox command.

� Run placement and Trial Route.

� Generate blackbox pins by applying the blackBoxPinAssign command.

� The Save Partition form will also create a blackbox subdirectory.


Blackbox Pin Assignment

You need to update the Blackbox abstract file with the pin placements.

Before Black Box Pin Assign

After Black Box Pin Assign


Specifying a Blackbox

The following text commands provide equivalent or additional functionality:� resizeBlackBox� specifyBlackBox� unspecifyBlackBox

Partition – Specify Black Box


Partitioning a Design

� Divides the design task into manageable partitions so that work can continue on several blocks in parallel.

� Partitioning uses the full-chip environment and performs analysis to

� Analyze top-level route congesting from early top-level floorplanning information.

� Optimize pin assignment based on full-chip placed and routed (in-context) results.

� Push down the top-level floorplan objects (power plan, blockages) into each partition if they overlap the partition.

� Generate timing budgets based on full-chip timing analysis. Timing constraints, clock exceptions, and path exceptions are pushed down to all partitions. Stamp models are generated for the partitions.


Results of Partitioning

Results of partitioning are two levels of partition hierarchy — the top-level infrastructure and the partition level.

� Partitioning generates top-level partitions and pushes down floorplan objects to the floorplan file.

� Partitioning generates all the necessary files for the First Encounter engine and other backend tools.

You create partitions that exist:

� Logically A partition is one of the modules or submodules in the design.

� Physically A partition must be completely intact and constrained by a fence.


Steps in Partitioning a DesignSpecifying the Partitions

Directory where the files that belong to the partition will be saved.

The name of the module that you want partitioned.

Layer names are determined from the technology file. The LEF file for the partition will contain obstructions for the unselected layers.

Partition – Specify Partition


Steps in Partitioning a Design (continued)

Core of Partition

Partition Pins

Std Cell RowMin Pin spacing on all sides

Specifying Partition Pins



Partitioning the Partitions

Partition – Partition



Saving the Partition – Creates the infrastructure for the hierarchy.

Design – Save Partition


Specifying a Module to Be a Partition

Specifying the Partitions

� Each specified module must first be floorplanned.

� For multiple instantiated modules to be partitioned you need to uniquify the netlist in the synthesis step of the design process.

� You can change the standard cell row height and place the partition’s pin away from standard cell power rails.


Multiply Instantiated Partitions

Handling Repeated Partitions

� These are multiple instantiated hierarchical instance of same cell type.

� You can choose all or none of them are to be partitions.

� You can choose to modify the netlist, so hierarchical instance names are unique.

� The hierarchical instance entered in the Specify Partition form is the master partition and other partitions are clones of it.

� Clones can have orientation changed using their Attribute form during floorplanning.


Running the Unpartition Program

Use the Unpartition program to remove selected partitions from a design. If changes are necessary for any of the partitions, you can change the partition status from a block to a fence.

Choose Partition – Unpartition.


Deriving Timing Budget Files for Partitions

Proportional will create proportional timing constraints between partitions.

The Trial IPO Estimates option produces proper timing constraints between partitions.

To resolve multiple timing constraints for I/O partitioning

Partition – Partition


Timing Budgeting

Each block requires:

Clock definition

set_input_delay

set_output_delay

set_drive

set_load

Path exceptions

(False, multicycle paths)Block 3

L

Block 1

L Block 2

L

Accurate timing budgets result in predictable timing convergence.


top.vtop.conftop.fptop.fp.spr

top.leftop.constrtop.dattop.deftop.libtop.tlftop.pwr.cmd

par_1.vpar_1.confpar_1.fppar_1.fp.spr

par_1.constrpar_1.constr.pkspar_1.constr.pt

par_1.trk.tclpar_1.defpar_1.pdefpar_1.fp.cmdpar_1.pwr.cmdpar_1.pin.tdf

After Saving Partition

Top Level Files � Partition Files �

Files for FEU

Files for FEU andthird party tools

Deriving Timing Budget Files for Partitions (continued)

� Produces proper timing constraints between partitions.

� Resolves conflict for multiple timing constraints for partition I/Os.

� Makes the timing constraints proportional between top and partitions or can fix the top first.


Timing Budget – Interface Logic Models

� Interface logic models (ILMs) provide an accurate, yet simplified timing models for hierarchical design.

� The original gate-level netlist of a block is modeled by another gate-level netlist that contains the interface logic of the block.

� The logic other than the interface logic is stripped out, thus simplifying the number of computations and shortening the time taken to perform timing analysis.

A

B

X

Y

A

B

X

Y


Partitioning ILMs Bottom-Up Flow

Use the interface logic model (ILM) flow to produce accurate timing analysis for a completed partition design.

To prepare for an ILM flow:

1. Make sure the work directories are created by a partition flow (saving partition).

2. When the design work is complete for all partitions, use the twocommands to derive and save the ILM netlist and SPEF files for each partition.

deriveInterfaceLogic

saveInterfaceLogic -spef

3. To do timing analysis for the entire chip, cd to the top-level directory where the work is complete.


Partitioning ILMs Bottom-Up Flow (continued)

Load top -level floorplan

Run Placement and Trial Route

Design Import with partition ILM files

Completed chip netlist

Load partition SPEF files by:

spefIn -ilm <partition.spef>for all partitions

Top Level

�

With ILM files from Step 2, the First Encounter tool is now in an ILM mode.

Trial Route knows to route to the partition pin locations.

When the timing graph is built, the SPEF data for the partitions are stitched and the SPEF for the top level are automatically extracted and stitched.

NoteWhen restoring the design, you need to stitch the SPEF file for each partition by using the spefIn command.

Timing Analysis and Optimization

Extract RC

Save Design

Flatten ILMs

Un-Flatten ILMsTop-Level CTS and

Detail Route


Partition Floorplan Objects

Partition Pin Blockage — to block area from creating pins on specific metal layers. Select the metal layers to be blocked.

Partition Feedthrough — to assign routing feed through area on a specific metal layers. Feedthrough object must cut through both sides of the partition.

Add Partition Pin Guide — to assign guides where you want to place certain pins on the partition.


Partition Floorplan Object — Partition Feedthrough

You can use Partition Feedthrough to reserve space in a partition for top-level routing and buffer insertion.

This flow is to:

� Create partitions.

� Create partition feedthroughs.

� Commit partitions.

Partition feedthrough affects only the physical aspect of the partition not the logical aspect.

The two types of partition feedthrough are:

� Channel — For top-level routing

� Placement island — For top-level buffer insertion


Partition Floorplan Object – Partition Feedthrough (continued)

� Method 1: Use the Add Partition Feedthrough icon to create the feedthrough buffer on the partition. Double-click the buffer to open the Object Attribute form, specify the metal layer, and click OK.

This creates the channel for the routing on the specified layers at the top level and pushes down appropriate routing blockages at the block level.

� Method 2: To specify narrow feedthroughs or several of them on a given partition, choose Partition – Create Feedthrough to open the Create Feedthrough form.

Use Partition – Create Feedthrough

Partition Feedthrough Floorplan icon


Partition Feedthrough – Placement Island

At partition level, commit partition automatically creates the following:

� Routing blockage(s) for channel feedthrough

� Placement blockage for placement island feedthrough

Partition with Partition Feedthroughs

Channel Feedthrough (layer = M6)

Channel Feedthrough (layer = M5)

Placement Island Feedthrough

Committed Partition

Routing Obstruction (M6)

Routing Obstruction (M5)

Placement Obstruction


Finding Feedthrough Nets

Use the showPtnWireX command to find nets that cross partitions.showPtnWireX [ptnName] [–outfile <partitionCrossingNetFile>]

[-exclude Net <exNetFileName>]

� Use ptnName to generate a file that lists the nets that cross a specific partition.

Use the output file as a starting point to generate a list of nets for feedthrough insertion.

� Not all nets in the generated partition-crossing net file will become feedthrough nets automatically.

� You need to decide which nets to use for inserting feedthrough buffer cells and add them to the excluded nets file.


Partition Feedthrough Buffer Insertion

Use insertPtnFeedthrough for inserting partition feedthrough buffer cells

insertPtnFeedthrough –bufCell <bufCellName>

-selectNet <fileName> | { -chanLess [-excludeNet <fileName>] }

{-doubleBuffer | -nobuffer} [-netMapping]

The -chanLess option specifies that the design is pure channelless, having no channel available for routing, and therefore all nets must be selected for feedthrough insertion.


Partition Feedthrough Buffer Cell (Continued)

Use netMapping to generate a mapping file for the original and new created net names.

Use doubleBuffer to insert 2 buffers for feedthrough nets.

� Insert one buffer close to incoming pin and another one close to an outgoing pin.

� Without this option, the buffer is inserted near the incoming pin.

Technique

� Create new feedthrough pins.

� Insert buffers and modify netlist.

� Run ecoPlace to place inserted buffers.


Partition Feedthrough Without Buffer Insertion

Allow creating logical partition feedthrough without inserting any buffer

� Use the insertPtnfeedthrough –noBuffer option.

� Adds a Verilog assign statement in the netlist of the partition block.

assign FE_FEEDX_new_in_port = FE_FEEDX_new_out_port ;

FE_FEEDX_new_out_portFE_FEEDX_new_in_port

Note: A dummy buffer with FE_DUMMYCELL cell type is inserted inside the data base to represent an assign statement.


Partition Floorplan Objects: Partition Pin Guide

1. You can create ports at the top side, starting left to right.

2. You can create ports at the top and bottom sides of Partition1 (one set of pins will be actually feed-through pins), and create ports at the top side of Partition2, starting left-to-right.

3. You can create ports at the right side, starting bottom-to-top, of Partition1.

1 2

3

Partition1

Partition2

Partition Pin Guide — to create partition port for a net or a bus name. Must overlap partition fence.


Partition Floorplan Objects: Partition Pin Guide (continued)

� Assign net names by changing the partition pin guide’s Name to a net name, bus name (bus_name[#,#]), or net group name.

� For a net group, use these commands: createNetGroup and addNetToNetGroup.

Assign port names by changing the partition pin guide’s name to a port name or pin group name.

� For a pin group, use these commands: createCellPinGroup and addPinToCellPinGroup.

� Then, enter cell type name in the PinGroup Cell field.


Partition Pin Editor Use the interactive pin editor to edit pin properties:

LocationMetal layerPin depth and widthEqual spacingSnapping to metal tracks or Microns.Fixing

Group pins as a bus.

Can list pins as: � All� Side� Unassigned� Other (group)

Choose Tools – Pin Editor.


Channel Width Estimation

� After specifying the partition, you can estimate the required spacing between partitions, blackboxes, and hard macros, and update the floorplan based on the required spacing information.

To estimate the routing channel, use this form:

� This will output an estimate of the required spacing surrounding each partition based on its pins, the relative distance between partition blocks required for top-level routing. This output also includes the estimated distance between blocks and core boundaries (top, bottom, left, right).

To estimate the routing channel, choose Partition – Estimate Routing Channel.


Example Report of Channel Width Estimation

HB2

HB1BB1

INST1

INST3

INST4

INST2

Partition Hard macro Blackbox

Block1 Block2 Current Required

bot-boundary INST1 24.6 28.8bot-boundary INST2 54.3 46.9bot-boundary HB2 25.0 31.2lft-boundary INST1 38.2 45.5lft-boundary INST3 43.2 37.8lft-boundary HB1 46.8 33.5INST1 INST3 64.8 39.4INST1 INST2 72.1 55.7HB1 top-boundary 57.2 10.9HB1 BB1 44.5 69.1INST4 top-boundary 59.5 51.7INST4 rht-boundary 53.0 50.5… … … …… … … …

Instance name

Core boundary edge

Spacing in micron


Channel Width Estimation Constraints

Set the following block placer constraints when adjusting channel widths

� Block halo

� Block-to-block distance (setBlockDistance)

� Block-to-boundary distance (setBlockToBoundary)

� Block order and alignment (setBlockOrderAlignment)

� Net weight (specifyNetWeight)

Reshape blackboxes and partitions to improve congestion

� The Channel Width Estimator honors user-specified block aspect ratio constraint (setBlockAspectRatio).


Global Partition Pin Size

� You can define the global pin size constraint for a specific partition.

� Set the global pin width, the pin depth, or both.

Applies to all pins of a partition that do not have their own pin widths/depths.

Use the setPtnPinWidth and setPtnPinDepth Tcl commands to set global pin width and depth, respectively.

setPtnPinWidth <partitionName> <layerId> <width>

setPtnPinDepth <partitionName> <layerId> <depth>

Width (in micron)

Width

Depth

Depth


Channelless Partitions

Different types of hierarchical design methodology:

� Channel-based (All top-level routing use channels.)

� Channelless (All top-level routing use feedthroughs.)

� Mixed (Some top-level routing use channels; some use feedthroughs.)

Channel-based methodology Channelless methodology Mixed methodology


Channelless Partitions (continued)

Techniques and approaches to insert feedthroughs

� Use insertPtnFeedthrough command.

� Changes the top-level and partition-level netlists.

� Use Partition – Create Feedthrough to create feedthroughs

� No netlist change

insertPtnFeedthrough is recommended for pure channelless or mixed methodology.


Channelless Partitions Simple Methodology Flow

� Design import

� Floorplan a design

� Specify partitions

� Place (with Amoeba)

� trialRoute

� showPtnWireX

� insertPtnFeedthrough

� trialRoute

� extractRc

� buildTimingGraph

� Commit partition

� Save partition


Channelless PartitionsSimple Methodology Flow (continued)

showPtnWireX generates an output file that lists all nets routed over partitions.

You have a choice of inserting feedthroughs for all nets or only for selected nets.

insertPtnFeedthrough can read a file that lists all the top-level nets for feedthrough insertion. This command does the following:

� Inserts buffer or buffers for the feedthrough nets.

� Modifies the netlist.

� Places buffers in the appropriate locations.

� Generates a partition boundary.

� Creates a timing budget with feedthroughs.


Channelless PartitionsExample of Channelless Methodology

Design After Committing Partitions

March 3, 2004

®

Flip-Chip

Appendix D


Flip-Chip Functions

� Supports full flip-chip flow.

� Creates bump MATRIX.

� Creates rows for I/O placement.

� Runs automatic I/O placement.

� Runs signal routing from bumps to I/O.

� Runs power routing from bumps to stripes.

� Supports flat and hierarchical flows.

Chip bumps

Contact pads


Area I/O Features

� Bump and tile flows

� Tile selection

� Bump array and matrix generation

� Bump assignment (signal and power/ground)

� I/O row generation

� Interface to CIOP (route feasibility)

� AIO placement

� Routing

� SRoute power and signal bumps

� Differential routing

� Hierarchical flow – partition

� LEF syntax


Area I/O Flows

SOCECIOP

CIOPRouteFeasibility

I/O file(Bump/Rows)

Partition

Floorplan

Verilog LEF

Bump Flow

Add Stripes

Place AIOAssign Bumps

Route Bumps

Edit Bumps

Route FeasibilityInterface

PlaceCells

RouteDesignBlock Design


Flip Chip: Add Tile Icon

Placing Tiles

� Tiles are a group of bumps.

� Tiles can contain macros and routing.

Add Tile Icon


Flip-Chip and Chip I/O Setup

Create bump array (4x4) to match package balls.


Flip-Chip: Signal Assignment

Select an I/O signal.


Flip-Chip: Signal Assignment (continued)

Signal BumpsBlue = signal assigned CLK

DI[0]


Flip-Chip: Power/Ground Assignment

Select Bumps and assign power

� Red = power

Select Bumps and assign ground

� Yellow = ground

Signal Bumps

� Blue = signal

Signal SignalGroundPower


Flip-Chip: I/O Driver Row

Place rows for I/O driver cells.

These areas are used by placeAIO.

I/O Row


Flip-Chip: Route Feasibility

Inputs

�Aio_bga.cio # package binary

�Default.ldf # Lef/cml pointer

Outputs

�route_feasibility.cio # binary

�route_feasibility.rpt # report

�Highlight un-routable Bumps

CIOP package routing


Place: PlaceAIO

placeAIO places I/O driver in rows.

LEF OBS LAYER OVERLAP

� Restricts standard cell placement.

IO Driver

Bump

Overlap


Partition – Internal Pin for Better Routing

Blk1 Blk2

Bump is pushed into Blk2

Routing without internal pin Routing with internal pin


Partition Commands

� Move module inside floorplan view

� Double click on partition (attribute editor) – change size

� placeAIO and trialRoute

� Specify partition

� handlePtnAreaIo <buffer> # New TCL command

� commitPartition

� checkPinAssignment

� Change partition view


Partition – FeedThru Buffer

Partition

IO Driver output

Buffer

Partition

IO Cell

Bump input

IO output (internal pin)Inserted buffer

Standard cellBoundary Pin


Partition – Commit

Partition Placement Island


Partition – Block: Push Down Blockages

Bump Routing Blockage

P&R Blockages

Cell already in module


LEF 5.5 Syntax

BUMP

MACRO bumpcell

CLASS COVER BUMP ;

Pin PAD ; # no SITE required. Only one pin is allowed

Driver Cell

MACRO drivercell

CLASS PAD AREAIO ;

SITE IO ;

PIN IN ;

LEF Tile Macro # multiple pins – must be flattened

MACRO Tile1

CLASS COVER BUMP ;

* “BUMP” is a reserved word in LEF5.5


Flip-Chip Routing Support

� Supports both signal and power bump routing.

� fcroute is the new command that supports this feature.

� Routes signal bump cells to the I/O cell.

� Routes power bump cells to the nearby stripes.

� Routes bump pins in the cover macro to the I/O drivers for the signals.

� Routes power bumps in the cover macro to the stripe rails.


Flip-Chip Routing Support (continued)

Signal Routing

� Primary and secondary layer change control.

� An option to use the user-defined width to do the bump to IO driver connection.

� Supports Redistribution Layer (RDL) Routing. An RDL is a routing layer of conductive metal within an IC that connects the diepad or solder bump to a connection point on an I/O driver. The Encounter router supports routing to this special layer.

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