com bi national mos logic circuits
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Combinational MOS LogicCombinational MOS Logic
CircuitsCircuits
By:
May (CMOS Logic Circuits)
Joshua (Complex Logic Circuits)
Hernan (CMOS Transmission Gates)
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Generic combinational logic circuit (gate)
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
MOS Logic Circuits with Depletion nMOS Loads
a. Two-Input NOR Gate
VA VB Vout
low low high
low high low
high low low
high high lower
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Calculation of VOH
which will result to:
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-When VA and VB are lower than the VTH,driver, driver
transistors are turned off and ID,driver is zero.
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Calculation of VOL
a. VA = VOH and VB = VOL
b. VA = VOL and VB = VOH
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
The output low voltage level VOL in both cases (a) and (b) is
If (W/L)A = (W/L)B , then VOL for (a) and (b) are identical
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
c. VA = VOH and VB = VOH
since
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
The output voltage level is
Thus, to guarantee the required value of VOL in the worst case, the design choice
should yield two identical driver transistors by
a. assuming either VA or VB is logic-high and
b. setting
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Generalized NOR Structure with Multiple Inputs
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
The combined pull-down current can be expressed by
a. at linear
b. at saturation
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Assuming that the input voltages of all the driver transistors are
identical,
a. at linear
b. at saturation
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Equivalent inverter circuit corresponding to the n-input
NOR gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Transient Analysis of NOR Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Equivalent NOR Gate
where:
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
b. Two-Input NAND Gate
VA VB Vout
low low high
low high high
high low high
high high low
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
The NAND2 gate with both of its inputs al logic high level
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Thus,
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Assuming
and
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
If
then
To simplify, assume
Thus, the drain currents in the linear region are
and
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Since
then
Also, using
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Generalized NAND Structure with Multiple Inputs
Assuming the threshold voltages of all transistors are
equal
a. In linear region
b. At saturation
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Equivalent NAND Structure Gate
if
then
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
TransientAnalysis
Of NAND Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
If VB = VOH and VA switches from VOH to VOL ,the lumped output
capacitance is
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
CMOS LOGIC CIRCUITS
a. CMOS NOR2 (Two-Input NOR)Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Complementary nature operation
When either one or both inputs are high, p-net is cut-off , when the net
creates a conducting path between the output node and the ground
If both input voltages are low, the n-net is cut-off, the p-net creates a
conducting path between the output node and the supply voltage VDD
For any given input combination, the output is either grounded or
connected to VDD
Thus, Vout attains logic-low of VOL = 0 and logic-high voltage of VOH = VDD
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Design Considerations
Also,
If the devices are the same, then
Thus,(nMOS transistors are saturated, VGS=VDS )
Therefore,
(combined drain currents of nMOS transistors)
Finally,
(switching threshold voltage)
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
For Vin = Vout , M3 operates in the linear region while M4 in saturation,
thus
and
also
thus
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Combining the two threshold voltages yields the threshold voltage of
the CMOS inverter
Note:
To achieve a switching threshold voltage of VDD/2 for simultaneous switching,
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Other representation
And the switching threshold voltage is
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Parasiticdevice
capacitance
of the
CMOS
NOR2circuit
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
EquivalentCMOS
NOR2
circuit with
lumped
outputcapacitance
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
b. CMOS NAND2 (Two-Input NAND)Gate
With
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
LAYOUT OF SIMPLE CMOS LOGIC GATES
a. CMOS NOR2 Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
LAYOUT OF SIMPLE CMOS LOGIC GATES
b. CMOS NAND2 Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Stick Diagram
a. CMOS NOR2 Gate
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Stick Diagram
b. CMOS NAND2 Gate
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SAMPLE LAYOUTSAMPLE LAYOUT
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Combinational MOS Logic CircuitsCombinational MOS Logic Circuits
Thank You!
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