combinational circuit design: practice · 2011-09-11 · combinational circuit design: practice....
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![Page 1: Combinational Circuit Design: Practice · 2011-09-11 · Combinational Circuit Design: Practice. RTL Hardware Design by P. Chu Chapter 7 2 Outline 1. Derivation of efficient HDL description](https://reader034.vdocument.in/reader034/viewer/2022042309/5ed638e90c1f140c715b4646/html5/thumbnails/1.jpg)
RTL Hardware Design by P. Chu
Chapter 7 1
Combinational Circuit Design: Practice
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RTL Hardware Design by P. Chu
Chapter 7 2
Outline
1. Derivation of efficient HDL description2. Operator sharing3. Functionality sharing4. Layout-related circuits5. General circuits
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RTL Hardware Design by P. Chu
Chapter 7 3
1. Derivation of efficient HDL description
• Think “H”, not “L”, of HDL• Right way:
– Research to find an efficient design (“domain knowledge”)
– Develop VHDL code that accurately describes the design
• Wrong way:– Write a C program and covert it to HDL
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RTL Hardware Design by P. Chu
Chapter 7 4
Sharing
• Circuit complexity of VHDL operators varies
• Arith operators – Large implementation– Limited optimization by synthesis software
• “Optimization” can be achieved by “sharing” in RT level coding– Operator sharing– Functionality sharing
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RTL Hardware Design by P. Chu
Chapter 7 5
An example 0.55 um standard-cell CMOS implementation
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RTL Hardware Design by P. Chu
Chapter 7 6
2. Operator sharing
– “value expressions” in priority network and multiplexing network are mutually exclusively:
– Only one result is routed to output – Conditional sig assignment (if statement)
sig_name <= value_expr_1 when boolean_expr_1 elsevalue_expr_2 when boolean_expr_2 elsevalue_expr_3 when boolean_expr_3 else. . .value_expr_n;
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RTL Hardware Design by P. Chu
Chapter 7 7
– Selected sig assignment (case statement)with select_expression select
sig_name <= value_expr_1 when choice_1,value_expr_2 when choice_2,value_expr_3 when choice_3,. . .value_expr_n when choice_n;
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RTL Hardware Design by P. Chu
Chapter 7 8
Example 1
• Original code:r <= a+b when boolean_exp else
a+c;
• Revised code:src0 <= b when boolean_exp else
c;r <= a + src0;
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RTL Hardware Design by P. Chu
Chapter 7 9
Area: 2 adders, 1 muxDelay:
Area: 1 adder, 1 muxDelay:
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RTL Hardware Design by P. Chu
Chapter 7 10
Example 2• Original code:
process(a,b,c,d,...)begin
if boolean_exp_1 thenr <= a+b;
elsif boolean_exp_2 thenr <= a+c;
elser <= d+1;
end ifend process;
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RTL Hardware Design by P. Chu
Chapter 7 11
• Revised code:process(a,b,c,d,...)begin
if boolean_exp_1 thensrc0 <= a;src1 <= b;
elsif boolean_exp_2 thensrc0 <= a;src1 <= c;
elsesrc0 <= d;src1 <= "00000001";
end if;end process;r <= src0 + src1;
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RTL Hardware Design by P. Chu
Chapter 7 12
Area:2 adders, 1 inc, 2 mux
Area: 1 adder, 4 mux
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RTL Hardware Design by P. Chu
Chapter 7 13
Example 3• Original code:
with sel selectr <= a+b when "00",
a+c when "01",d+1 when others;
• Revised code:with sel_exp select
src0 <= a when "00"|"01",d when others;
with sel_exp selectsrc1 <= b when "00",
c when "01","00000001" when others;
r <= src0 + src1;
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RTL Hardware Design by P. Chu
Chapter 7 14
Area:2 adders, 1 inc, 1 mux
Area: 1 adder, 2 mux
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RTL Hardware Design by P. Chu
Chapter 7 15
Example 4• Original code:
process(a,b,c,d,...)begin
if boolean_exp thenx <= a + b;y <= (others=>'0');
elsex <= (others=>'1');y <= c + d;
end if;end process;
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RTL Hardware Design by P. Chu
Chapter 7 16
Area:2 adders, 2 mux
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RTL Hardware Design by P. Chu
Chapter 7 17
• Revised code:begin
if boolean_exp thensrc0 <= a;src1 <= b;x <= sum;y <= (others=>'0');
elsesrc0 <= c;src1 <= d;x <= (others=>'1');y <= sum;
end if;end process;sum <= src0 + src1;
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RTL Hardware Design by P. Chu
Chapter 7 18
• Area: 1 adder, 4 mux• Is the sharing worthwhile?
– 1 adder vs 2 mux– It depends . . .
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RTL Hardware Design by P. Chu
Chapter 7 19
Summary
• Sharing is done by additional routing circuit
• Merit of sharing depends on the complexity of the operator and the routing circuit
• Ideally, synthesis software should do this
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RTL Hardware Design by P. Chu
Chapter 7 20
3. Functionality sharing
– A large circuit involves lots of functions– Several functions may be related and have
common characteristics– Several functions can share the same circuit.– Done in an “ad hoc” basis, based on the
understanding and insight of the designer (i.e., “domain knowledge”)
– Difficult for software it since it does not know the “meaning” of functions
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RTL Hardware Design by P. Chu
Chapter 7 21
e.g., add-sub circuit
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RTL Hardware Design by P. Chu
Chapter 7 22
• Observation: a – b can be done by a + b’ + 1
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RTL Hardware Design by P. Chu
Chapter 7 23
• Manual injection of carry-in:• Append an additional bit in right (LSB):
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RTL Hardware Design by P. Chu
Chapter 7 24
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RTL Hardware Design by P. Chu
Chapter 7 25
e.g., sign-unsigned comparator
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RTL Hardware Design by P. Chu
Chapter 7 26
Binary wheel
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RTL Hardware Design by P. Chu
Chapter 7 27
• Observation:– Unsigned: normal comparator– Signed:
• Different sign bit: positive number is larger• Same sign: compare remaining 3 LSBs
This works for negative number, too!E.g., 1111 (-1), 1100 (-4), 1001(-7)
111 > 100 > 001– The comparison of 3 LSBs can be shared
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RTL Hardware Design by P. Chu
Chapter 7 28
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RTL Hardware Design by P. Chu
Chapter 7 29
e.g., Full comparator
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RTL Hardware Design by P. Chu
Chapter 7 30
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RTL Hardware Design by P. Chu
Chapter 7 31
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RTL Hardware Design by P. Chu
Chapter 7 32
• Read 7.3.3 and 7.3.5
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RTL Hardware Design by P. Chu
Chapter 7 33
4. Layout-related circuits
– After synthesis, placement and routing will derive the actual physical layout of a digital circuit on a silicon chip.
– VHDL cannot specify the exact layout– VHDL can outline the general “shape”
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RTL Hardware Design by P. Chu
Chapter 7 34
– Silicon chip is a “square” – “Two-dimensional” shape (tree or rectangular) is
better than one-dimensional shape (cascading-chain)
– Conditional signal assignment/if statement form a single “horizontal” cascading chain
– Selected signal assignment/case statement form a large “vertical” mux
– Neither is ideal
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RTL Hardware Design by P. Chu
Chapter 7 35
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RTL Hardware Design by P. Chu
Chapter 7 36
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RTL Hardware Design by P. Chu
Chapter 7 37
e.g., Reduced-xor circuit
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RTL Hardware Design by P. Chu
Chapter 7 38
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RTL Hardware Design by P. Chu
Chapter 7 39
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RTL Hardware Design by P. Chu
Chapter 7 40
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RTL Hardware Design by P. Chu
Chapter 7 41
• Comparison of n-input reduced xor – Cascading chain :
• Area: (n-1) xor gates• Delay: (n-1)• Coding: easy to modify (scale)
– Tree:• Area: (n-1) xor gates• Delay: log2n• Coding: not so easy to modify
– Software should able to do the conversion automatically
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RTL Hardware Design by P. Chu
Chapter 7 42
e.g., Reduced-xor-vector circuit
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RTL Hardware Design by P. Chu
Chapter 7 43
• Direct implementation
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RTL Hardware Design by P. Chu
Chapter 7 44
• Functionality Sharing
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RTL Hardware Design by P. Chu
Chapter 7 45
• Direct tree implementation
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RTL Hardware Design by P. Chu
Chapter 7 46
• “Parallel-prefix” implementation
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RTL Hardware Design by P. Chu
Chapter 7 47
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RTL Hardware Design by P. Chu
Chapter 7 48
• Comparison of n-input reduced-xor-vector – Cascading chain
• Area: (n-1) xor gates• Delay: (n-1)• Coding: easy to modify (scale)
– Multiple trees• Area: O(n2) xor gates• Delay: log2n• Coding: not so easy to modify
– Parallel-prefix• Area: O(nlog2n) xor gates• Delay: log2n• Coding: difficult to modify
– Software is not able to convert cascading chain to parallel-prefix
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RTL Hardware Design by P. Chu
Chapter 7 49
e.g., Shifter (rotating right)• Direct implementation
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RTL Hardware Design by P. Chu
Chapter 7 50
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RTL Hardware Design by P. Chu
Chapter 7 51
• Better implementation
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RTL Hardware Design by P. Chu
Chapter 7 52
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RTL Hardware Design by P. Chu
Chapter 7 53
• Comparison for n-bit shifter– Direct implementation
• n n-to-1 mux• vertical strip with O(n2) input wiring• Code not so easy to modify
– Staged implementation• n*log2n 2-to-1 mux• Rectangular shaped• Code easier to modify
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RTL Hardware Design by P. Chu
Chapter 7 54
5. General examples
– Gray code counter– Signed addition with status– Simple combinational multiplier
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RTL Hardware Design by P. Chu
Chapter 7 55
e.g., Gray code counter
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RTL Hardware Design by P. Chu
Chapter 7 56
• Direct implementation
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• Observation– Require 2n rows– No simple algorithm for gray code increment– One possible method
• Gray to binary• Increment the binary number• Binary to gray
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• binary to gray
• gray to binary
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e.g., signed addition with status• Adder with
– Carry-in: need an extra bit (LSB)– Carry-out: need an extra bit (MSB)– Overflow:
• two operands has the same sign but the sum has a different sign
– Zero– Sign (of the addition result)
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e.g., simple combinational multiplier
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