combinational cmos
TRANSCRIPT
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Combinational CMOS
Only one of the network is conducting at any given
time (except during switching)
VDD
F(In1,In2,InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS only
NMOS only
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Strong 0's and 1's
Strong 0
VDD 0
CLVDD
S
D
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Strong 0's and 1's
Weak 1
0 VDD - VTn
CL
VDD
VDD
S
D
VGS
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Strong 0's and 1's
Weak 0
VDD |VTp|
CLS
D
VGS
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Strong 0's and 1's
NMOS cannot propagate strong 1's
PMOS cannot propagate strong 0's
PDN
PUN
Threshold drop
VDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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Strong 0's and 1's
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Logic Rules
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Complex Functions
Complex (active low) function can be achieved with just
one PDN and one PUN
OUT = D + A (B + C)
D
A
B C
D
A
B
C
PUN and PDN are dual networks
CMOS is naturally inverting
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Voltage Transfer Characteristic
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Voltage Transfer Characteristic
Case 1: (blue)
both A & B change from 0 to 1 simultaneously
Has the biggest noise margin
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Voltage Transfer Characteristic
Case 2: (Green)
Hold A at 1, change B from 0 to 1
Only one PMOS is conducting, therefore PDN is stronger
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Voltage Transfer Characteristic
Conclusion: Noise margins are input pattern dependent
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Propagation Delay
Case 1
A: 1 0, B: 1 0
Pull-up path delay
0.69 x Rp/2 x C
L
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Propagation Delay
Case 2
A: 1 1, B: 1 0
Pull-up path delay
0.69 x Rp
x CL
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Propagation Delay
Case 3
A: 0 1, B: 0 1
Pull-down path delay
0.69 x 2RN
x CL
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Propagation Delay
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CMOS Problem: Large Fan-in
As the fan-in grows thepropagation delay deteriorates
rapidly
1.Many PMOS transistors in a NANDgate PUN will add up to a large
total capacitance
2.The series connection will get
longer longer path delay
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Dealing with Large Fan-in
1) Increase the sizes of all transistors
Consequence: a decrease in resistance, but an
increase in capacitance
Only effective when dealing with large fan-out loads
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Dealing with Large Fan-in
4) Logic Restructuring
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Power Consumption
Two types
Dynamic: dominant
Static: negligible but significant in < 65nm
Physics reminder
P = V . I = dE/ dt
E = V.i(t).dt = V C.(dV/dt).dt = CV dV = CV2
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Dynamic Power Consumption
Occurs only when output switches
Two causes
a) Charging and discharging of capacitances
b) Direct path current
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Dynamic Power Consumption
Charging and discharging of capacitances
E = CLV
DD2
P = CLVDD2f
Famous equation for describing
dynamic power dissipation
With switching probability ():P = C
LV
DD2f
(0
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Static Power Consumption
Power dissipation in steady state
Due to leakage current in reverse bias diodes
inside the transistor
Pstatic
= Istatic
VDD
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Dynamic Power Consumption
How to decrease power dissipation?
Pdyn = CLVDD2f
Totol Power Consumption: Pdynamic + Pstatic
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Pseudo NMOS
Used for high fan-ingates
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P T i t L i
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Pass Transistor Logic
Very fast
Suffers from threshold drops
T i i G t
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Transmission Gates
Connect source and drain of PMOS and NMOS
Let the NMOS take care of propagating the 0, PMOS the 1.
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T i i G t
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Transmission Gates
This circuit still would not work. Why?
XOR Gate
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(8 transistors)
Another XOR Gate
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(6 transistors)
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4 to 1 Multiplexer
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4-to-1 Multiplexer
Transmission Gate
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Transmission Gate
Suffers from relatively high resistance andpropagation delay when placed in series
Use sparingly
Glitching
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Glitching
Causes excessive power consumption
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