combined lumped and continuum parameter design...

ASME 2016 International Design Engineering Technical Conferences andComputers and Information in Engineering Conference

IDETC2016August 21–24, 2016, Charlotte, North Carolina

IDETC2016-60218

COMBINED LUMPED AND CONTINUUM PARAMETER DESIGN OPTIMIZATION OFELECTRO-THERMAL SYSTEMS

Danny J. LohanJames T. Allison

Engineering System Design LaboratoryDepartment of Systems and Entrepreneurial Engineering

University of Illinois, Urbana, IL 61801Email: [dlohan2, jtalliso] @illinois.edu

Ercan M. DedeMasanori Ishigaki

Electronics Research DepartmentToyota Research Institute of North America

Ann Arbor, MI, 48105Email: [eric.dede, masanori.ishigaki]@toyota.com

ABSTRACTIn this article we explore a coupled design strategy for the

simultaneous optimization of lumped-parameter (electrical) andcontinuum parameter (thermal) systems. In terms of electricalcircuit response, advances in the development of wide band-gapsemiconductors and the high speed transient behavior of thesedevices leads to challenges associated with damping or over-shoot. To address such issues, traditional circuit design strate-gies should evolve to incorporate next generation electrical com-ponents effectively. Thus, we propose the incorporated designof circuit layout and routing in conjunction with heat spreaderdesign as a more comprehensive means to optimize the layoutof power-dense electronics. The effects of this multidisciplinarydesign are evaluated by analyzing the Pareto set, which was ob-served to shift towards the utopia point with each additional de-sign consideration.

1 INTRODUCTIONTo address the emergence of wide band-gap semiconductor

devices, we propose a coupled design strategy for a lumped pa-rameter electrical circuit model and a continuum thermal model.This is achieved by simultaneously designing a heat spreaderwith circuit layout to capture the design coupling between thetwo systems and improve overall performance. In optimizing theperformance of the circuit, four distinct design considerationsare taken into account: circuit component placement, the routing

of the electrical trace connecting these components, trace shape,and heat spreader topology. These design considerations influ-ence three dependent properties: self-inductance, resistance, andtemperature. These properties are then used to evaluate three cir-cuit performance metrics: current overshoot, direct current (DC)loss, and maximum temperature (Fig. 1). Design coupling isdue to Joule heating, which is resistive heating that arises fromelectrical current. Flow of electrical current influences heatingand temperature, but temperature influences electrical resistance,which in turn impacts electrical current.

The detrimental effects of heat on circuit performance arewell-known and researchers have used co-simulation techniqueson a discretized domain to evaluate these effects. Ren et al. used

Trace Layout

Trace Shape

Component Placement

Design Variables

DependentVariables

Metrics

Circu

it L

ayou

tLu

mped

Sys

tem

Temperature

Topology

Continuum System

MaxTemperatureDC LossOvershoot

Inductance Resistance

~

FIGURE 1. Circuit design relationships.

1 Copyright c© 2016 by ASME

the finite volume method to evaluate the voltage drop and temper-ature on the domain [1]. Liu et al. used co-simulation to evaluatehow heating affects the maximum current that can pass througha wire [2]. Lu and Jin used the Finite Element Tearing and In-terconnection method to decrease the computational burden forsimulation by decomposing the finite element model and solv-ing spatial domains in parallel [3, 4]. As a step towards mitigat-ing thermal effects, Xie and Swaminathan designed the use ofthrough-silicon vias as a tool for improved heat dissipation [5].Additionally, Dede et al. investigated the use of topology opti-mization to design electro-thermal circuit trace shielding zonesto protect temperature sensitive components [6]. In this work,a co-simulation strategy is used to enforce consistency betweena lumped parameter circuit and distributed parameter heated do-main. In using this technique, design variables are properly up-dated to shift towards a system-level optimal solution using bothcircuit layout and topology optimization.

In optimizing the circuit layout two distinct considerationsare taken into account, the first of which is the placement ofcircuit components. This type of layout optimization problemhas been explored by several researchers for different scale prob-lems. Considering a small scale problem, Shook et al. [7] used alumped thermal system model to predict thermal characteristicson the domain when optimizing the placement of power modules.Hammadi et al. [8] coupled several commercial finite elementpackages using iSIGHT in the layout optimization of power mod-ules. Transitioning to large-scale problems is difficult, in partic-ular because of the increased number of constraints. Screeningmethods have been developed to assist engineers in designinga circuit [9, 10], however the task still relies on the engineer tomake design decisions. The methods presented here are for smallcircuit applications, but may be scaled to larger circuits.

The second circuit layout design consideration addressedhere is the routing of the conductive trace that connects compo-nents. Traditional methods for solving the circuit routing prob-lem rely on a ground structure of nodes and shortest path al-gorithms to determine the minimum wiring required to connectcomponents together. For large scale circuits, escape routingstrategies have been developed to minimize wiring length [11–14]. For smaller circuit problems, inter-component connectionsare designed using various heuristic-based approaches [15–17].In the application presented here, inter-component routing isconsidered with spline representations for the wires. This param-eterization of the wire trace allows for design freedom in mod-ifying the geometrically dependent circuit dynamics, resistance,and inductance.

As a final design consideration, a heat spreader will be de-signed in conjunction with the circuit using topology optimiza-tion approaches. Topology optimization strategies have beenwell-studied across several domains since the seminal paper waspublished by Bendsoe and Kikuchi [18]. Several researchershave adapted this technique for various applications of heat trans-

fer. When considering steady-state heat conduction for a homo-geneously heated domain [19–23], optimal passive heat spread-ers resembled branching structures. This tendency is also ob-served when designing three-dimensional heat spreaders andcold plates [24–26]. In this study, topology optimization tech-niques are applied to a domain consisting of discrete heat sourceswhere the structure of the optimal heat spreader is unknown.

To assess the effect of each design consideration, multi-objective optimization studies are conducted to develop Paretosets [27] that are used as targets for the investigation of sin-gle level coordination strategies to design these discrete sys-tems [28].

The organization of the paper follows. The next section de-scribes model development and design parameterization for theelectrical circuit. A multi-objective study is then presented to de-velop a benchmark to test the simultaneous electro-thermal de-sign strategy. Topology optimization is then presented and incor-porated as a design strategy. The following section presents re-sults when using multi-disciplinary optimization (MDO) strate-gies to coordinate the design of these coupled but distinct sys-tems. This article then concludes with a discussion of results andfuture work.

2 Electrical Circuit AnalysisTo demonstrate the capability of this design methodology,

a case study is selected based on a printed circuit board proto-type described in Ref. [29]. Of particular interest is the inter-face between the main heat generating and electrically sensitivecomponents, the gallium nitride field-effect transistor (GaN FET)switches. The buck converter prototype may be simplified by thegraphical procedure illustrated in Fig. 2.

The lumped resistance, R, is a function of the length of eachwire trace section and the internal resistance of the switches. Itis modeled using the following equation:

R = ρl

Ae, (1)

s1 s2

c

+

-

R

C

L

s1 s2

c

+ -

ContinuumModel

ParameterExtraction

LumpedModel

FIGURE 2. Lumped parameter model extraction for RLC equivalentcircuit. Note that the dashed orange, blue, green, and red lines representthe equivalent capacitance, inductance, voltage source, and resistance,respectively.


where ρ is the electrical resistivity of the conductor, l is thelength of a trace section, and Ae is the effective cross sectionalarea in which current travels. Both DC current and alternatingcurrent (AC) characteristics are observed in the operation of thebuck converter. To capture this, two different definitions of Aewill be used based on the mode of operation. While DC currentuses the entire wire cross section, AC current migrates to the wiresurface. The depth from the surface at which a majority of theAC current flows is called the ‘skin depth’, δ , which is definedas:

δ =

√2ρ

ωµ

√√1+(ρωε)2 +ρωε. (2)

The skin depth depends on AC frequency, ω , permitivity of themetal trace, ε , and magnetic permeability, µ .

The lumped inductance, L, is computed based on trace lay-out. Specifically, the self inductance of the wire loop that resultswhen connecting the components together is calculated. Theself-inductance of an arbitrarily shaped wire loop may be ap-proximated by the following equation [30]:

L =µ0

4π

(∮ dx ·dx′

|x−x′|

)|s−s′|>w/2

+µ0

4πlY +H.O.T., (3)

where the self-inductance, L, is given by the boundary integralof one over the norm of each finite segment, s, with respect toevery other finite segment, s′. The second term captures the con-tribution of the skin effect as a function of wire length, l, and skindepth parameter, Y . Given that the inductance must be calculatedby a discretized representation of the wire loop, the accuracy ofthe equation depends on the wire trace width, w. The error of thisinductance model tends to zero as w decreases.

The lumped capacitance is derived from the capacitance ofthe switches, which can be obtained from vendor component datasheets. These simplified models are used to quickly extract thelumped parameters for the circuit and capture the characteristicsof a design. Future studies include higher fidelity finite elementanalysis to increase the accuracy of solutions.

Overshoot and loss metrics for the circuit are calculatedbased on the following transfer function expressed in the Laplacedomain:

Vc(s)V (s)

=1

LC

s2 + RL s+ 1

LC

, (4)

This transfer function compares the output voltage across aswitch to the input voltage. Performing analysis in the Laplace

0 5 10 15 20 250

0.5

1

1.5

O

Time (s)

Nor

mal

ized

Am

plitu

de

PL

FIGURE 3. Sample second order signal, where overshoot, O, is mea-sured from steady-state value to peak, and DC loss, PL, is quantified asthe sum of the area under the DC signal.

domain supports simple analytical calculation of electrical re-sponse metrics. A sample second order response is presentedin Fig. 3.

A second order transfer function can be represented usingthe following general form:

G(s) =ω2

n

s2 +ζ ωns+ω2n, (5)

where ωn is the natural frequency of the system and ζ is thedamping coefficient. From the general form, closed form solu-tions for quantities of interest (Table 1) can be derived as a meansto reduce optimization computational cost.

TABLE 1. Metrics for evaluating system performance.

Name Variable Expression

Overshoot O e−πζ/√

1−ζ 2

DC Loss PL I2RMSRDC

For a second order system, the overshoot of the system canbe found in terms of the damping ratio, ζ . Comparing the struc-ture of the derived transfer function to the general form, ζ is:

ζ =RAC√

C2√

L, (6)

where RAC is the AC circuit resistance. The DC loss of the systemis a function of the root-mean-square current, IRMS, and DC re-sistance, as loss more closely resembles a steady-state response.These objectives are used in quantifying circuit performance andobtaining a Pareto set. To develop a Pareto front, the following


optimization problem can be solved varying the parameter, α ,from 0 to 1.

Obj = αPL +(1−α)O (7)

When optimizing the system, varying α produces various typesof structures. This weighted-sum strategy for multi-objectiveoptimization does have some disadvantages, including inabil-ity to resolve non-convex portions of Pareto fronts. The multi-objective optimization studies presented in this article were per-formed instead using the MATLAB R© multi-objective genetic al-gorithm (MOGA) tool, gamultiobj. In addition to provid-ing an effective means for identifying points in the Pareto set,gamultiobj also improves the probability of finding globally-optimal solutions.

2.1 Co-simulation StrategyTo evaluate the performance of the system properly with

respect to heating considerations, a co-simulation strategy wasused. Both the lumped and distributed parameter models aresolved iteratively (fixed-point iteration [28]) to achieve agree-ment in thermal response. The power loss of each switch andsection of trace wire is distributed equally to each representativeelement in the continuum model. This is used as a load inputfor the finite element analysis used to solve for the temperatureresponse on the domain. The mean temperature of the elementsfor each switch and trace wire is returned to the lumped circuitmodel for re-evaluation. The convergence criterion for this itera-tive analysis is:

mean(T (i)−T (i−1))2 ≤ ξ

where: T (i) = [Ts1(i),Ts2(i),Tt1(i),Tt2(i),Tt3(i)].(8)

The co-simulation technique is repeated between the lumpedparameter and continuum model until the square of the meanchange in temperatures is less than a specified tolerance, ξ . InEqn. (8), T (i) is a vector consisting of the mean temperature ofeach switch and section of trace wire at iteration, i. This guaran-tees that the temperature of each discrete object converges withinthe tolerance, ξ . The co-simulation analysis is shared between alloptimization routines to ensure accurate evaluation.

2.2 Circuit Layout DesignThe circuit layout here is defined by the location of each

component and the routing of the trace connecting the compo-nents. When these geometric properties are modified, the lumpedparameters of the circuit are updated. In this design problem, sys-tem architecture is fixed (the set of components and connections

Control Points Axis of Symmetry

Placement ZonesRw

Rh

FIGURE 4. Circuit layout parameterization using optimized deviceposition and trace spline control point design variables.

does not change). The two switches are placed at the upper ver-tices of a rectangle and the capacitor is placed in the center of thelower length as shown in Fig. 4.

Early experimentation revealed the symmetric tendencies ofoptimal designs. Enforcing symmetry via design representationreduces the component placement design description dimensionto two design variables, as illustrated by Rv and Rw in Fig. 4. Thetrace wires that connect each pair of components are parameter-ized by vertices, referred to as control points. A spline that rep-resents trace wire routing path is fit from one component throughits control points to the paired component. The control points arerestricted to separate zones to ensure the trace remains within aboundary which prevents overlap. The number of control pointsthat represent a spline can be changed to vary available splinegeometry complexity and allow access to other sections of thedesign domain. The design vector, xE , for the electrical systemis:

xE = [Rw, Rh, c1x, c1y, c2x, c2y, ..., cnx, cny] , (9)

where component locations are specified by Rw and Rh, and thetrace geometry is specified by the x and y coordinates of the ncontrol points c.

Based on these design considerations, a multi-objective opti-mization study can be performed to develop an initial Pareto set.The results of this study when using different spline resolutionsare presented in Fig. 5.

The ideal design performance for a multi-objective designoptimization study is the utopia point, a (normally unattainable)design that achieves the best possible values for all objectivefunctions simultaneously based on the best values obtained ifeach objective function was optimized individually (i.e., the an-chor points). In realistic multi-objective problems the utopiapoint is unattainable because the objectives conflict. Paretofronts quantify the tradeoffs between conflicting objective func-


Normalized Overshoot0 0.25 0.5 0.75 1

Nor

mal

ized

DC

Los

s

0

0.25

0.5

0.75

1

1 CPPS2 CPPS3 CPPSUtopia Point

FIGURE 5. Pareto front of optimal circuit designs for three distinctspline resolutions.

tions. Shifting to better design strategies or technologies oftencan shift the entire Pareto front closer to the utopia point (a de-sirable result).

The multi-objective optimization study was repeated forthree different spline resolutions, with 1-3 control points perspline (CPPS). Increasing the available complexity of the splinemakes possible the shifting of the Pareto front closer to the utopiapoint. For this particular problem, Pareto front shifts are possi-ble because lower CPPS values cannot access higher-performingdesign geometries. The 2 CCPS spline representation providesreasonable design space coverage, so it was chosen as the basisfor subsequent studies. When analyzing Fig. 5, it can be seenthat the chosen objectives, overshoot and DC loss, are compet-ing objectives. Increasing one objective function will degrade theother. Improving both simultaneously (i.e., a Pareto front shift)can be realized by exploring design changes beyond componentlocation and trace routing.

2.3 Trace Shape DesignIn addition to component placement and trace routing,

changes to trace shape design were considered as well. Whentraveling through a wire, a majority of the electrons in alternat-ing current travel at the surface of the wire. This results in adifference between AC and DC resistance values. Since AC re-sistance has significant dynamic effects on damping, designingthe trace shape to optimize these effects is desirable. Considerthe parameterization presented in Fig. 6 where the trace can haverectangular protuberances extending from the trace path.

Given a bounded design domain, or path of trace wire, the

l

w

PD

a

Current Flow

d

FIGURE 6. Circuit trace parameterization where DC current flowsthrough the middle rectangle and AC current flows along the blue path.

gap between AC and DC resistance can be modeled in a simpli-fied way by comparing perimeter and area. DC current travelsthrough the smallest uniform cross section of the wire which isthus used to calculate DC resistance:

RDC = ρl

w−2a. (10)

The effective area of the cross section is the difference be-tween the wire width w and total lateral size of the square fea-tures, 2a. Since AC current only travels through the surface of thewire, designs that increase the path length of AC current travelwill increase AC resistance. This can be approximated by thefollowing equation:

RAC = ρl +2na

2δ, (11)

where the number of square features, n, is chosen to be largeenough to maintain the surface current effect of AC current. Ifthe number of square features along the spline is held fixed atthe maximum allowable number, this creates a one dimensionalproblem that can be solved in terms of feature height, a, toachieve a desired damping increase. The rate of increase of ACand DC resistance while varying a is visualized in Fig. 7.

This chart may be used to select the maximum amount ofAC resistance that can be achieved for a given increase in DCresistance. For small changes in DC resistance, large changesin AC resistance can be obtained. As a demonstration of theconcept, a minimum DC loss design was obtained and is shownin Fig. 8. The trace paths connect components with minimumpath length for the two control point parameterization, and squarefeatures are added to the trace wire to tune AC resistance.

We would like to use trace shape design as a mechanismto help shift the Pareto front. Specifically, maximizing the gap


a [%W]0 0.1 0.2 0.3 0.4 0.5

Res

ista

nce

Incr

ease

[%10

0]

0

10

20

30

40

50

AC - DCDCAC

FIGURE 7. Trace design resistance comparison.

1

1

2

2

A A

B B

FIGURE 8. Circuit trace shape design with square features to increaseAC resistance.

between AC and DC resistance should help accomplish this byallowing for the best possible damping effect. Repeating thisstudy with the extended design flexibility of trace shape designdid in fact result in a Pareto front shift as shown in Fig. 9.

When including trace shape design, optimal designs are ob-served that perform worse in DC loss. However, designs thatperform better in overshoot are also observed. This is due tothe increase in AC and DC resistance accessible through wiretrace shape adjustments. To address the increase in DC loss, heatspreader design will now be considered in addition to the circuitlayout and trace shape optimization.

3 Heat Spreader DesignTo augment the circuit design problem that addresses elec-

trical system performance, the design of a heat spreader will beconsidered to help improve thermal performance. The circuitdesign problem is formulated using a lumped parameter model,and the heat spreader design problem is formulated using a dis-tributed parameter (continuum system) model. It will be shown

Normalized Overshoot0 0.25 0.5 0.75 1

Nor

mal

ized

DC

Los

s

0

0.25

0.5

0.75

1

Circuit LayoutCircuit Layout + ShapeUtopia Point

FIGURE 9. Pareto fronts of optimal circuit designs with and withouttrace shape design. Adding trace shape design results in overall perfor-mance improvement.

W

GD

GN

f1

f2

FIGURE 10. Circuit continuum representation for heat spreader de-sign.

that incorporating electrical and thermal systems together intoa single simultaneous design optimization problem further im-proves system performance. The heat spreader will be placedwithin a multi-layer printed circuit board. To understand heatspreader design, consider the diagram in Fig. 10 that depicts theheat conduction aspects of a sample circuit.

The power loss of the circuit is realized as component andJoule heat, f1 and f2, respectively (Eqn. (12) below). This heat istransferred to the heat spreader, which is modeled as a continuum


system. Here we assume that the entire domain boundary ΓN isadiabatic. In the present problem there are several sinks presenton the design domain ΓD. The general goal of heat spreader de-sign is to extract as much heat as possible from the domain toensure the integrity of the electronic components. As a meansof designing the heat spreader efficiently (i.e., maximum thermalperformance for a given amount of material), a topology opti-mization strategy is implemented.

∇ · (k(γ)∇T )+ f1 + f2 = 0 on Ω, (12)T = 0 on ΓD, (13)

(k∇T ) ·n = 0 on ΓN , (14)

3.1 Topology OptimizationContinuum topology optimization determines the optimal

allocation of material on a design domain. This is done by dis-cretizing the design domain into finite elements and assigninga material density, 0 ≤ γi ≤ 1, to each finite element. A com-mon type of objective function used in topology optimizationproblems is a compliance metric. Thermal compliance is as-sociated with the degree of heat extraction, and the widespreaduse of this objective is due to its simple and inexpensive gradi-ent calculation. An exploration of heat spreader design problemformulations for printed circuit board applications was recentlyconducted by the authors [31]. For the purpose of the studieshere, the maximum temperature was chosen as an objective. Thisaligns well with the power loss objective and promotes a circuitboard with desirable low temperatures. Direct consideration ofelectrical performance in topology optimization is a topic forfuture work, possibly utilizing generative design strategies thatsupport more general formulations [23].

The topology optimization problem considered here is:

min.xT

max(T ) (15)

s. t. V (xT ) =Vp (16)R(xT )≥ Rmin, (17)

where xT = [γ1,γ2, . . . ,γnE ]T is the thermal system design vector

and nE is the number of elements in the design domain.A fixed volume constraint, V (xT ) = Vp, must be satisfied,

and a manufacturing constraint ensuring a minimum member ra-dius, Rmin, is observed. To solve this problem the Solid IsotropicMicrostructure with Penalization (SIMP) method is used. TheSIMP method uses continuous density variables for each cell.This enables use of efficient gradient-based optimization meth-ods, but presents the challenge of cells with intermediate density.SIMP addresses this by penalizing elements away from interme-diate density values, resulting in cells that are approximately void(γi ≈ 0) or full density (γi ≈ 1) [19]. In this problem 0 representsan element with non-conductive material (FR-4) and 1 represents

an element with conductive material (copper). When optimiz-ing the heat spreader design for a given circuit with various vol-ume constraints, different structures can be observed as shown inFig. 11.

Volume Fractions5% 20% 40%

Copper FR-4 Copper FR-4 Copper FR-4

0 0.2 0.4 0 0.1 0 0.1

FIGURE 11. Heat spreader designs (top). Dark regions indicate solidconductive material and light regions indicate void. Normalized temper-ature maps (bottom). Red regions are hot and blue regions are cool.

By varying Vp we can identify the minimum conductive ma-terial volume fraction that provides acceptable heat extraction.Figure 12 shows how maximum domain temperature varies withvolume fraction for a fixed circuit design. Though this maynot hold for all circuit layout designs, it is clear that beyondVp = 20%, further increase in volume fraction does not reducemaximum domain temperature significantly for this design.

To use SIMP with the multi-objective genetic algorithmavailable in MATLAB R©, a nested formulation is used. For eachcandidate circuit design tested by the outer loop, the optimal heatspreader design is found using SIMP. The resulting Pareto frontis compared to previous results in Fig. 13

Once again, adding a new design consideration (heatspreader design here) shifts the Pareto set closer to the utopiapoint. The use of a heat spreader reduces circuit losses sincetemperature influences DC resistance. Though DC loss appears


0 20 40 60 80 100

Material Volume Fraction (%)

0

0.2

0.4

0.6

0.8

1N

oram

ilize

d M

axim

um T

empe

ratu

re

FIGURE 12. Maximum temperature vs volume fraction.

0 0.25 0.5 0.75 1

Normalized Overshoot

0

0.25

0.5

0.75

1

Nor

mal

ized

DC

Los

s

Circuit LayoutCircuit Layout + ShapeCircuit Layout + Shape + TopologyUtopia Point

FIGURE 13. Pareto front of optimal circuit designs when using 3 setsof design considerations.

to improve, overshoot remains largely the same.

4 Pareto Set RefinementWhile genetic algorithms (GAs) improve efforts to identify

global optima, and can generate Pareto sets through a single al-gorithm execution, GA solutions cannot be proven to be optimal.In addition, solution precision is often low. Identifying one ormore anchor points using gradient-based algorithms may helpimprove confidence in MOGA results if these points are con-sistent with the MOGA-generated Pareto fronts. In this sectionwe present results from using gradient based optimization tech-niques to identify minimal DC loss designs (lower right anchorpoint in the Pareto sets here). Two different coordination strate-gies were used: nested and simultaneous.

The nested design strategy was described above, but used

Optimizer

Co-Simulation

ThermalSub-optimizer

Sub-optimizerxE,xT yE,yT

xT yT

xE,xT yE,yT xE,xT yE,yT

(a) Nested formulation

Optimizer

Co-Simulation

x yx y

(b) Simultaneous formulation

FIGURE 14. Candidate solution methods for the combined circuitand heat spreader design problem.

MOGA for the outer-loop solution. Here a gradient-basedmethod is used for both inner and outer loops. For each candidateelectrical system design, the optimal heat spreader will be foundand used in evaluation. The information flow of this procedure isillustrated in Fig. 14(a). Though this strategy guarantees a feasi-ble design at each iteration, it requires many function evaluationsfor convergence. In implementing this strategy, the MATLAB R©

function fmincon is used to update the circuit design param-eters, and the method of moving asymptotes (MMA) is used asthe SIMP solver to converge quickly on a heat spreader designfor each candidate circuit layout.

The simultaneous strategy solves a single optimization prob-lem for both sets of design variables concurrently. When usingsimultaneous optimization, feasibility with respect to design con-straints is not guaranteed until optimization convergence. Boththe circuit and heat spreader design variables are optimized usingthe MATLAB R© function fmincon. The gradients for the circuitdesign problem are calculated using forward finite differencingas defined by the following formula:

∆PL =PL(x+h)−PL(x)

h, (18)

where the change in the loss for a circuit layout is measured oncefor each small perturbation h. Gradients for the heat spreaderare calculated using analytical sensitivity analysis [32]. To im-prove the convergence characteristics of this problem, the gra-dients of the circuit layout are scaled adaptively to match theorder of the topology optimization problem. The simultaneousstrategy requires that multidisciplinary analysis is performed via


co-simulation.To test the effectiveness of each strategy, numerical experi-

ments were conducted to achieve the minimum loss designs. Amulti-start approach was used to improve the probability of find-ing a globally-optimal design. The results from each strategy arepresented in Table 2.

When using the nested coordination strategy, the algorithmperforms well when optimizing for minimum loss. The per-formance value obtained is the best result and lies just belowthe Pareto curve obtained using MOGA. The simultaneous de-sign strategy, however, was not able to produce the same result.The optimal circuit layout and heat spreader topology have diffi-culty converging to the optimal designs. This is evident from theamount of intermediate density material (gray-scale) throughoutmost of the domain for the simultaneous result shown in Table 2.

5 ConclusionThis initial study has revealed many insights pertaining to

coupled electro-thermal system design. In using a lumped andcontinuum model co-simulation strategy, the effects of designcoupling are apparent as the design choices in one domain clearly

TABLE 2. Comparison of optimization results using nested and si-multaneous coordination strategies for DC loss minimization. Note thediffering temperature scales.

Topology

Copper FR-4 Copper FR-4

Temperature

0 0.01 0.02 0.03 0.04 0 1 2 3

Value PL = 0.00 PL = 0.11

Coordination Nested Simultaneous

affected the results in the other. This is observed in the multi-objective optimization studies where the Pareto front shifts to-wards the utopia point when incorporating additional design el-ements into the optimization problem. This highlights the im-portance of including thermal considerations when designing forelectrical efficiency. Though initial results are promising, thereare several issues to address that may help improve simulationaccuracy and deisgn performance.

When using the simultaneous coordination strategy withgradient-based optimization, it was difficult to obtain solutionsas good as those obtained via MOGA. A possible strategy to ad-dress this is to reformulate the topology optimization routine toinherently consider the electrical efficiency of the lumped sys-tem. In this way, gradient-based updates may converge moresmoothly. In addition to this convergence issue, there is inaccu-racy in the line integral equation used to approximate the induc-tance of a wire loop with large radius. Future work will investi-gate a continuum finite element strategy for approximating loopself-inductance.

Exploring complex heat spreader designs is also of interest.It was shown that when using heat spreader design minimizingthe maximum temperature on the domain, the temperature of thetrace wire was reduced considerably. This may create adverseeffects by reducing the damping of the dynamic electrical re-sponse. In designing the trace layout and shape for damping,this distributed heat source is easy to cool. Designing a heatspreader which targets sensitive components, but avoids the dis-tributed wire heat, may exhibit in a more robust system which hasboth good damping characteristics and retains a low temperaturefor heat sensitive components. This type of design explorationwould be possible if topology optimization was driven directlyby electrical system performance instead of pseudo objectives.

6 AcknowledgmentsThe authors would like to acknowledge the Toyota Research

Institute of North America for funding this work.

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