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Communication IC& Signal Processing Lab.

PostSim CoreGenerator IP in ISE 5.1i

with Verilog HDL

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Communication IC& Signal Processing Lab.

Step 1. Compile postsim libarary

compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs

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Step 2. Create postsim libarary

Verilog lib

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Communication IC& Signal Processing Lab.

Step 3. Run Xilinx CORE Generator

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Communication IC& Signal Processing Lab.

Step 4. Choose Multiplier IP

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Communication IC& Signal Processing Lab.

Step 5. Create files from CORE Generator

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Communication IC& Signal Processing Lab.Step 6. Prepare a top file for mult8x8.v(from Co

reGen)

module Top_mult8x8(a,b,o);

input [7:0] a,b;

output [15:0] o;

// ----- Begin Cut here for INSTANTIATION Template ---

// INST_TAG

mult8x8 ttt ( .a(a), .b(b), .o(o));

// INST_TAG_END

endmodule

Top_mult8x8.v

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Communication IC& Signal Processing Lab.

Step 7. Run Synplify_Pro Synthesizer

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Communication IC& Signal Processing Lab.

Step 8. Add two files in the project

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Communication IC& Signal Processing Lab.

Step 9. Prepare two files for implement

Generate from CoreGenGenerate from Synplify_Pro

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Communication IC& Signal Processing Lab.Step 10. Run Xilinx ISE 5.1i with E

DIF design flow

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Communication IC& Signal Processing Lab.Step 11. Add *.edn and *.edf in the proj

ect

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Communication IC& Signal Processing Lab.Step 12. Set the postsim generated files

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Communication IC& Signal Processing Lab.

Step 13. Generate postsim *.v and *.sdf

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Communication IC& Signal Processing Lab.

Step 14. Prepare files for post-simulation

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Communication IC& Signal Processing Lab.

Step 15. Run ModelSim, then change the directory

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Communication IC& Signal Processing Lab.

Step 16. Create a New library

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Communication IC& Signal Processing Lab.

Step 17. Run *.do batch file in command window

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Communication IC& Signal Processing Lab.

Step 18. Create a waveform window

Mouse right click

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Communication IC& Signal Processing Lab.

Step 19. Run, then produce the waveform

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Communication IC& Signal Processing Lab.

Appendix

glbl.v

test_mult8x8.v

timesim.v

fpga1.f

vlog -f fpga1.fvsim -L C:/Modeltech_5.7c/examples/Xilinx_libs/simprim_ver -L C:/Modeltech_5.7c/examples/Xilinx_libs/unisim_ver -L C:/Modeltech_5.7c/examples/Xilinx_libs/XilinxCoreLib_ver -sdftyp /mult2=c:/test-postsim/PS/timesim.sdf work.stimulus work.glbl

fpga1.do

You must modify the lib path

You must modify the applied region name

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Communication IC& Signal Processing Lab.

test_mult8x8.v

`timescale 1ns / 100ps

module stimulus;

reg[7:0] A,B;

wire[15:0] PRODUCT;

reg CLK;

reg Reset;

reg [15:0] D_PRODUCT;

reg [7:0] IN_A [3:0];

reg [7:0] IN_B [3:0];

reg [1:0] index;

// --------------------------------

Top_mult8x8 mult2 (A,B,PRODUCT);

// -------------------------------

always #10 CLK=~CLK;

initial

begin

Reset=1'b0;

CLK=1'b0;

#25 Reset=1'b1;

end

…………

………….

………….