1

Compact Modeling of Partially DepletedSilicon-on-Insulator Drain-Extended MOSFET(DEMOS) including High-voltage and Floating

Body EffectsTarun Kumar Agarwal, Amit R. Trivedi, Vaidyanathan Subramanian,

and M. Jagadesh Kumar, Senior Member, IEEE.

Abstract—In this paper, a scalable compact model for partiallydepleted SOI drain extended MOSFETs (DEMOS) is developedusing a sub-circuit approach. The proposed compact modelcaptures the special dc behavior of a partially depleted SOIDEMOS transistor. Our model accounts for high voltage effectssuch as quasi saturation, impact ionization in the drift regionalong with a floating body effect such as the kink effect inthe output characteristics of the floating body PD SOI DEMOStransistor. In the sub-circuit approach used, the channel regionis modeled using the BSIM4SOI model and the drift region ismodeled using a bias-dependent resistance model along with acurrent-controlled current source. The model is validated for aset of channel and drift lengths to demonstrate the scalabilityof the model. The accuracy of the proposed compact model isverified using 2-D numerical simulations.

Index Terms—SOI DEMOS, High voltage devices, quasi sat-uration, impact ionization, Sub circuit approach, floating bodyeffects, kink effect, Compact model, Scalability.

I. INTRODUCTION

Currently, the drain extended MOSFETs (DEMOS) havebecome quite preferable as a high voltage (HV) device forsmart power IC’s and interest in the accurate modeling of HVMOS transistors has increased in recent years due to the com-patibility of these devices with standard CMOS technology[1]. HV MOS transistors can be designed for a wide rangeof voltage supplies, ranging from 5 V to 1000 V, leading tonumerous applications, ranging from a power amplifier (PA) inmobile handsets and base stations to automotive systems [2].Over the years, as Si-RF technologies are maturing, silicon-on-insulator (SOI) HV MOSFETs have become a preferred choiceover bulk HV MOSFETs providing enhanced power addedefficiency (PAE) and reduced crosstalk [3]. Optimal design ofpower circuits requires an accurate compact model of partiallydepleted SOI DEMOSFETs, which captures the high voltagebehavior along with the floating body effects.

To model the bulk HV MOSFETs and the SOI HV MOS-FETs with a body contact, various modeling approaches are

This work was supported in part by the IBM Faculty award to M. J .Kumar.T. K. Agarwal and M. J. Kumar are with the Department of Electrical

Engineering, Indian Institute of Technology, Delhi 110016, India (e-mail:tarun.agrawal90@gmail.com, mamidala@ieee.org).

A. R. Trivedi and V. Subramanian are with Semiconductor Re-search and Development Center, IBM, Bangalore 560024, India (e-mail:amtrived@in.ibm.com, vaisubra@in.ibm.com).

reported in literature [4]–[9]. A frequently followed approachis to use a sub circuit along with the conventional low-voltageMOS transistor models. Some compact models are examplesof this approach such as HV-EKV [4], [5], MM20 models[6], [7]. These models account only for the quasi saturationeffect and show good results in terms of accuracy and speedfor both dc and ac domains. But, sufficient emphasis onaccurate modeling of other high voltage effects such as impactionization in the drift region is not present in these modelsand also channel length scaling is not reported for all dccharacteristics of HV MOSFETs. On the other hand, Wanget al. [10] report only the impact ionization in the drift regionat higher gate biases and a physical model based on the BSIM3substrate current model to model the impact ionization in thedrift region. To the best of our knowledge, there is no compactmodel in literature for the floating body partially depleted SOIDEMOSFETs taking into account the quasi saturation effect,the impact ionization in the drift region and the kink effect inthe output characteristics.

The aim of this paper is, therefore, to develop a scalablecompact model for partially depleted SOI DEMOSFETs si-multaneously considering all the above special dc effects. Tomodel these effects accurately, a sub-circuit consisting of abias-dependent resistor and a current-controlled current sourceare used along with the BSIM4SOI compact model [11], [12].The BSIM4SOI compact model can predict the kink for thegate biases where the channel region current is dominating.But, as the drift region starts dominating at higher gate biases,a sub-circuit is needed to model the kink effect along withthe other high voltage effects. The other effects dominantin SOI transistors such as self-heating effect (SHE) can beeasily modeled using the BSIM4SOI model and the developedmodel can be extended to capture ac behavior of a PD SOIDEMOS transistor. It may be noted that our compact model inits present form does not model the breakdown characteristicsaccurately. The accuracy of the proposed compact model isverified by 2-D device simulations [13].

II. DEVICE STRUCTURE AND SIMULATION RESULTS

Fig. 1 shows the cross sectional schematic of a conventionalfloating body PD SOI MOS and a floating body PD SOIDEMOS transistor respectively. It is shown that a floating

2

body DEMOS device shown in Fig. 1(b) is derived from a PDSOI NMOS device shown in Fig. 1(a) by simply extendingthe drain of the device with a lightly doped drift region.Similarly, a body contacted DEMOS device can be derivedfrom a floating body DEMOS device shown in Fig. 1(b) bysimply having a p-type doped region beneath the source. Thedevice parameters for simulation are given in Table. I basedon a fabricated high voltage PD SOI MOS device in [14]. Thedevice simulations are done using a 2-D numerical simulator,ATLAS from SILVACO [13]. To maintain sanity and self-consistency in the simulated data, calibration of the impactionization model in ATLAS is performed with the measureddata of a PD SOI DEMOS device fabricated with SOI CMOSprocess [14]. In calibration, impact ionization coefficients areoptimized to best fit the experimental results (AN1 = 2x106

cm−1, AN2 = 2x106 cm−1, BN1 = 1.7x106 V/cm and BN2 =1.7x106 V/cm). Further details are provided in Appendix. A.The drift region doping for the reference device is chosen tohave a breakdown voltage higher than 15 V for the floatingbody device and 20 V for the body contacted device. Someaspects such as graded channel doping density and gate overlapare not considered in the design of DEMOS device shown inFig. 1(b). This is due to the availability of sub micrometerphotolithography to define the channel length in the same wayas CMOS devices and a self aligned drift-region implantationto the gate, rather than relying on the double-diffusion process[15].

The concept of intrinsic drain potential (VK) has been apowerful tool to understand and model the high voltage effectsobserved in HV MOS transistors [16]. As Fig. 1(b) shows, VK

denotes the surface potential at the junction of the intrinsicMOS region and the drift region. Fig. 2 shows the variationof VK with gate and drain biases for the body contacted PDSOI DEMOS device obtained using ATLAS. An interestingobservation from Fig. 2 is that VK decreases with VG afterreaching a maximum (VKMAX ) at a fixed drain voltage VD.The reasons for this reduction in VK are clearly explained in[16]. Our analysis also shows that for lower values of VG,when the pinch-off of the depletion region in the drift regionoccurs, VK reaches its maximum value (VKMAX ) and currentwill be forced through the depletion zone of the drift region.However, as VG increases, pinch-off is delayed resulting ina local accumulation or corner injection of carriers in thesubstrate near the drift region leading to the VK reductionwith VG after reaching the maximum [16].

Further, it can be physically explained using Kirk Effect.Kirk effect states that when the injected electron density fromchannel to the drift region exceeds the doping concentrationof the drift region (Ndr), the peak electric field shifts from thechannel-drift (p−– n−) junction to the drift-drain (n−– n+)junction at higher gate biases [17]. It further explains that VK

increases with the gate voltage due to the existence of peakelectric field at the channel-drift (p−– n−) junction. This leadsto an increase in the surface potential at p−– n− junction withan increase in the gate voltage. And, with further increase inthe gate voltage, VK decreases due to the existence of the peakelectric field at the drift-drain (n−– n+) junction. As a result,the surface potential decreases at the p−– n− junction while

it increases at the n−– n+ junction. Based on the variation ofVK with the gate voltage, we define two modes of operationfor HV MOSFETs. First being, a low voltage FET (or intrinsicMOS) dominant mode of operation in which VK increases withthe gate voltage and reaches to a maximum (VKMAX ). Secondmode of operation is when the drift region starts dominatingand VK starts decreasing from VKMAX with an increase in thegate voltage. Based on the variation of VK , quasi saturationand the impact ionization in the drift region are physicallyexplained using Kirk effect which further explains the secondhump in the impact ionization current as shown in Fig. 3.

To understand the kink behavior in the floating body PDSOI DEMOSFETs, a conventional PD SOI MOS transistor ischosen as a starting point. And it is observed that a floatingbody PD SOI DEMOS device behaves as a conventionalfloating body PD SOI MOS device in the first mode ofoperation based on the VK variation. And, in the drift dominantsecond mode of operation, due to the impact ionization inthe drift region or electron-hole pair generation at n−– n+

junction, the floating body potential shows different behaviorthan a conventional floating body PD SOI MOS transistoras shown in Fig. 4. It is clear from Fig. 4(b) that in thedrift dominant mode of operation, the body potential startsrising at lower drain voltages, resulting in a kink in the outputcharacteristics of the floating body PD SOI DEMOSFETs atlower drain voltages. And, with further increase in the gatevoltage, the transistor enters the deep triode region of operationand the kink in the output characteristics disappears as shownin Fig. 5(b). In conclusion, to accurately model the kinkbehavior in the drift dominant mode of operation, the impactionization in the drift region is to be accurately modeled.

III. MODELING STRATEGY

Based on the physical insights gained from the devicesimulations, a compact model for partially depleted SOIDEMOSFETs is derived from the BSIM4SOI model and thesub-circuit. Here, the BSIM4SOI model is used to model theintrinsic MOS dominant mode of operation and the sub circuit,containing a bias-dependent resistance and a current-controlledcurrent source, is used to model the drift region dominantmode of operation of the transistor. Fig. 6 shows the SPICEsub-circuit implementation, containing an intrinsic MOSFET, abias-dependent resistor and a current-controlled current source(CCCS). The drain terminal of the intrinsic MOSFET is namedas “K”. VK is calculated using the BSIM4SOI model and thebias-dependent resistor within the simulator. In this way, thedrain to source current (IDS), body current (IB) and VK areexpressed explicitly in terms of the external node voltages (D,G, S, B, X) where X (substrate node) is always grounded.

A. Channel region or intrinsic MOS modeling

The intrinsic MOSFET of the PD SOI DEMOS de-vice is modeled using the BSIM4SOI compact model. TheBSIM4SOI model shows good capability in modeling floatingbody effects, observed in partially depleted SOI MOSFETs,along with self heating effects (SHE) by using an improvedimpact ionization current and parasitic BJT current model [18].

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In floating body configuration, only three external nodes arepresent for the intrinsic MOS which are gate (G), source (S)and substrate (X) while drain (K) and body (B) node voltagesof the intrinsic MOS (VB and VK) are calculated iteratively incircuit simulation. The potential of body node VB is calculatedby the balance of all body current components and VK iscalculated by the intrinsic MOS and the drift region currents.The body resistance, which is the part of the BSIM4SOImodel, is neglected in the developed model i.e. the bodyresistance model parameters present in the BSIM4SOI modelare set to their default values. The channel current, calculatedusing the BSIM4SOI model, is a function of VK , VG, VS ,VB and VX . The impact ionization current due to the channelregion (Iii1) is also calculated using the BSIM4SOI model.Iii1 is a function of IKS , VKS , VGS and VX .

B. Drift region modeling

In the drift region dominant mode of operation, the HV-MOSFETs shows two important effects: (i) quasi saturation(as the drain current compression in the output characteristics)and (ii) the impact ionization in the drift region (as a secondhump in the body current variation with gate voltage).

a) Quasi saturation: Attempts to model quasi saturationaccurately with JFET and a bias-dependent resistance arereported in literature [19]–[21]. However, to have a scalablemodel, bias-dependent resistance is more popular. In our work,a scalable bias-dependent drift region resistance (RDRIFT )model is based on the equations used in the industry standardcompact model HiSiM HV [22]. The modified equations forRDRIFT model are given as :

RDRIFT = (RD · LDR + f(VDS)) · f(VGS) · f(VBS) (1)

where,

f(VDS) = V asatDS ·RDVD (2)

f(VGS) =

(1 +RDV G1−

(RDV G1

RDV G2

)VGS

)(3)

f(VBS) = 1−RDV B · VBS (4)

RDVD = RDVD ·(1+

RDVDS

(LGATE · 102)RDVDSP

)·SC (5)

SC = LDR ·RDSC1 +RDSC2 (6)

Model parameters in this scalable bias-dependent drift resis-tance model are RD, asat, RDVG1, RDVG2, RDVB, RDVD,RDVDS, RDVDSP, RDSC1 and RDSC2. And, the extractionprocedure for these model parameters and hence, the driftresistance is given in Appendix. B.

b) Impact ionization in the drift region: The impact ion-ization current, in DEMOS devices, has contributions fromboth the channel-drift and the drift-drain junctions as shownin Fig. 3. As the BSIM4SOI’s improved impact ionizationmodel is only capable of modeling the impact ionization at thechannel-drift junction using Iii1, an extra current-controlledcurrent source (Iii2) is added between external drain andbody nodes to model the impact ionization at the drift-drainjunction. Here, the derived equations for extra body currentare physical as they involve VK , solved by the simulator. A

general body current equation due to the impact ionization inthe drift region can be written as:

Iii2 =

∫ LDR

0

alpha · IDS · exp(− B

Ey)dy (7)

Eq. 7 can be approximated into a well known equation asgiven below [23]:

Iii2 = alpha · (VD − VK) · IDS · exp(− B · LDR

(VD − VK)

)(8)

Here, VK is the potential at y=0 (at body-drift junction) andVD is the potential at y=LDR. As shown in Fig. 3, IB increaseswith gate voltage continuously until the device breaks downafter the transistor enters the triode region. To model thisbehavior, Eq. 8 is modified as:

Iii2 = alpha · (VD − VK) · IDS · exp(− B

Eeff

)(9)

where,

Eeff =

((VD − VK) · (VGS − VOFF )

coeff1

LDR

)(10)

Model parameters in the current-controlled current sourcemodel (Eq. 9) are alpha, B, VOFF and coeff1.

IV. RESULTS AND DISCUSSION

The model parameters of the developed compact modelare extracted using a commercial extraction software package,ICCAP, after implementing the SPICE sub-circuit shown inFig. 6 in Spectre [24]. The potential of the floating nodes“K” and “B” are calculated within the simulator using thein-built model, BSIM4SOI version 4, and the proposed sub-circuit. Moreover, VB and VK are modeled through an inferredapproach. And, to correctly model VB and VK , other corre-lation plots such as the output characteristics depicting thebody bias and the drift resistance effect are used. CalculatedVK and VB characteristics are shown in Fig. 7. Initially, afteridentifying the intrinsic MOSFET dominant regions, extractionof the BSIM4SOI model parameters is done for the scalabledata. These are regions where VK increases with gate anddrain biases. Next, to model VK correctly in the drift regiondominant mode of operation, bias-dependent resistor modelparameters are extracted for different channel and drift lengths.Fig. 7(a) shows that the calculated VK trend in the driftmode of operation is in complete agreement with the 2-Dnumerically simulated data. To model VB , which is crucialfor modeling the kink behavior, the body current is accuratelymodeled for different channel lengths as shown in Fig. 8.Further, to accurately model the kink in the output charac-teristics, the effect of different body voltages (VB) on thedrain current is accurately modeled using Fig. 9 and 10. And,all body voltage dependent model parameters are extractedusing the output characteristics and transfer characteristicsfor different body voltages, channel and drift lengths. Thecalculated results from the proposed model are calibrated withthe 2-D numerically simulated characteristics of both the bodycontacted and floating body PD SOI DEMOS transistors for

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different dimensions.Fig. 10 shows that the calculated output characteristics of thebody contacted transistor are in excellent agreement with the2-D numerically simulated data for different channel and driftlengths. It is clear that the quasi saturation effect is well mod-eled using a scalable bias-dependent drift resistance model.The drift resistance model captures the increase in the driftresistance with increase in the drift length shown in Fig. 10(a)and Fig. 10(b). It also predicts a higher drain resistance atlower channel lengths to model the quasi saturation effectat lower gate biases for short channel devices as shown inFig. 10(a) and Fig. 10(c). To accurately calculate the inferredbody potential in the floating body PD SOI DEMOS, all thebody current components such as impact ionization current,diode current and parasitic BJT currents need to be accuratelymodeled. Fig. 8 shows that the impact ionization current dueto both channel and drift region is well modeled for differentchannel lengths. The impact ionization in the channel regionis modeled using BSIM4SOI model parameters while impactionization in the drift region is modeled using a current-controlled current source described in section III. Fig. 11(a)shows that the kink behavior in the quasi saturation regime iswell captured by accurately modeling the impact ionizationin the drift region. The output characteristics of a floatingbody PD SOI DEMOS transistor is accurately modeled acrossvarious channel and drift lengths, as shown in Fig. 11. Thispaper mainly focuses in modeling high voltage and floatingbody effects observed in PD SOI DEMOSFETs. Other secondorder effects such as self heating are not taken into account,but can easily be included by extracting the BSIM4SOI selfheating model parameters.

V. CONCLUSION

A scalable compact model for high voltage PD SOI devicesis developed using a proposed sub-circuit approach. Thedeveloped compact model includes the high voltage and thefloating body effects observed in PD SOI DEMOS devices.The relationship between the proposed sub-circuit modelingapproaches and the physical mechanism of high voltage PDSOI MOS devices has also been discussed based on thedevice simulation results. Using the 2-D numerical simulator,ATLAS, a physical description of the specific dc behaviorof partially depleted SOI DEMOSFETs is presented. Thefamous kink effect is studied for high-voltage floating bodyPD SOI devices. And, it is demonstrated that the kink effectdisappears when the high voltage transistor enters deep quasisaturation regime. In the proposed modeling approach, thesub-circuit comprises of a intrinsic MOSFET and the driftregion which are modeled using the BSIM4SOI model anda bias-dependent resistor respectively. Additionally, to modelthe impact ionization in the drift region, a current-controlledcurrent source is added to the sub-circuit. The model per-formance is demonstrated for the 20-V DEMOS device byimplementing the SPICE sub-circuit in Spectre (Cadence).Generally, the proposed compact model can be run on anySPICE simulator, since the model equations of the standardBSIM4SOI compact model are not changed. Therefore, the

developed compact model in this paper will enable the accuratedesign of complex circuits using PD SOI DEMOS devicesbased on SPICE simulation.

ACKNOWLEDGMENT

The authors would like to thank Y. S. Chauhan, A. Bandy-opadhyay and folks at SRDC, Bangalore for their interest-ing comments. This work was sponsored by SemiconductorResearch and Development Center, IBM, Bangalore, India.We are grateful to the reviewers for their careful and criticalcomments which have significantly improved the readabilityand usefulness of the paper.

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[5] Y. S. Chauhan, R. Gillon, B. Bakeroot, F. Krummenacher, M. Declercq,and A. M. Ionescu, “An EKV-based high voltage MOSFET model withimproved mobility and drift model,” Solid State Electron., vol. 51, no.11/12, pp. 1581-1588, Nov./Dec. 2007.

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[10] J. Wang, R. Li, Y. Dong, X. Zou, L. Shao, and W. T. Shiau, “Substratecurrent characterization and optimization of high voltage LDMOStransistors,” Solid State Electron., vol. 52, no. 6, pp. 886-891, Jun. 2008.

[11] D. Sinitsky, S. Tang, A. Jangity, F. Assaderaghi, G. Shahidi and C.Hu, “Simulation of SOI devices and circuits using BSIM3SOI,” IEEETransactions on Electron Devices, vol. 19, no. 9, pp. 323-325, Sep 1998.

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[17] M.B. Willemsen and R. van Langevelde, “High-voltage LDMOS com-pact model for RF applications,” in IEDM Technical Digest., 2005, pp.208-211.

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APPENDIX ACALIBRATION PROCEDURE

To achieve sanity and self consistency in the data obtainedusing ATLAS for modeling purpose, the coefficients of theimpact ionization model, in ATLAS, are found out usingthe calibration procedure described below. While, the otherphysical models, used in simulation by ATLAS, use the defaultvalue of coefficients.In our calibration, a device structure similar to the one usedin [14] is created and simulated using ATLAS. Then, theoutput characteristics of SOI DMEOS transistor with andwithout the body contact are compared. Fig. 12(a) and 12(b)depict the measured output characteristics and those obtainedusing TCAD simulations primarily to show the off statebreakdown voltage and the kink in the output characteristics.The calibrated device used for the TCAD simulation is not theexact replica of the experimental device. The main intention ofshowing the experimental data from [14] in Fig. 12 was merelyas a guideline in order to come up with self consistent andmeaningful data from device simulations which could then beused for the modeling part. However, the simulated data usedin this paper is self-consistent which is shown by the presenceof the kink in the output characteristics of the floating bodydevice, the lower breakdown voltage of floating body devicein comparison to the body contacted device and the scalingbehavior with the channel and the drift length. In the end, theimpact ionization model coefficients are optimized to best fitthe TCAD generated results such as the off-state breakdownvoltage of SOI DEMOS device, with and without the bodycontact.

APPENDIX BDRIFT RESISTANCE EXTRACTION PROCEDURE

The drift resistance equation is, based on the equations usedin the industry standard compact model HiSiM HV, given byEq. 1. The equation shows the drift resistance dependence ongate, drain and body bias along with the gate length. Theextraction procedure for the model parameters used in theseequations can be summarized in the following steps:

1) Firstly, a wide gate length device is chosen for extractingthe model parameters used in RDRIFT equations suchas RD, asat, RDVG1, RDVG2, RDVB and RDVD.

• At low drain biases, all the BSIM4SOI modelparameters pertaining to the mobility, subthresholdslope, VTLIN and body effects are extracted.

• Using the IDLIN at higher gate biases, the RDRIFT

at low drain bias is modeled using the parameterRD. This is followed by the medium and high drainbias modeling i.e. the output characteristics fitting.

• The drain bias dependence of RDRIFT i.e. RDVD isextracted by fitting the output characteristics slopeand the quasi saturation regime.

• Similarly, the gate bias dependence of RDRIFT i.e.RDVG1 and RDVG2 and the body bias dependencei.e. RDVB are extracted.

2) Then, the deviations associated with the small geome-tries are taken into account by extracting the parametersRDVDS, RDVDSP, RDSC1 and RDSC2, following thestep 1.

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TABLE IDEVICE PARAMETERS USED IN THE SIMULATION, DERIVED FROM A

REFERENCE DEVICE IN [14].

Symbol Description ValuetOX Gate oxide thickness 30 nmtSI Silicon film thickness 180 nm

tBOX Buried oxide thickness 1 µmNch Channel doping (p-type) 1.5x1017 cm−3

Ndr Drift region doping (n-type) 4x1016 cm−3

— S/D doping concentration 1020 cm−3

LCH Channel length 0.64 µmLDR Drift region length 1 µm

SourceGate

Drain

P-Body

0Y

X

tOX

tSI

tBOX

LCH

Buried Oxide

N+ N+

Substrate

Substrate(a)

SourceGate

Drain

P-Body

0Y

X

tOX

tSI

tBOX

LCH

LDR

VK

Buried Oxide

N+ N+N-

Substrate

Substrate(b)

Fig. 1. Cross sectional schematics of the n-channel devices. (a) A con-ventional floating body partially depleted SOI MOSFET. (b) A floating bodypartially depleted drain extended MOSFET (DEMOS).

0 1 2 3 4 5 60

0.5

1

1.5

2

Gate Voltage(V)

VK(V

)

2.0

3.0

4.0

5.0V

DS=6.0 V

Mode I :Conventional MOSFET operation

Mode II :Drift dominant mode of operation

Fig. 2. Variation of VK with gate bias for different drain biases obtainedusing ATLAS for a body contacted PD SOI DEMOS device.

0 1 2 3 4 5 6 70

1

2

3

4

Gate Voltage(V)

Bod

y C

urre

nt (

nA/µ

m)

4.0

5.0

5.5

VDS

=6.0 V

Impact ionization current same as conventional MOSFET

Impact ionization in the drift region

Fig. 3. Variation of the body current with gate bias for a body contacted PDSOI DEMOS device showing impact ionization in the drift region at highergate biases, obtained using ATLAS.

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0 1 2 3 4 50

0.2

0.4

0.6

0.8

1

Drain Voltage(V)

VB(V

)

VGS

=2.0 V

VGS

=5.0 V

in steps of 0.5 V

(a)

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

Drain Voltage(V)

VB(V

)

VGS

=2.0 V

3.0 3.5

4.0

4.5 5.0

(b)

Fig. 4. Body potential variation with drain bias obtained using ATLAS. (a)A conventional floating body partially depleted SOI MOSFET. (b) A floatingbody partially depleted drain extended MOSFET (DEMOS).

0 1 2 3 4 50

100

200

300

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

(a)

0 1 2 3 4 5 60

20

40

60

80

100

120

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

Mode I

Mode II

(b)

Fig. 5. Output characteristics of the n-channel devices obtained usingATLAS. (a) A conventional floating body partially depleted SOI MOSFET.(b) A floating body partially depleted drain extended MOSFET (DEMOS).

G

K

B

S

D

R(VG,VD)

X

Iii1

Iii2=f(ID,VD,VK,VG)

BSIM4SOI Model

Fig. 6. SPICE sub-circuit implementation with the BSIM4SOI compactmodel.

8

3 3.5 4 4.5 5 5.5 60

0.5

1

1.5

2

Gate Voltage(V)

VK(V

)

2.0

3.0

4.0

5.0

VDS

=6.0 V

2D numerical simulationmodeled

(a)

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

1

Drain Voltage(V)

VB(V

)

VGS

=2.0 V

3.03.5

4.0 4.5

5.0

2D numerical simulationmodeled

(b)

Fig. 7. (symbols) 2-D numerically simulated and (solid lines) calculatedVK and VB characteristics of (a) Body contacted PD SOI DEMOS and (b)Floating body PD SOI DEMOS using BSIM4SOI approach for LCH=0.64µm and LDR=1 µm

0 1 2 3 4 5 6 70

1

2

3

4

Gate Voltage(V)B

ody

Cur

rent

(nA

/µm

)

4.0

5.0

5.5

VDS

=6.0 V

2D numerical simulationmodel

(a)

0 1 2 3 4 5 6 70

0.2

0.4

0.6

0.8

1

1.2

Gate Voltage(V)

Bod

y C

urre

nt (

nA/µ

m)

4.0

5.0

5.5

VDS

=6.0 V

2D numerical simulationmodel

(b)

Fig. 8. (symbols) 2-D numerically simulated and (solid lines) calculatedbody current characteristics of PD SOI DEMOS using BSIM4SOI approachfor (a) LCH=0.64 µm and LDR=1 µm. (b) LCH=3 µm and LDR=1 µm.

9

0 1 2 3 4 5 60

20

40

60

80

100

120

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

VGS

=4.0, 4.5, 5.0 V

2D numerical simulationmodeled

(a)

0 1 2 3 4 5 60

20

40

60

80

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0VGS

=3.5, 4.0, 4.5, 5.0 V

2D numerical simulationmodeled

(b)

0 1 2 3 4 5 60

20

40

60

80

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

2D numerical simulationmodeled

(c)

Fig. 9. (symbols) 2-D numerically simulated and (solid lines) calculatedoutput characteristics of a body contacted PD SOI DEMOS using BSIM4SOIapproach at VB = 0.7 V for (a) LCH=0.64 µm and LDR=1 µm. (b)LCH=0.64 µm and LDR=3 µm. (c) LCH=3 µm and LDR=1 µm.

0 1 2 3 4 5 60

20

40

60

80

100

120

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.04.5

VGS

=5.0 V

2D numerical simulationmodeled

(a)

0 1 2 3 4 5 60

20

40

60

80

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

VGS

=4.0, 4.5, 5.0 V

2D numerical simulationmodeled

(b)

0 1 2 3 4 5 60

20

40

60

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

2D numerical simulationmodeled

(c)

Fig. 10. (symbols) 2-D numerically simulated and (solid lines) calculatedoutput characteristics of a body contacted PD SOI DEMOS using BSIM4SOIapproach for (a) LCH=0.64 µm and LDR=1 µm. (b) LCH=0.64 µm andLDR=3 µm. (c) LCH=3 µm and LDR=1 µm.

10

0 1 2 3 4 5 60

20

40

60

80

100

120

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

2D numerical simulationmodeled

(a)

0 1 2 3 4 5 60

20

40

60

80

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5V

GS=4.0, 4.5, 5.0 V

2D numerical simulationmodeled

(b)

0 1 2 3 4 5 60

20

40

60

Drain Voltage (V)

Dra

in C

urre

nt (

µA

/µm

)

2.0

3.0

3.5

4.0

4.5

VGS

=5.0 V

2D numerical simulationmodeled

(c)

Fig. 11. (symbols) 2-D numerically simulated and (solid lines) calculatedoutput characteristics of a floating body PD SOI DEMOS using BSIM4SOIapproach for (a) LCH=0.64 µm and LDR=1 µm. (b) LCH=0.64 µm andLDR=3 µm. (c) LCH=3 µm and LDR=1 µm.

(a)

0 5 10 15 20 250

50

100

150

200

Drain Voltage (V)

Dra

in C

urre

nt (

µA/µ

m)

with body contactwithout body contact

BVoff

(b)

Fig. 12. Measured and TCAD generated output characteristics of a SOIDEMOS device with and without body contact. (a) Measured output character-istics [14] and (b) Output characteristics obtained using ATLAS at VGS=3.5,3.0, 2.5, 2.0, 1.5, 0 V.

11

Tarun Kumar Agarwal was born in Aligarh, Ut-tar Pradesh, India. He received the B.Tech degreein Electronic and communication Engineering fromZ.H.C.E.T., Aligarh in 2008 and the M.Tech. de-gree in VLSI Design Tools and Technology fromIndian Institute of Technology Delhi, India in 2010.His research interest includes compact modeling ofpower semiconductor devices, nano-scale MOSFETsand low-power circuit design.

Amit Ranjan Trivedi was born in Agra, India, in1984. He received the B.Tech and M.Tech degreesin Electrical Engineering from Indian Institute ofTechnology, Kanpur (IITK). He pursued his mas-ter’s thesis in ’Developing Numerical Techniques toCalculate Band Strucutre of Self Assembled Quan-tum Dots’. In 2008, he joined IBM SemiconductorResearch and Development Center (SRDC) in Ban-galore, India. His research interest includes compactmodeling of MOSFET, high voltage devices such asLDMOS, and nano-electronic devices.

Vaidyanathan Subramanian received his Bache-lors’ Degree in Materials Science and Engineeringfrom IIT Chennai in 2000 and his Masters’ Degreein Electrical and Electronics Engineering from PennState University, USA. From 2003 to 2008, he wasa researcher at IMEC Belgium where he worked onaspects of technology, characterization and modelingof deep sub-micron CMOS devices. In 2008 heobtained his Ph.D. from KU Leuven, Belgium onthe topic ”Analog/RF performance of Multiple GateMOSFETs”. Since 2008, he is working at IBM

SRDC, Bangalore, India on aspects of RF SOI FET modeling for IndustryProcess Design Kits (PDKs). He has (co)-authored more than 25 papers.

M. Jagadesh Kumar was born in Mamidala,Andhra Pradesh, India. He received the M.S. andPh.D. degrees in electrical engineering from theIndian Institute of Technology (IIT), Madras, India.

From 1991 to 1994, he performed a postdoc-toral research on the modeling and processing ofhighspeed bipolar transistors with the Departmentof Electrical and Computer Engineering, Universityof Waterloo, Waterloo, ON, Canada. While withthe University of Waterloo, he also did research onamorphous-silicon thin-film transistors. From July

1994 to December 1995, he was initially with the Department of Electronicsand Electrical Communication Engineering, IIT, Kharagpur, India, and then,he was with the Department of Electrical Engineering, IIT, New Delhi, India,where he became an Associate Professor in July 1997 and has been a FullProfessor in January 2005. He is currently the Chair Professor of the NXP(Philips) (currently, NXP Semiconductors India Pvt. Ltd.) established at IITDelhi by Philips Semiconductors, The Netherlands. He is the Coordinatorof the Very Large Scale Integration (VLSI) Design, Tools, and Technologyinterdisciplinary program at IIT Delhi. He is also a Principal Investigator ofthe Nano-scale Research Facility at IIT Delhi.

His research interests include nanoelectronic devices, device modeling andsimulation for nanoscale applications, integrated-circuit technology, and powersemiconductor devices. He has published extensively in these areas of researchwith three book chapters and more than 145 publications in refereed journalsand conferences. His teaching has often been rated as outstanding by theFaculty Appraisal Committee, IIT Delhi.

Dr. Kumar is a fellow of the Indian National Academy of Engineering,The National Academy of Sciences, India and the Institution of Electronicsand Telecommunication Engineers (IETE), India. He is recognized as a Distin-guished Lecturer of the IEEE Electron Devices Society (EDS). He is a memberof the EDS Publications Committee and the EDS Educational ActivitiesCommittee. He is an Editor of the IEEE TRANSACTIONS ON ELECTRONDEVICES. He was the lead Guest Editor for the following: 1) the joint specialissue of the IEEE TRANSACTIONS ON ELECTRON DEVICES and theIEEE TRANSACTIONS ON NANOTECHNOLOGY (November 2008 issue)on Nanowire Transistors: Modeling, Device Design, and Technology and 2)the special issue of the IEEE TRANSACTIONS ON ELECTRON DEVICESon Light Emitting Diodes (January 2010 issue). He is the Editor-in-Chiefof the IETE Technical Review and an Associate Editor of the Journal ofComputational Electronics. He is also on the editorial board of Recent Patentson Nanotechnology, Recent Patents on Electrical Engineering, Journal of LowPower Electronics, and Journal of Nanoscience and Nanotechnology. He hasreviewed extensively for different international journals.

He was a recipient of the 29th IETE Ram LalWadhwa GoldMedal forhis distinguished contribution in the field of semiconductor device designand modeling. He was also the first recipient of the India SemiconductorAssociation-VLSI Society of India TechnoMentor Award given by the IndiaSemiconductor Association to recognize a distinguished Indian academicianfor playing a significant role as a Mentor and Researcher. He is also arecipient of the 2008 IBM Faculty Award. He was the Chairman of theFellowship Committee of The Sixteenth International Conference on VLSIDesign (January 4-8, 2003, New Delhi, India), the Chairman of the TechnicalCommittee for High Frequency Devices of the International Workshop on thePhysics of Semiconductor Devices (December 13-17, 2005, New Delhi), theStudent Track Chairman of the 22nd International Conference on VLSI Design(January 5-9, 2009, New Delhi), and the Program Committee Chairman ofthe Second International Workshop on Electron Devices and SemiconductorTechnology (June 1-2, 2009, Mumbai, India).