compaq presario cq40 - compal la-4101p
TRANSCRIPT
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Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cover SheetCus tom
1 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Compal confidentialSchematics Document
Mobile Penryn uFCPGA with IntelCantiga_GM+ICH9-M core logic
2008-01-01
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Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Block DiagramCus tom
2 46S aturday, January 05, 2008
2006/02/13 2006/03/10Compal Electronics, Inc.
Compal confidential
Thermal SensorEMC1402
Fan conn
Mobile Penryn
uFCPGA-478 CPU
FSB667/800/1066 MHz 1.05V
H_A#(3. .35)
H_D#(0. .63)
FCBGA 1329
Intel Cantiga MCH
DMI X4
BANK 0, 1, 2, 3DDR2 SO-DIMM X2DDR2 667MHz 1.8V
Dual Channel
LPC BUS
DC/DC Interface CKT.
RTC CKT.
mBGA-676
Intel ICH9-M
Touch Pad CONN. Int.KBD
ENE
RTL8102EL(10/100M)
RJ45/11 CONN
PCI-E BUS*5
LED
SATA HDD Connector
SATA Master-1
SATA Slave
C-Link
Codec_IDT9271B7Audio CKT AMP & Audio Jack
TPA6017A2
USB conn x1
USB2.0 X12
Azalia
BT Conn
KB926
P6, 7, 8
P9,10, 11, 12, 13, 14
P15, 16
P20,21,22,23
P24
P25
P25
P21
P28 P29
P30
P33
P32
P32
P36
P06
P06
Montevina Consumer 14" UMA
SPI
Clock Generator SLG8SP553V
P17
CK505 72QFN
CRT
LVDS PanelInterface
P18
SATA Slave
P30e-SATA Connector
New Card
P26
HDMI P35
P19
Support V1.3P30
USB Camera
Capsense switch Conn
SATA ODD Connector
P19
P24
P31
SPI ROM25LF080A
MDCP29
Mini-Card
P26P26
Mini-Card
WLANTV-tuner orRobson
P33
P33
Audio board、CIR Conn P29
USB Board ConnP30
PCIECardReaderJMB385 P27
Finger printP30
USB conn x2
5 in1 SlotP33
K/B backlight ConnP33
P24
P24
ACCELEROMETER-2 BOSCH
ACCELEROMETER-1 ST
USB2.0*1
RGB
RJ45
SPDIF
CIR
MIC*1
LINE-OUT*1
Dock
P34
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Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0 .3
Notes ListCus tom
3 46S a turday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
O MEANS ON X MEANS OFFVoltage Rails
+0.9V
S3
+3VS
X
+3VALW
+5VS
S1
+2.5VS
+CPU_CORE
+VCCP
powerplane
O
S5 S4/ Battery only
+B
State
+1.5VS
+1.8V
S5 S4/AC & Batterydon't exist
S5 S4/AC
+5VALW
S0
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
SERIALEEPROM
SMB_EC_CK2
SOURCE
KB926
INVERTER BATTThermalSensor SODIMM CLK CHIP
SMBUS Control Table
SMB_CK_CLK1
SMB_CK_DAT1ICH9
MINI CARD
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
LCD_CLK
LCD_DATCantiga
LCD
X V1 0 1 0 0 1 0 0A4
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
ADDRESS
DDR SO-DIMM 0
1 1 0 1 0 0 1 0
DEVICE
+1.8VS
O
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
X
X
X
XX
V
V
V V V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
KB926
DEBUG@ : means just reserve for debug.
CONN@ : means ME part
GS @ : means just reserve for G sensor
ESATA @ : means just reserve for ESATA
BATT @ : means need be mounted when 45 level assy or rework stage.
45@ : means need be mounted when 45 level assy or rework stage.
FP @ : means just reserve for Finger Print
USB-1 Right side
USB-8 MiniCard(WWAN/TV)
USB-6 Bluetooth
USB-5 WLAN
USB-4 Camera
USB-2 Left side(with ESATA)
USB-10 X
USB-9 Express card
USB-3 Dock
USB-7 Finger Printer
USB assignment:
USB-11 X
USB-0 Right side
PCIe-2 X
PCIe assignment:PCIe-1 TV /WWAN/Robeson
PCIe-3 WLAN
PCIe-4 GLAN (Realtek)
PCIe-5 Card reader
PCIe-6 New Card
Multi @ : means just reserve for Multi Bay
43154432L01 UMA GM :::: PA FF (SI-1)43154432L02 UMA GM :::: PR FF (SI-1)43154432L03 UMA:::: GL PR FF-
Cantiga GM45 B0(QR32) SA00001P930::::
ICH9M A2 ES2 Base :::: SA00002AN10
Cap sensor board
X
X
X
V
NEW CARD G sensor
V V
X X
X
X
X
X
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
43154432L04 UMA GM:::: OPP (SI-1)43154432L05 U:::: MA GL OPP
43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP:::: @/ESATA@/GS@/Multi@/2MiniC@43154432L02 Main@/DEBUG@/DOCK@/NewC:::: @/FP@/ESATA@/GS@/2MiniC@43154432L03 Main@/DEBUG@/DOC:::: K@/NewC@/FP@/2MiniC@43154432L04 OP:::: P@/DEBUG@43154432L05 OP:::: P@/DEBUG@
2MiniC@ : means just reserve for 2nd Mini card sl ot
DAZ03V00100 --->OPPDA600007100 --->Main
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B B
A A
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Power deliveryC
4 46Saturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
VINAC
DC BATT
B+
INVPWR_B+
B++
B+++
1.05V_B+
LVDS CON
+3VALW
+5VALW
ICH9
+3VAUX_BT
SPI ROM
+3VALW_EC
+3VS
Finger printer
PC Camera
MDC 1.5
New card
ICH9
0.3A
278mA
300mA
60mA
20mA
10mA
+1.8V
LAN +3VS_DVDDALC268
25mA
+5VS+VDDAIDT 9271B7
35mA
50mA
1A
177mA
35mA
+LCDVDD1.5A
+3VS_CK505250mA
+5VAMP10mA
ODD1.8A
SATA700mA
MCH3.7A
DDR2 800Mhz 4G x28 A
+0.9V50mA
+VCCP
ICH9
MCH1.26A
CPU2.3A
1.17A
LVDS CON
50mA
3.39A5.89A
3.7 X 3=11.1V
1.7A
2A
1.3A0.58A
12.11A1.9A
4.7A
7A
+V_BATTERY Dock con1A
+1.5VS
ICH_VCC1_5ICH9
657mA
ICH91.56A
2.2A0.3A
Muti Bay1.8A
JMB385550mA
CPU_B+ +VCC_CORE10mA2A
CPU34A/1.025V
Mini card (WLAN)1A
1AMini card (TV tu/WWAN/Robeson)
A
A
1 1
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0 .3
Power sequenceCus tom
5 46S a turday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_ THERMDA
H_T H ERMDC
THERM#
SMB_EC_DA2
SMB_EC_CK2
H_P ROCHOT# O CP#
H_T H ERMDC
H_THERMTRIP#
H_ THERMDAH_ THERMDA_RH_T H ERMDC_R
H_P ROCHOT#
H _HITM#H _HIT#
H_RESET#
H_T RDY#
H _RS#1H _RS#2
H _RS#0
H _LOCK#
XDP_HOOK1
XDP_HOOK1
XDP_BPM#3
XDP_DBRESET#_R
XDP_BPM#0XDP_BPM#1
XDP_BPM#2
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TDI
XDP_TMS
XDP_TCK
XDP_TRST#
XDP_TCK
XDP_TDO
H_RESET#
XDP_TRST#
XDP_TMS
XDP_TDO
XDP_TDI
H_P WRG OOD_R
H_RESET#_R
XDP_BPM#5
CLK_CPU_XDP#CLK_CPU_XDP
XDP_BPM#4XDP_BPM#5
H_ IE RR#
H_A#3
H_A#10
H_A#13
H_A#11
H_ADSTB#0
H_A#7
H_A#9
H_A#16
H_A#6
H_A#8
H_A#12
H_A#15
H_A#5
H_A#14
H_A#4
H _REQ#2
H _REQ#4
H _REQ#1
H _REQ#3
H_A#32
H_A#34H_A#35
H_A#33
H_A#18
H_A#30
H_A#27H_A#26
H_A#21
H_A#17
H_A#20
H_A#25
H _REQ#0
H_ADSTB#1
H_A#28H_A#29
H_A#19
H_A#23H_A#24
H_A#22
H_A#31
H_SMI#
H_STPCLK#H_ I NTR
H_ IG NNE#
H_A20M#H_F ERR#
H_N MIC LK_CPU_BCLK#C LK_CPU_BCLK
XDP_BPM#0
XDP_BPM#2XDP_BPM#3
XDP_TRST#
XDP_BPM#1
XDP_TCK
XDP_TMSXDP_TDOXDP_TDI
XDP_DBRESET#
XDP_BPM#5XDP_BPM#4
H_B NR#H _ADS#
H_ BPRI#
H_D EFER#
H_ DBSY#H_DRDY #
H _BR0#
H_ INIT#H_ IE RR#
+ FAN
OCP# <22>
H_THERMTRIP# <9,21>
H_HIT# <9>H_HITM# <9>
H_RESET# <9>H_RS#0 <9>H_RS#1 <9>H_RS#2 <9>
H_T RDY# <9>
H_LOCK# <9>
F AN_PWM<32>
H_P WRGOOD<7,21> CLK_CPU_XDP <17>CLK_CPU_XDP# <17>
H_A#[3..16]<9>
H_ADSTB#0<9>
H_REQ#0<9>H_REQ#1<9>H_REQ#2<9>
H_A#[17..35]<9>
H_ADSTB#1<9>
H_REQ#4<9>H_REQ#3<9>
H_A20M#<21>H_F ERR#<21>
H_ IGNNE#<21>
H_STPCLK#<21>H_ INTR<21>H_NMI<21>H_SMI#<21>
CLK_CPU_BCLK <17>CLK_CPU_BCLK# <17>
XDP_DBRESET# <22>
H_ADS# <9>H_BNR# <9>
H_BPRI# <9>
H_DEFER# <9>H_DRDY # <9>H_DBSY# <9>
H_BR0# <9>
H_ INIT# <21>
SMB_EC_CK2 <32>
SMB_EC_DA2 <32>
+3VS
+3VS
+V CCP
+V CCP
+5VS
+3VS
+V CCP+VCCP
+VCCP
+V CCP
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Penryn(1/3)-AGTL+/ITP-XDPCus tom
6 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Address:100_1100H_THERMDA, H_THERMDC routing together,Trace w idth / Spacing = 10 / 10 mil
For Merom, R14 and R15 are 0ohmFor Penryn, R14 and R15 are 100ohm.
PWM Fan Control circuit
Place R191 within 200ps (~1") to CPU
This shall place near CPU
ITP-XDP ConnectorChange value in 5/02
Removed at 5/30.(FollowChimay)
Place TP with a GND 0.1" away
11/01 update
Change PCB Footprint fromACES_85204-02001_2P toACES_88231-02001_2P
R11 200_0402_1%12
S
GD Q2
SI3456BDV-T1-E3_TSOP6
3
624
51
R120_0402_5%
1 2
JP2
ACES_88231-02001C ONN@
11
22
GND3
GND4
R14 100_0402_5%1 2
C44.7U_0805_10V4Z
1
2
R 7 54.9_0402_1%1 2
R1856_0402_5%
12
R11K_0402_5%
@1 2
R1756_0402_5%
@12
R15 100_0402_5%1 2
EB
C
Q1MMBT3904_NL_SOT23-3
@
2
3 1
AD
DR
GR
OU
P_0
AD
DR
GR
OU
P_1
CO
NT
RO
LX
DP
/IT
P S
IGN
ALS
H CLK
THERMAL
RE
SE
RV
ED
ICH
JCPU1A
P enryn
A[10]#N3
A[11]#P5
A[12]#P2
A[13]#L2
A[14]#P4
A[15]#P1
A[16]#R1
A[17]#Y2
A[18]#U5
A[19]#R3
A[20]#W6
A[21]#U4
A[22]#Y5
A[23]#U1
A[24]#R4
A[25]#T5
A[26]#T3
A[27]#W2
A[28]#W5
A[29]#Y4
A[3]#J4
A[30]#U2
A[31]#V4
RSVD[01]M4
RSVD[02]N5
RSVD[03]T2
RSVD[04]V3
RSVD[05]B2
RSVD[06]D2
RSVD[07]D22
A[4]#L5
A[5]#L4
A[6]#K5
A[7]#M3
A[8]#N2
A[9]#J1
A20M#A6
ADS# H1
ADSTB[0]#M1
ADSTB[1]#V1
RSVD[08]D3
BCLK[0] A22
BCLK[1] A21
BNR# E2
BPM[0]# AD4
BPM[1]# AD3
BPM[2]# AD1
BPM[3]# AC4
BPRI# G5
BR0# F1
DBR# C20
DBSY# E1
DEFER# H5
DRDY# F21
FERR#A5
HIT# G6
HITM# E4
IERR# D20
IGNNE#C4
INIT# B3
LINT0C6
LINT1B4
LOCK# H4
PRDY# AC2
PREQ# AC1
PROCHOT# D21
REQ[0]#K3
REQ[1]#H2
REQ[2]#K2
REQ[3]#J3
REQ[4]#L1
RESET# C1
RS[0]# F3
RS[1]# F4
RS[2]# G3
SMI#A3
STPCLK#D5
TCK AC5
TDI AA6
TDO AB3
THERMTRIP# C7
THERMDA A24
THERMDC B25
TMS AB5
TRDY# G2
TRST# AB6
A[32]#W3
A[33]#AA4
A[34]#AB2
A[35]#AA3
RSVD[09]F6
C 2
0.1
U_
04
02
_1
6V4Z 1
2
R 6 54.9_0402_1%@ 1 2
JP1
SAMTE_BSH-030-01-L-D-AC ONN@
GND01
OBSFN_A03
OBSFN_A15
GND27
OBSDATA_A09
OBSDATA_A111
GND413
OBSDATA_A215
OBSDATA_A317
GND619
OBSFN_B021
OBSFN_B123
GND825
OBSDATA_B027
OBSDATA_B129
GND1031
OBSDATA_B233
OBSDATA_B335
GND1237
PWRGOOD/HOOK039
HOOK141
VCC_OBS_AB43
HOOK245
HOOK347
GND1449
SDA51
SCL53
TCK155
TCK057
GND1659
GND1 2
OBSFN_C0 4
OBSFN_C1 6
GND3 8
OBSDATA_C0 10
OBSDATA_C1 12
GND5 14
OBSDATA_C2 16
OBSDATA_C3 18
GND7 20
OBSFN_D0 22
OBSFN_D1 24
GND9 26
OBSDATA_D0 28
OBSDATA_D1 30
GND11 32
OBSDATA_D2 34
OBSDATA_D3 36
GND13 38
ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42
VCC_OBS_CD 44
RESET#/HOOK6 46
DBR#/HOOK7 48
GND15 50
TD0 52
TRST# 54
TDI 56
TMS 58
GND17 60
C 1 0.1U_0402_16V4Z12
R 5 54.9_0402_1%1 2
R91K_0402_5%
12
D1
RB751V_SOD323
21
R16
10K_0402_5%1 2
C50.1U_0402_16V4Z
1
2
R 3 54.9_0402_1%1 2
R 4 54.9_0402_1%1 2
T1
U 1
EMC1402-1-ACZL-TR_MSOP8
DN3
DP2
VDD1
ALERT# 6
SMCLK 8
THERM#4 GND 5
SMDATA 7
D2
RLZ5.1B_LL34
@
12
R 2 54.9_0402_1%1 2
R 8 54.9_0402_1%1 2
R13 49.9_0402_1%1 2
R10 1K_0402_1%1 2
C3
2200P_0402_50V7K1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_CPU_GTLREF
H_ D#4
H _D#14
H _D#10H_ D#9
H_ D#3
H _D#13
H_ D#6
H_ D#2
H_ D#8
H _D#12
H_ D#1
H_ D#5
H_ D#7
H _D#11
H_ D#0
H _D#15
H _D#27
H _D#25
H _D#31
H _D#24
H _D#20
H _D#30
H _D#23
H _D#19
H _D#29
H _D#16
H _D#18
H _D#22
H _D#26
H _D#28
H _D#17
H _D#21
H_D INV#0
H_D INV#1H_DSTBP#1H_DSTBN#1
H_DSTBP#0H_DSTBN#0
+ VCCPA+ VCCPB
VSSSENSE
V CCSENSE
VSSSENSE
V CCSENSE
+V_CPU_GTLREFTEST1
H _D#35
H _D#46H _D#47
H _D#37
H _D#34
H _D#41
H _D#45
H _D#43
H _D#33
H _D#39H _D#40
H _D#44
H _D#32
H _D#42
H _D#38
H _D#36
H_D INV#2
H_DSTBN#2H_DSTBP#2
H_D INV#3
H_DSTBN#3H_DSTBP#3
H _D#48
H _D#56
H _D#52
H _D#59
H _D#63
H _D#55
H _D#51
H _D#62
H _D#58
H _D#54
H _D#50
H _D#57
H _D#61
H _D#53
H _D#49
H _D#60
COMP0
COMP2COMP3
COMP1
H_P WR GOODH _CPUSLP#
H_DPSLP#H_DPRSTP#
H_PSI#
H_DP WR#
TEST3
TEST7CPU_BSEL0
TEST4
CPU_BSEL1
TEST5TEST6
CPU_BSEL2
TEST2
V CCSENSE <43>
VSSSENSE <43>
H_D# [0..15]<9>
H_DSTBN#0<9>H_DSTBP#0<9>H_DINV#0<9>H_D#[16..31]<9>
H_DSTBN#1<9>H_DSTBP#1<9>H_DINV#1<9>
CP U_VID0 <43>CP U_VID1 <43>CP U_VID2 <43>CP U_VID3 <43>CP U_VID4 <43>CP U_VID5 <43>CP U_VID6 <43>
H_D#[32..47] <9>
H_DSTBN#2 <9>H_DSTBP#2 <9>H_DINV#2 <9>H_D#[48..63] <9>
H_DSTBN#3 <9>H_DSTBP#3 <9>H_DINV#3 <9>
H_DPRSTP# <9,21,43>H_DPSLP# <21>
H_CPUSLP# <9>
H_DP WR# <9>H_P WRGOOD <6,21>
H_PSI# <43>CPU_BSEL2<17>CPU_BSEL1<17>CPU_BSEL0<17>
+VCCP
+V CCP
+1.5VS
+V CC_CORE +V CC_CORE
+V CC_CORE
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Penryn(2/3)-AGTL+/ITP-XDPCus tom
7 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Close to CPU pin AD26within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
166
200
0 1
CPU_BSEL0
Resistor placed within 0.5"of CPU pin.Trace should beat least 25 mils away fromany other toggling signal.COMP[0,2] trace width is 18mils. COMP[1,3] trace widthis 4 mils.
Length match within 25 mils.The trace width/space/other is 20/7/25.
Close to CPU pin within500mils.
Near pin B26
* Route the TEST3 and TEST5 signals througha ground referenced Zo = 55-ohm trace thatends in a via that is near a GND via and isaccessible through an oscilloscopeconnection.
266
1
10
0 0
0
0
R26
27
.4_
04
02_1
%1
2
C 8
0.0
1U
_0
40
2_16
V7K
1
2
R22 1K_0402_5%@ 1 2
T5
R271K_0402_1%
12
T3
R190_0402_5%1 2
R21 1K_0402_5%@ 1 2
R30 100_0402_1%1 2
T4
R292K_0402_1%
12
+ C 6330U_D2E_2.5VM_R7
1
2
T2
R24
27
.4_
04
02_1
%1
2
C 7
10
U_
08
05
_6.
3V6M
1
2
T6
DA
TA
GR
P 0
DA
TA
GR
P 1
DA
TA
GR
P 2
DA
TA
GR
P 3
MISC
JCPU1B
Penryn
COMP[0] R26
COMP[1] U26
COMP[2] AA1
COMP[3] Y1
D[0]#E22
D[1]#F24
D[10]#J24
D[11]#J23
D[12]#H22
D[13]#F26
D[14]#K22
D[15]#H23
D[16]#N22
D[17]#K25
D[18]#P26
D[19]#R23
D[2]#E26
D[20]#L23
D[21]#M24
D[22]#L22
D[23]#M23
D[24]#P25
D[25]#P23
D[26]#P22
D[27]#T24
D[28]#R24
D[29]#L25
D[3]#G22
D[30]#T25
D[31]#N25
D[32]# Y22
D[33]# AB24
D[34]# V24
D[35]# V26
D[36]# V23
D[37]# T22
D[38]# U25
D[39]# U23
D[4]#F23
D[40]# Y25
D[41]# W22
D[42]# Y23
D[43]# W24
D[44]# W25
D[45]# AA23
D[46]# AA24
D[47]# AB25
D[48]# AE24
D[49]# AD24
D[5]#G25
D[50]# AA21
D[51]# AB22
D[52]# AB21
D[53]# AC26
D[54]# AD20
D[55]# AE22
D[56]# AF23
D[57]# AC25
D[58]# AE21
D[59]# AD21
D[6]#E25
D[60]# AC22
D[61]# AD23
D[62]# AF22
D[63]# AC23
D[7]#E23
D[8]#K24
D[9]#G24
TEST5AF1
DINV[0]#H25
DINV[1]#N24
DINV[2]# U22
DINV[3]# AC20
DPRSTP# E5
DPSLP# B5
DPWR# D24
DSTBN[0]#J26
DSTBN[1]#L26
DSTBN[2]# Y26
DSTBN[3]# AE25
DSTBP[0]#H26
DSTBP[1]#M26
DSTBP[2]# AA26
DSTBP[3]# AF24
GTLREFAD26
PSI# AE6
PWRGOOD D6
SLP# D7
TEST3C24
BSEL[0]B22
BSEL[1]B23
BSEL[2]C21
TEST2D25
TEST4AF26
TEST6A26
TEST1C23
TEST7C3
R23
54
.9_
04
02_1
%1
2
JCP U1C
Penryn .
VCC[001]A7
VCC[002]A9
VCC[003]A10
VCC[004]A12
VCC[005]A13
VCC[006]A15
VCC[007]A17
VCC[008]A18
VCC[009]A20
VCC[010]B7
VCC[011]B9
VCC[012]B10
VCC[013]B12
VCC[014]B14
VCC[015]B15
VCC[016]B17
VCC[017]B18
VCC[018]B20
VCC[019]C9
VCC[020]C10
VCC[021]C12
VCC[022]C13
VCC[023]C15
VCC[024]C17
VCC[025]C18
VCC[026]D9
VCC[027]D10
VCC[028]D12
VCC[029]D14
VCC[030]D15
VCC[031]D17
VCC[032]D18
VCC[033]E7
VCC[034]E9
VCC[035]E10
VCC[036]E12
VCC[037]E13
VCC[038]E15
VCC[039]E17
VCC[040]E18
VCC[041]E20
VCC[042]F7
VCC[043]F9
VCC[044]F10
VCC[045]F12
VCC[046]F14
VCC[047]F15
VCC[048]F17
VCC[049]F18
VCC[050]F20
VCC[051]AA7
VCC[052]AA9
VCC[053]AA10
VCC[054]AA12
VCC[055]AA13
VCC[056]AA15
VCC[057]AA17
VCC[058]AA18
VCC[059]AA20
VCC[060]AB9
VCC[061]AC10
VCC[062]AB10
VCC[063]AB12
VCC[064]AB14
VCC[065]AB15
VCC[066]AB17
VCC[067]AB18
VCC[068] AB20
VCC[069] AB7
VCC[070] AC7
VCC[071] AC9
VCC[072] AC12
VCC[073] AC13
VCC[074] AC15
VCC[075] AC17
VCC[076] AC18
VCC[077] AD7
VCC[078] AD9
VCC[079] AD10
VCC[080] AD12
VCC[081] AD14
VCC[082] AD15
VCC[083] AD17
VCC[084] AD18
VCC[085] AE9
VCC[086] AE10
VCC[087] AE12
VCC[088] AE13
VCC[089] AE15
VCC[090] AE17
VCC[091] AE18
VCC[092] AE20
VCC[093] AF9
VCC[094] AF10
VCC[095] AF12
VCC[096] AF14
VCC[097] AF15
VCC[098] AF17
VCC[099] AF18
VCC[100] AF20
VCCA[01] B26
VCCP[03] J6
VCCP[04] K6
VCCP[05] M6
VCCP[06] J21
VCCP[07] K21
VCCP[08] M21
VCCP[09] N21
VCCP[10] N6
VCCP[11] R21
VCCP[12] R6
VCCP[13] T21
VCCP[14] T6
VCCP[15] V21
VCCP[16] W21
VCCSENSE AF7
VID[0] AD6
VID[1] AF5
VID[2] AE5
VID[3] AF4
VID[4] AE3
VID[5] AF3
VID[6] AE2
VSSSENSE AE7
VCCA[02] C26
VCCP[01] G21
VCCP[02] V6
R28 100_0402_1%1 2
R200_0402_5%1 2
R25
54
.9_
04
02_1
%1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V CC_CORE
+V CC_CORE
+V CC_CORE
+V CC_CORE
+V CCP
+V CC_CORE
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Penryn(3/3)-AGTL+/ITP-XDPCus tom
8 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Inside CPU center cavity in 2 rows
Mid Frequence Decoupling
Place these capacitors onL8 (North side,SecondaryLayer)
ESR <= 1.5m ohmCapacitor > 1980uFNear CPU CORE regulator
5
5
5
5
5
Place these capacitors onL8 (North side,SecondaryLayer)
Place these capacitors onL8 (North side,SecondaryLayer)
Place these capacitors onL8 (North side,SecondaryLayer)
11/21 Change ESR=7m ohm
C26
10U_0805_6.3V6M
1
2
C34
10U_0805_6.3V6M
1
2
+C423
30
U_
D2
_2
VY
_R
7M
@1
2
C19
10U_0805_6.3V6M
1
2
C10
10U_0805_6.3V6M
1
2
C27
10U_0805_6.3V6M
1
2
C15
10U_0805_6.3V6M
1
2
C13
10U_0805_6.3V6M
1
2
C50
0.1U_0402_10V6K
1
2
+C43
33
0U
_D
2_
2V
Y_
R7
M
1
2
C20
10U_0805_6.3V6M
1
2
C23
10U_0805_6.3V6M
1
2
C21
10U_0805_6.3V6M
1
2
C9
10U_0805_6.3V6M
1
2
C12
10U_0805_6.3V6M
1
2
C39
10U_0805_6.3V6M
1
2
C24
10U_0805_6.3V6M
1
2
+C44
33
0U
_D
2_
2V
Y_
R7
M
1
2
C36
10U_0805_6.3V6M
1
2
C35
10U_0805_6.3V6M
1
2
C48
0.1U_0402_10V6K
1
2
C29
10U_0805_6.3V6M
1
2
C46
0.1U_0402_10V6K
1
2
C49
0.1U_0402_10V6K
1
2
C16
10U_0805_6.3V6M
1
2
C32
10U_0805_6.3V6M
1
2
C38
10U_0805_6.3V6M
1
2
C25
10U_0805_6.3V6M
1
2
C28
10U_0805_6.3V6M
1
2
C22
10U_0805_6.3V6M
1
2
C40
10U_0805_6.3V6M
1
2
C11
10U_0805_6.3V6M
1
2
C18
10U_0805_6.3V6M
1
2
C31
10U_0805_6.3V6M
1
2
C47
0.1U_0402_10V6K
1
2
C33
10U_0805_6.3V6M
1
2
C37
10U_0805_6.3V6M
1
2
+C41
33
0U
_D
2_
2V
Y_
R7
M
1
2
C14
10U_0805_6.3V6M
1
2
C30
10U_0805_6.3V6M
1
2
C45
0.1U_0402_10V6K
1
2
C17
10U_0805_6.3V6M
1
2
JCP U1D
P enryn .
VSS[082] P6
VSS[148] AE11
VSS[002]A8
VSS[003]A11
VSS[004]A14
VSS[005]A16
VSS[006]A19
VSS[007]A23
VSS[008]AF2
VSS[009]B6
VSS[010]B8
VSS[011]B11
VSS[012]B13
VSS[013]B16
VSS[014]B19
VSS[015]B21
VSS[016]B24
VSS[017]C5
VSS[018]C8
VSS[019]C11
VSS[020]C14
VSS[021]C16
VSS[022]C19
VSS[023]C2
VSS[024]C22
VSS[025]C25
VSS[026]D1
VSS[027]D4
VSS[028]D8
VSS[029]D11
VSS[030]D13
VSS[031]D16
VSS[032]D19
VSS[033]D23
VSS[034]D26
VSS[035]E3
VSS[036]E6
VSS[037]E8
VSS[038]E11
VSS[039]E14
VSS[040]E16
VSS[041]E19
VSS[042]E21
VSS[043]E24
VSS[044]F5
VSS[045]F8
VSS[046]F11
VSS[047]F13
VSS[048]F16
VSS[049]F19
VSS[050]F2
VSS[051]F22
VSS[052]F25
VSS[053]G4
VSS[054]G1
VSS[055]G23
VSS[056]G26
VSS[057]H3
VSS[058]H6
VSS[059]H21
VSS[060]H24
VSS[061]J2
VSS[062]J5
VSS[063]J22
VSS[064]J25
VSS[065]K1
VSS[066]K4
VSS[067]K23
VSS[068]K26
VSS[069]L3
VSS[070]L6
VSS[071]L21
VSS[072]L24
VSS[073]M2
VSS[074]M5
VSS[075]M22
VSS[076]M25
VSS[077]N1
VSS[078]N4
VSS[079]N23
VSS[080]N26
VSS[081]P3 VSS[162] A25VSS[161] AF21VSS[160] AF19VSS[159] AF16VSS[158] AF13VSS[157] AF11VSS[156] AF8VSS[155] AF6VSS[154] A2VSS[153] AE26VSS[152] AE23VSS[151] AE19
VSS[083] P21
VSS[084] P24
VSS[085] R2
VSS[086] R5
VSS[087] R22
VSS[088] R25
VSS[089] T1
VSS[090] T4
VSS[091] T23
VSS[092] T26
VSS[093] U3
VSS[094] U6
VSS[095] U21
VSS[096] U24
VSS[097] V2
VSS[098] V5
VSS[099] V22
VSS[100] V25
VSS[101] W1
VSS[102] W4
VSS[103] W23
VSS[104] W26
VSS[105] Y3
VSS[107] Y21
VSS[108] Y24
VSS[109] AA2
VSS[110] AA5
VSS[111] AA8
VSS[112] AA11
VSS[113] AA14
VSS[114] AA16
VSS[115] AA19
VSS[116] AA22
VSS[117] AA25
VSS[118] AB1
VSS[119] AB4
VSS[120] AB8
VSS[121] AB11
VSS[122] AB13
VSS[123] AB16
VSS[124] AB19
VSS[125] AB23
VSS[126] AB26
VSS[127] AC3
VSS[128] AC6
VSS[129] AC8
VSS[130] AC11
VSS[131] AC14
VSS[132] AC16
VSS[133] AC19
VSS[134] AC21
VSS[135] AC24
VSS[136] AD2
VSS[137] AD5
VSS[138] AD8
VSS[139] AD11
VSS[140] AD13
VSS[141] AD16
VSS[142] AD19
VSS[143] AD22
VSS[144] AD25
VSS[145] AE1
VSS[146] AE4
VSS[106] Y6
VSS[001]A4
VSS[149] AE14
VSS[150] AE16
VSS[147] AE8
VSS[163] AF25
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_EXTTS#0
V _DDR _MCH_REF
H_R COMP
CLKREQ#_7
+H_ SWNG
H _D#32
H _D#24
H _D#19
H _D#59
H _D#42
H _D#36
H_ D#3
H _D#40
H_R COMP
H _D#55
H_ D#4
H _D#60
H _D#30
H _D#34
H _D#27
H_ D#1
H _D#23
H _D#51
H _D#48
H _D#46
H _D#44
H _D#39
H _D#22
H _D#15H _D#14
H_ D#9
H _D#56
H _D#54
H_ D#8
H_RESET#
H _D#37
H _D#35
H _D#28
H _D#25
H _D#12
H _D#38
H _D#26
H _D#11
H_ D#7
H _D#53H _D#52
H _D#41
H _D#18
H _D#10
+ H_VREF
H _D#57
H _D#33
H _D#29
+H_ SWNG
H_ D#6
H _D#45
H _D#43
H _D#20
H _D#61
H _D#17
H _D#63
H _D#58
H _D#21
H _D#16
H _D#50
H _CPUSLP#
H _D#62
H_ D#5
H _D#49
H _D#31
H_ D#2
H _D#47
H _D#13
H_ D#0
H_A#7
H_A#12
H_A#32
H_A#24
H_A#3
H_A#18
H_A#21
H_A#16
H_A#19
H_A#31
H_A#27
H_A#5
H_A#30
H_A#9
H_A#26
H_A#14
H_A#11
H_A#22H_A#23
H_A#34
H_A#20
H_A#8
H_A#15
H_A#6
H_A#25
H_A#17
H_A#4
H_A#13
H_A#33
H_A#29H_A#28
H_A#10
H_A#35
CLK_MCH_BCLK#
H _LOCK#
C LK_MCH_BCLK
H_ADSTB#1
H_D EFER#
H _HITM#
H _ADS#
H _BR0#
H_ DBSY#
H _HIT#
H_ BPRI#
H_DRDY #
H_B NR#
H_DP WR#
H_ADSTB#0
H_T RDY#
+ H_VREF
H_D INV#0
H_D INV#3
H_D INV#1H_D INV#2
H_DSTBN#1
H_DSTBN#3
H_DSTBN#0
H_DSTBN#2
H_DSTBP#2
H_DSTBP#0
H_DSTBP#3
H_DSTBP#1
H _REQ#0
H _REQ#3
H _REQ#1
H _REQ#4
H _REQ#2
H _RS#1H _RS#0
H _RS#2
MCH_CLKSEL0
SMRCOMP_VOL
+ CL_VREF
HDA _ SDIN2_NB
MCH_ICH _SYNC#CLKREQ#_7
C L_CLK0CL_DATA0
CL_RST#M _PWROK
DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3
DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3
D MI_RXN0D MI_RXN1D MI_RXN2D MI_RXN3
DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3
MCH_ SSCDREFCLKMCH_ SSCDREFCLK#
CLK _MCH_DREFCLK#CLK _ MCH_DREFCLK
CLK_MCH_3GPLL#CLK_MCH_3GPLL
SM_PWROK
TP_SM_DRAMRST#SM_REXT
V _DDR _MCH_REF
M_ CLK_DDR3
M_ CLK_DDR#0M_ CLK_DDR#1M_ CLK_DDR#2M_ CLK_DDR#3
M_ CLK_DDR2
M_ CLK_DDR0M_ CLK_DDR1
S MRCOMP_VOHSMRCOMP_VOL
M_ODT1
SMRCOMP#
M_ODT3
M_ODT0
M_ODT2
S MRCOMP
DDR _CKE0_DIMMADDR _CKE1_DIMMA
DDR _CKE3_DIMMB
DDR _CS1_DIMMA#
DDR _CKE2_DIMMB
DDR _CS0_DIMMA#
DDR _CS3_DIMMB#DDR _CS2_DIMMB#
HDM ICLK_NBHD MIDAT_NB
MCH_CLKSEL1MCH_CLKSEL2
CF G11
CF G9
CF G7
CF G10
CF G6
CF G14
CF G16CF G15
CF G17
CF G8
CF G5
CF G13
CF G18CF G19
CF G12
CF G20
H_DPRSTP#
THERMTRIP#
PM_PWROKPM_EXTTS#1PM_EXTTS#0
PM_BMBUSY#
DP RSLPVR
S MRCOMP_VOH
PLT_RST#
PM_EXTTS#1
TSATN#
V _DDR_MCH_REF<15,16>
H_D#[0..63]<7>
H_CPUSLP#<7>H_RESET#<6>
H_A#[3..35] <6>
H_ADS# <6>
H_ADSTB#1 <6>H_ADSTB#0 <6>
H_BPRI# <6>H_B NR# <6>
H_DEFER# <6>H_BR0# <6>
H_DBSY# <6>CLK_MCH_BCLK <17>CLK_MCH_BCLK# <17>H_DP WR# <7>H_DRDY # <6>H_HIT# <6>H_HITM# <6>H_LOCK# <6>H_T RDY# <6>
H_DINV#0 <7>H_DINV#1 <7>H_DINV#2 <7>H_DINV#3 <7>
H_DSTBN#0 <7>H_DSTBN#1 <7>H_DSTBN#2 <7>H_DSTBN#3 <7>
H_DSTBP#0 <7>H_DSTBP#1 <7>H_DSTBP#2 <7>H_DSTBP#3 <7>
H_REQ#3 <6>H_REQ#2 <6>H_REQ#1 <6>
H_REQ#4 <6>
H_REQ#0 <6>
H_RS#2 <6>H_RS#1 <6>H_RS#0 <6>
MCH_CLKSEL0<17>MCH_CLKSEL1<17>MCH_CLKSEL2<17>
TSATN# <32>
HDA_RST#_NB <21>
HDA _S YNC_NB <21>HDA _SDOUT_NB <21>
MCH_ ICH_SYNC# <22>
CL_CLK0 <22>CL_DATA0 <22>M_PWROK <22,32>CL_RST# <22>
DMI_TXP0 <22>
DMI_RXN0 <22>
DMI_RXP0 <22>
DMI_TXN0 <22>DMI_TXN1 <22>DMI_TXN2 <22>DMI_TXN3 <22>
DMI_TXP1 <22>DMI_TXP2 <22>DMI_TXP3 <22>
DMI_RXN1 <22>DMI_RXN2 <22>DMI_RXN3 <22>
DMI_RXP1 <22>DMI_RXP2 <22>DMI_RXP3 <22>
CLK_MCH_3GPLL <17>CLK_MCH_3GPLL# <17>
MCH_SSCDREFCLK <17>MCH_SSCDREFCLK# <17>
CLK _MCH_DREFCLK <17>CLK _MCH_DREFCLK# <17>
DDR_CKE0_DIMMA <15>DDR_CKE1_DIMMA <15>DDR_CKE2_DIMMB <16>DDR_CKE3_DIMMB <16>
DDR_CS0_DIMMA# <15>DDR_CS1_DIMMA# <15>DDR_CS2_DIMMB# <16>DDR_CS3_DIMMB# <16>
M_CLK_DDR0 <15>M_CLK_DDR1 <15>M_CLK_DDR2 <16>M_CLK_DDR3 <16>
M_CLK_DDR#0 <15>M_CLK_DDR#1 <15>M_CLK_DDR#2 <16>M_CLK_DDR#3 <16>
M_ODT0 <15>M_ODT1 <15>M_ODT2 <16>M_ODT3 <16>
HDMIDAT_NB <35>HDMICLK_NB <35>
CLKREQ#_7 <17>
CF G5<11>
CF G9<11>
CF G11<11>CF G10<11>
CF G6<11>CF G7<11>
CF G13<11>CF G12<11>
CF G16<11>
CF G18<11>
CF G20<11>CF G19<11>
CF G8<11>
CF G14<11>CF G15<11>
CF G17<11>
PM_BMBUSY#<22>H_DPRSTP#<7,21,43>PM_EXTTS#0<15>
DPRSLPVR<22,43>
PM_EXTTS#1<16>PM_PWROK<22,32>
H_THERMTRIP#<6,21>PLT_RST#<20,25,26,27>
HDA_BITCLK_NB <21>
HDA _SDIN2 <21>
+VCCP+V CCP
+3VS
+1.8V
+1.8V
+V CCP
+1.8V
+VCCP
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cantiga(1/6)-AGTL/DMI/DDRCus tom
9 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Layout Note:H_RCOMP / H_VREF / H_SWNGtrace width and spacing is 10/20
Layout Note: V_DDR_MCH_REFtrace width and spacing is 20/20.
Near B3 pinwithin 100 mils from NB
Layout note: Route H_SCOMP and H_SCOMP# with tracewidth, spacing and impedance (55 ohm) same asFSB data traces
0621 add CLK and DAT for DVI
0830 Add pull-up and pull-down resistor.
*R44*Follow Intelfeedback
Follow Design GuideFor Cantiga: 80.6ohm
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
+V_DDR_MCH_REF generated by DC-DC
R39 10K_0402_5%1 2
R52
2K
_0
402
_1%
12
T36
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATION
CLK
DMI
CFG
RSVD
GRAPHICS VID
ME
HDA
U2B
CANTIGA ES_FCBGA1329
SA_CK_0 AP24
SA_CK_1 AT21
SB_CK_0 AV24
SA_CK#_0 AR24
SA_CK#_1 AR21
SB_CK#_0 AU24
SA_CKE_0 BC28
SA_CKE_1 AY28
SB_CKE_0 AY36
SB_CKE_1 BB36
SA_CS#_0 BA17
SA_CS#_1 AY16
SB_CS#_0 AV16
SB_CS#_1 AR13
SM_DRAMRST# BC36
SA_ODT_0 BD17
SA_ODT_1 AY17
SB_ODT_0 BF15
SB_ODT_1 AY13
SM_RCOMP BG22
SM_RCOMP# BH21
CFG_18P29
CFG_19R28
CFG_2P25
CFG_0T25
CFG_1R25
CFG_20T28
CFG_3P20
CFG_4P24
CFG_5C25
CFG_6N24
CFG_7M24
CFG_8E21
CFG_9C23
CFG_10C24
CFG_11N21
CFG_12P21
CFG_13T21
CFG_14R20
CFG_15M20
CFG_16L21
CFG_17H21
PM_SYNC#R29
PM_EXT_TS#_0N33
PM_EXT_TS#_1P32
PWROKAT40
RSTIN#AT11
DPLL_REF_CLK B38
DPLL_REF_CLK# A38
DPLL_REF_SSCLK E41
DPLL_REF_SSCLK# F41
DMI_RXN_0 AE41
DMI_RXN_1 AE37
DMI_RXN_2 AE47
DMI_RXN_3 AH39
DMI_RXP_0 AE40
DMI_RXP_1 AE38
DMI_RXP_2 AE48
DMI_RXP_3 AH40
DMI_TXN_0 AE35
DMI_TXN_1 AE43
DMI_TXN_2 AE46
DMI_TXN_3 AH42
DMI_TXP_0 AD35
DMI_TXP_1 AE44
DMI_TXP_2 AF46
DMI_TXP_3 AH43
RESERVEDAL34
RESERVEDAN35RESERVEDAK34
RESERVEDAM35
RESERVEDBG23
RESERVEDBF23
RESERVEDBH18
RESERVEDBF18
PM_DPRSTP#B7
SB_CK_1 AU20
SB_CK#_1 AV20
RESERVEDAY21
RESERVEDAH9
RESERVEDAH10
RESERVEDAH12
RESERVEDAH13
RESERVEDM36
RESERVEDN36
RESERVEDR33
RESERVEDT33
GFX_VID_0 B33
GFX_VID_1 B32
GFX_VID_2 G33
GFX_VID_3 F33
GFX_VR_EN C34
SM_RCOMP_VOH BF28
SM_RCOMP_VOL BH28
THERMTRIP#T20
DPRSLPVRR32
RESERVEDK12
CL_CLK AH37
CL_DATA AH36
CL_PWROK AN36
CL_RST# AJ35
CL_VREF AH34
NCA47
NCBG48
NCBF48
NCBD48
NCBC48
NCBH47
NCBG47
NCBE47
NCBH46
NCBF46
NCBG45
NCBH44
NCBH43
NCBH6
NCBH5
NCBG4
SDVO_CTRLCLK G36
SDVO_CTRLDATA E36
CLKREQ# K36
RESERVEDT24
ICH_SYNC# H36
TSATN# B12
PEG_CLK# E43PEG_CLK F43
NCBH3
GFX_VID_4 E33
RESERVEDB31
DDPC_CTRLCLK N28
NCBF3
NCBH2
NCBG2
NCBE2
NCBG1
NCBF1
NCBD1
NCBC1
NCF1
SM_VREF AV42
SM_PWROK AR36
SM_REXT BF17
RESERVEDM1
HDA_BCLK B28
HDA_RST# B30
HDA_SDI B29
HDA_SDO C29
HDA_SYNC A28
DDPC_CTRLDATA M28
RESERVEDB2
R47
22
1_
060
3_1% 1
2
T7
T13
T37
T12
R38 10K_0402_5% 1 2
R481K_0402_1%
12
C560.1U_0402_16V4Z
1
2
C55
0.1
U_
04
02
_1
6V4Z
@1
2
R40 10K_0402_5%1 2
T34
C58
0.1
U_
04
02
_16
V4Z 1
2
C5
12
.2U
_0
60
3_
6.3
V4Z
1
2
C5
32
.2U
_0
60
3_
6.3
V4Z
1
2
R420_0402_5%
1 2
R210
33_0402_5%
1 2
R37 499_0402_1%1 2
T35
C57
0.1
U_
04
02
_1
6V4Z
1
2
R311K_0402_1%
12
T15
T29 P AD
T26
T23
T30
R55
10
0_
040
2_1%
12
R35 80.6_0402_1%1 2
T25
T17T16
T22
T31
T14
T28
T9
C5
2
0.0
1U
_0
40
2_25
V7K
1
2
R331K_0402_1%
12
R737 56_0402_5%1 2R46
1K
_0
402
_1%
12
R41100_0402_5%
1 2
T32
R44499_0402_1%
12
T24
T27
C59
0.1
U_
04
02
_16
V4Z
1
2
HOST
U2A
CANTIGA ES_FCBGA1329
H_A#_10 P16
H_A#_11 R16
H_A#_12 N17
H_A#_13 M13
H_A#_14 E17
H_A#_15 P17
H_A#_16 F17
H_A#_17 G20
H_A#_18 B19
H_A#_19 J16
H_A#_20 E20
H_A#_21 H16
H_A#_22 J20
H_A#_23 L17
H_A#_24 A17
H_A#_25 B17
H_A#_26 L16
H_A#_27 C21
H_A#_28 J17
H_A#_29 H20
H_A#_3 A14
H_A#_30 B18
H_A#_31 K17
H_A#_4 C15
H_A#_5 F16
H_A#_6 H13
H_A#_7 C18
H_A#_8 M16
H_A#_9 J13
H_ADS# H12
H_ADSTB#_0 B16
H_ADSTB#_1 G17
H_BNR# A9
H_BPRI# F11
H_BREQ# G12
HPLL_CLK# AH6
H_CPURST#C12
HPLL_CLK AH7
H_D#_0F2
H_REQ#_2 F13
H_REQ#_3 B13
H_D#_1G8
H_D#_10M9
H_D#_20L6
H_D#_30N10
H_D#_40AA8
H_D#_50AA2
H_D#_60AE11
H_D#_8D4
H_D#_9H3
H_DBSY# B10
H_D#_11M11
H_D#_12J1
H_D#_13J2
H_D#_14N12
H_D#_15J6
H_D#_16P2
H_D#_17L2
H_D#_18R2
H_D#_19N9
H_D#_2F8
H_D#_21M5
H_D#_22J3
H_D#_23N2
H_D#_24R1
H_D#_25N5
H_D#_26N6
H_D#_27P13
H_D#_28N8
H_D#_29L7
H_D#_3E6
H_D#_31M3
H_D#_32Y3
H_D#_33AD14
H_D#_34Y6
H_D#_35Y10
H_D#_36Y12
H_D#_37Y14
H_D#_38Y7
H_D#_39W2
H_D#_4G2
H_D#_41Y9
H_D#_42AA13
H_D#_43AA9
H_D#_44AA11
H_D#_45AD11
H_D#_46AD10
H_D#_47AD13
H_D#_48AE12
H_D#_49AE9
H_D#_5H6
H_D#_51AD8
H_D#_52AA3
H_D#_53AD3
H_D#_54AD7
H_D#_55AE14
H_D#_56AF3
H_D#_57AC1
H_D#_58AE3
H_D#_59AC3
H_D#_6H2
H_D#_61AE8
H_D#_62AG2
H_D#_63AD6
H_D#_7F6
H_DEFER# E9
H_DINV#_0 J8
H_DINV#_1 L3
H_DINV#_2 Y13
H_DINV#_3 Y1
H_DPWR# J11
H_DRDY# F9
H_DSTBN#_0 L10
H_DSTBN#_1 M7
H_DSTBN#_2 AA5
H_DSTBN#_3 AE6
H_DSTBP#_0 L9
H_DSTBP#_1 M8
H_DSTBP#_2 AA6
H_DSTBP#_3 AE5
H_AVREFA11
H_DVREFB11
H_TRDY# C9
H_HIT# H9
H_HITM# E12
H_LOCK# H11
H_REQ#_0 B15
H_REQ#_1 K13
H_REQ#_4 B14
H_A#_32 B20
H_A#_33 F21
H_A#_34 K21
H_A#_35 L20
H_SWINGC5
H_CPUSLP#E11
H_RCOMPE3
H_RS#_0 B6
H_RS#_1 F12
H_RS#_2 C8T33
T11
T21
R431K_0402_1%
12
T10
R34 80.6_0402_1%
1 2
R323.01K_0402_1%
12
T8
T19
R54
24
.9_
04
02_1
%
12
T18
R36 0_0402_5%1 2
R451K_0402_1%
12
C5
4
0.0
1U
_0
40
2_2
5V7K
1
2
T20
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
D DR_A_BS0D DR_A_BS1D DR_A_BS2
D DR_A_MA0D DR_A_MA1
D DR_A_MA4
D DR_A_MA2D DR_A_MA3
D DR_A_MA5D DR_A_MA6D DR_A_MA7D DR_A_MA8D DR_A_MA9
DDR_A_MA12DDR_A_MA13
DDR_A_MA11DDR_A_MA10
DDR _A_DQS#0DDR _A_DQS#1
DDR _A_DQS#3DDR _A_DQS#2
DDR _A_DQS#5DDR _A_DQS#4
DDR _A_DQS#6DDR _A_DQS#7
DDR _A_DQS0DDR _A_DQS1DDR _A_DQS2DDR _A_DQS3DDR _A_DQS4DDR _A_DQS5DDR _A_DQS6DDR _A_DQS7
DDR _A_DM7
DDR _A_DM5
DDR _A_DM2DDR _A_DM1
DDR _A_DM6
DDR _A_DM4
DDR _A_DM0
DDR _A_DM3
DD R_A_CAS#DD R_A_RAS#
DDR _A_WE#
DDR _A_D63DDR _A_D62DDR _A_D61DDR _A_D60DDR _A_D59DDR _A_D58DDR _A_D57DDR _A_D56DDR _A_D55DDR _A_D54
DDR _A_D51DDR _A_D50DDR _A_D49DDR _A_D48
DDR _A_D53DDR _A_D52
DDR _A_D47DDR _A_D46
DDR _A_D43DDR _A_D42DDR _A_D41DDR _A_D40
DDR _A_D45DDR _A_D44
DDR _A_D39DDR _A_D38
DDR _A_D35DDR _A_D34DDR _A_D33DDR _A_D32
DDR _A_D37DDR _A_D36
DDR _A_D31DDR _A_D30
DDR _A_D27DDR _A_D26DDR _A_D25DDR _A_D24
DDR _A_D15DDR _A_D14
DDR _A_D11DDR _A_D10DDR_ A_D9
DDR _A_D13DDR _A_D12
DDR _A_D29DDR _A_D28
DDR _A_D23DDR _A_D22
DDR _A_D19DDR _A_D18DDR _A_D17DDR _A_D16
DDR _A_D21DDR _A_D20
DDR_ A_D8
DDR_ A_D5DDR_ A_D4DDR_ A_D3
DDR_ A_D7DDR_ A_D6
DDR_ A_D2DDR_ A_D1DDR_ A_D0
DDR_A_MA14
DD R_B_RAS#
DDR_B_MA14
DDR_B_MA10
DDR _B_DQS#7
DDR _B_DQS#2
DDR _B_DQS7
DDR _B_DQS2
DDR _B_DM3
DDR _B_D51
DDR _B_D39
DDR _B_D18
D DR_B_MA7
DDR _B_DQS0
DDR_ B_D7
DDR _B_D54
DDR_ B_D4
DDR _B_D36
DDR _B_D21
D DR_B_MA4
DDR _B_DM0
DDR _B_D62
DDR _B_D34
DDR _B_D19
DDR _B_D13
D DR_B_MA5
DDR_B_MA11
D DR_B_BS2
DDR _B_D42
DDR _B_D35
DDR _B_D31
DDR _B_D24
DDR _B_D15
D DR_B_MA3
DDR _B_DQS#6
DDR _B_DM7
DDR _B_D50
DDR _B_D38
DDR _B_D32
DDR _B_D23
D DR_B_MA6
DDR_ B_D6
DDR _B_D53
DDR _B_D33
DDR_ B_D3
DDR _B_D20
DDR _B_DQS#5
D DR_B_BS1
DDR _B_D61
DDR _B_D59
DDR _B_D46
DDR _B_D12
DDR _B_DQS3
DDR _B_D47
DDR _B_D30
DDR _B_D14
D DR_B_MA0
DDR _B_DQS#0
DDR _B_DM6
DDR _B_DM4
DDR _B_D55
DDR _B_D44
DDR _B_D29
DDR _B_D27
DDR _B_D22
DDR_B_MA13
D DR_B_MA1
DDR _B_D57
DDR _B_D52
DDR_ B_D2
DDR _B_D17
DDR _B_DQS#1
DDR _B_DQS1
DDR_ B_D9
DDR _B_D60
DDR _B_D58
DDR _B_D45
DDR _B_DQS4
D DR_B_MA9
DDR _B_DQS#4
DDR _B_DM5
DDR _B_DM2
DDR _B_D49
DDR _B_D41
DDR _B_D28
DDR _B_D11
DDR _B_WE#
DDR_B_MA12
DDR _B_D56
DDR _B_D48
DDR _B_D16
DDR_ B_D1
D DR_B_MA2
DDR _B_DQS5
DDR_ B_D8
DDR _B_D63
DDR _B_D37
DDR_ B_D0 DDR_B_BS0
DDR_ B_D5
D DR_B_MA8
DDR _B_DQS#3
DDR _B_DQS6
DDR _B_DM1
DD R_B_CAS#
DDR _B_D43
DDR _B_D40
DDR _B_D26DDR _B_D25
DDR _B_D10
DDR_A_BS0 <15>DDR_A_BS1 <15>DDR_A_BS2 <15>
DDR_A _D[0..63]<15>
DDR_A_MA[0..14] <15>
DDR_A _DQS#[0..7] <15>
DDR_A _DQS[0..7] <15>
DDR_A _DM[0..7] <15>
DDR_A_CAS# <15>DDR_A_RAS# <15>
DDR_A_WE# <15>
DDR_B _D[0..63]<16>
DDR_B_BS0 <16>DDR_B_BS1 <16>DDR_B_BS2 <16>
DDR_B_CAS# <16>DDR_B_RAS# <16>
DDR_B_WE# <16>
DDR_B _DM[0..7] <16>
DDR_B _DQS[0..7] <16>
DDR_B _DQS#[0..7] <16>
DDR_B_MA[0..14] <16>
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cantiga(2/6)-DDR2 A/B CHCus tom
10 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
DDR SYSTEM MEMORY B
U2E
CANTIGA ES_FCBGA1329
SB_DQ_0AK47
SB_DQ_1AH46
SB_DQ_10BA48
SB_DQ_11AY48
SB_DQ_12AT47
SB_DQ_13AR47
SB_DQ_14BA47
SB_DQ_15BC47
SB_DQ_16BC46
SB_DQ_17BC44
SB_DQ_18BG43
SB_DQ_19BF43
SB_DQ_2AP47
SB_DQ_20BE45
SB_DQ_21BC41
SB_DQ_22BF40
SB_DQ_23BF41
SB_DQ_24BG38
SB_DQ_25BF38
SB_DQ_26BH35
SB_DQ_27BG35
SB_DQ_28BH40
SB_DQ_29BG39
SB_DQ_3AP46
SB_DQ_30BG34
SB_DQ_31BH34
SB_DQ_32BH14
SB_DQ_33BG12
SB_DQ_34BH11
SB_DQ_35BG8
SB_DQ_36BH12
SB_DQ_37BF11
SB_DQ_38BF8
SB_DQ_39BG7
SB_DQ_4AJ46
SB_DQ_40BC5
SB_DQ_41BC6
SB_DQ_42AY3
SB_DQ_43AY1
SB_DQ_44BF6
SB_DQ_45BF5
SB_DQ_46BA1
SB_DQ_47BD3
SB_DQ_48AV2
SB_DQ_49AU3
SB_DQ_5AJ48
SB_DQ_50AR3
SB_DQ_51AN2
SB_DQ_52AY2
SB_DQ_53AV1
SB_DQ_54AP3
SB_DQ_55AR1
SB_DQ_56AL1
SB_DQ_57AL2
SB_DQ_58AJ1
SB_DQ_59AH1
SB_DQ_6AM48
SB_DQ_60AM2
SB_DQ_61AM3
SB_DQ_62AH3
SB_DQ_63AJ3
SB_DQ_7AP48
SB_DQ_8AU47
SB_DQ_9AU46
SB_BS_0 BC16
SB_BS_1 BB17
SB_BS_2 BB33
SB_CAS# BG16
SB_DM_0 AM47
SB_DM_1 AY47
SB_DM_2 BD40
SB_DM_3 BF35
SB_DM_4 BG11
SB_DM_5 BA3
SB_DM_6 AP1
SB_DM_7 AK2
SB_DQS_0 AL47
SB_DQS_1 AV48
SB_DQS_2 BG41
SB_DQS_3 BG37
SB_DQS_4 BH9
SB_DQS_5 BB2
SB_DQS_6 AU1
SB_DQS_7 AN6
SB_DQS#_0 AL46
SB_DQS#_1 AV47
SB_DQS#_2 BH41
SB_DQS#_3 BH37
SB_DQS#_4 BG9
SB_DQS#_5 BC2
SB_DQS#_6 AT2
SB_DQS#_7 AN5
SB_MA_0 AV17
SB_MA_1 BA25
SB_MA_10 BB16
SB_MA_11 AW33
SB_MA_12 AY33
SB_MA_13 BH15
SB_MA_2 BC25
SB_MA_3 AU25
SB_MA_4 AW25
SB_MA_5 BB28
SB_MA_6 AU28
SB_MA_7 AW28
SB_MA_8 AT33
SB_MA_9 BD33
SB_MA_14 AU33
SB_RAS# AU17
SB_WE# BF14
DDR SYSTEM MEMORY A
U 2D
CANTIGA ES_FCBGA1329
SA_DQ_0AJ38
SA_DQ_1AJ41
SA_DQ_10AU40
SA_DQ_11AT38
SA_DQ_12AN41
SA_DQ_13AN39
SA_DQ_14AU44
SA_DQ_15AU42
SA_DQ_16AV39
SA_DQ_17AY44
SA_DQ_18BA40
SA_DQ_19BD43
SA_DQ_2AN38
SA_DQ_20AV41
SA_DQ_21AY43
SA_DQ_22BB41
SA_DQ_23BC40
SA_DQ_24AY37
SA_DQ_25BD38
SA_DQ_26AV37
SA_DQ_27AT36
SA_DQ_28AY38
SA_DQ_29BB38
SA_DQ_3AM38
SA_DQ_30AV36
SA_DQ_31AW36
SA_DQ_32BD13
SA_DQ_33AU11
SA_DQ_34BC11
SA_DQ_35BA12
SA_DQ_36AU13
SA_DQ_37AV13
SA_DQ_38BD12
SA_DQ_39BC12
SA_DQ_4AJ36
SA_DQ_40BB9
SA_DQ_41BA9
SA_DQ_42AU10
SA_DQ_43AV9
SA_DQ_44BA11
SA_DQ_45BD9
SA_DQ_46AY8
SA_DQ_47BA6
SA_DQ_48AV5
SA_DQ_49AV7
SA_DQ_5AJ40
SA_DQ_50AT9
SA_DQ_51AN8
SA_DQ_52AU5
SA_DQ_53AU6
SA_DQ_54AT5
SA_DQ_55AN10
SA_DQ_56AM11
SA_DQ_57AM5
SA_DQ_58AJ9
SA_DQ_59AJ8
SA_DQ_6AM44
SA_DQ_60AN12
SA_DQ_61AM13
SA_DQ_62AJ11
SA_DQ_63AJ12
SA_DQ_7AM42
SA_DQ_8AN43
SA_DQ_9AN44
SA_BS_0 BD21
SA_BS_1 BG18
SA_BS_2 AT25
SA_CAS# BD20
SA_DM_0 AM37
SA_DM_1 AT41
SA_DM_2 AY41
SA_DM_3 AU39
SA_DM_4 BB12
SA_DM_5 AY6
SA_DM_6 AT7
SA_DQS_0 AJ44
SA_DQS_1 AT44
SA_DQS_2 BA43
SA_DQS_3 BC37
SA_DQS_4 AW12
SA_DQS_5 BC8
SA_DQS_6 AU8
SA_DQS_7 AM7
SA_DM_7 AJ5
SA_DQS#_0 AJ43
SA_DQS#_1 AT43
SA_DQS#_2 BA44
SA_DQS#_3 BD37
SA_DQS#_4 AY12
SA_DQS#_5 BD8
SA_DQS#_6 AU9
SA_DQS#_7 AM8
SA_MA_0 BA21
SA_MA_1 BC24
SA_MA_10 BC21
SA_MA_11 BG26
SA_MA_12 BH26
SA_MA_13 BH17
SA_MA_2 BG24
SA_MA_3 BH24
SA_MA_4 BG25
SA_MA_5 BA24
SA_MA_6 BD24
SA_MA_7 BG27
SA_MA_8 BF25
SA_MA_9 AW24
SA_RAS# BB20
SA_WE# AY20
SA_MA_14 AY25
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CF G5
TMDS_B_HPD#
V S Y NCCRT _ VSYNC
H S Y NC
3V DD CCL3V DD CDA
M _REDM _GREEN
CRT _HS YNC
TV_COMPSTV_LUMATV_CRMA
M_BLUE
LVDS_B1+LVDS_B2+
LVDS_B0+
LVDS_B3+
LVDS_B1-LVDS_B0-
LVDS_B2-LVDS_B3-
LVDS_A1+LVDS_A2+
LVDS_A0+
LVDS_A3+
LVDS_A0-
LVDS_A2-LVDS_A1-
LVDS_A3-
LVDS_BCLK+LVDS_BCLK-LVDS_ACLK+LVDS_ACLK-
E NA VDD
DDC2 _CLKDD C2_DATA
ENBKL
LVDS_ACLK+
LVDS_ACLK-
LVDS_A0-
LVDS_A0+
LVDS_A1-
LVDS_A1+
LVDS_A2+
LVDS_A2-
TMDS_BDATA1#TMDS_BDATA2#
TMDS_BDATA0#TMDS_BCLK#
TMDS_BDATA2
TMDS_BDATA0TMDS_BCLK
TMDS_BDATA1
ENBKL
CF G5<9>
CRT _VSYNC<18>
3V DDCDA<18>CRT _HS YNC<18>
3V DDCCL<18>
E NA VDD<19>
DDC2_CLK<19>DDC2_DATA<19>
ENBKL<32>
M_BLUE<18>M_GREEN<18>M_RED<18>
TMDS_B_HPD# <35>
LVDS_A0+<19>
LVDS_A1+<19>
LVDS_A2+<19>
LVDS_A0-<19>
LVDS_A1-<19>
LVDS_A2-<19>
LVDS_ACLK-<19>
LVDS_ACLK+<19>
CF G6<9>
CF G7<9>
CF G8<9>
CF G9<9>
CF G10<9>
CF G11<9>
CF G12<9>
CF G13<9>
CF G14<9>
CF G15<9>
CF G17<9>
CF G18<9>
CF G16<9>
CF G19<9>
CF G20<9>
TMDS_B_CLK <35>
TMDS_B_CLK# <35>
TMDS_B_DATA0 <35>
TMDS_B_DATA0# <35>
TMDS_B_DATA1 <35>
TMDS_B_DATA1# <35>
TMDS_B_DATA2 <35>
TMDS_B_DATA2# <35>
+VCC_PEG
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cantiga(3/6)-VGA/LVDS/TVCus tom
11 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
PEGCOMP trace widthand spacing is 20/25 mils.
000 = FSB 1066MHz
CFG[4:3] Reserved
CFG60 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable *
Reserved
CFG10
(Default)11 = Normal Operation10 = All Z Mode Enabled
00 = Reserved01 = XOR Mode Enabled
*
0 = Enable
1 = Disable *
CFG9 (PCIE GraphicsLane Reversal)
CFG[2:0] FSB Freqselect
Reserved
ReservedCFG[15:14]
Strap Pin Table
ReservedCFG[18:17]
(Lane number in Order)
Others = Reserved011 = FSB 667MHz010 = FSB 800MHz
*
1 = Reverse Lane
0 = Reverse Lane,15->0, 14->1
1 = Enabled
0 = Normal Operation
0 = Disabled
*
0 = DMI x 2
*
*
*
1 = PCIE/SDVO are operating simu.
0 = Only PCIE or SDVO is operational. *
1 = Normal Operation,Lane Number inorder
1 = DMI x 4
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
CFG5 (DMI select)
CFG19 (DMI Lane Reversal)
CFG16 (FSB Dynamic ODT)
CFG7
CFG20
CFG11
CFG[13:12] (XOR/ALLZ)
CFG8
Follow Intel DG &Checklist
Solve 3G WWAN issue
(Intel ManagementEngine Crypto strap)
(PCIELookbackenable)
(PCIE/SDVOconcurrent)
Follow Intel DG &Checklist
Follow Intel DG &Checklist
11/10 Disable TV out
T38
T39
R62
75
_0
402_1%
12
R67
15
0_
04
02_1%
12
T40
R714.02K_0402_1%
12
T75
C274 0.1U_0402_10V7K1 2
R58 10K_0402_5%1 2
R842.21K_0402_1%
@ 1 2
R872.21K_0402_1%
@ 1 2
T41
R862.21K_0402_1%
@ 1 2
C620.1U_0402_10V6K
@1
2
T80
T48
R61
75
_0
402_1%
12
R63
75
_0
402_1%
12
C275 0.1U_0402_10V7K1 2
R59 10K_0402_5%1 2
T77
R734.02K_0402_1%
@ 1 2
C276 0.1U_0402_10V7K1 2
R66
15
0_
04
02_1%
12
R60 2.37K_0402_1%1 2
R792.21K_0402_1%
@ 1 2
T81
R802.21K_0402_1%
@ 1 2
T49
R822.21K_0402_1%
@ 1 2
R852.21K_0402_1%
@ 1 2
C277 0.1U_0402_10V7K1 2
T79
R772.21K_0402_1%1 2
R724.02K_0402_1%
1 2
C630.1U_0402_10V6K
@1
2
LVDS
PCI-EXPRESS GRAPHICS
TV
VGA
U 2C
CANTIGA ES_FCBGA1329
PEG_COMPI T37
PEG_COMPO T36
PEG_RX#_0 H44
PEG_RX#_1 J46
PEG_RX#_2 L44
PEG_RX#_3 L40
PEG_RX#_4 N41
PEG_RX#_5 P48
PEG_RX#_6 N44
PEG_RX#_7 T43
PEG_RX#_8 U43
PEG_RX#_9 Y43
PEG_RX#_10 Y48
PEG_RX#_11 Y36
PEG_RX#_12 AA43
PEG_RX#_13 AD37
PEG_RX#_14 AC47
PEG_RX#_15 AD39
PEG_RX_0 H43
PEG_RX_1 J44
PEG_RX_2 L43
PEG_RX_3 L41
PEG_RX_4 N40
PEG_RX_5 P47
PEG_RX_6 N43
PEG_RX_7 T42
PEG_RX_8 U42
PEG_RX_9 Y42
PEG_RX_10 W47
PEG_RX_11 Y37
PEG_RX_12 AA42
PEG_RX_13 AD36
PEG_RX_14 AC48
PEG_RX_15 AD40
PEG_TX#_0 J41
PEG_TX#_10 Y40
PEG_TX#_3 M40
PEG_TX#_4 M42
PEG_TX#_5 R48
PEG_TX#_6 N38
PEG_TX#_7 T40
PEG_TX#_8 U37
PEG_TX#_9 U40
PEG_TX#_1 M46
PEG_TX#_11 AA46
PEG_TX#_12 AA37
PEG_TX#_13 AA40
PEG_TX#_14 AD43
PEG_TX#_15 AC46
PEG_TX#_2 M47
PEG_TX_0 J42
PEG_TX_1 L46
PEG_TX_2 M48
PEG_TX_3 M39
PEG_TX_4 M43
PEG_TX_5 R47
PEG_TX_6 N37
PEG_TX_7 T39
PEG_TX_8 U36
PEG_TX_9 U39
PEG_TX_10 Y39
PEG_TX_11 Y46
PEG_TX_12 AA36
PEG_TX_13 AA39
PEG_TX_14 AD42
PEG_TX_15 AD46
L_CTRL_CLKM32
L_CTRL_DATAM33
L_DDC_CLKK33
L_DDC_DATAJ33
L_VDD_ENM29
LVDS_IBGC44
LVDS_VBGB43
LVDS_VREFHE37
LVDS_VREFLE38
LVDSA_CLK#C41
LVDSA_CLKC40
LVDSA_DATA#_0H47
LVDSA_DATA#_1E46
LVDSA_DATA#_2G40
LVDSA_DATA_1D45
LVDSA_DATA_2F40
LVDSB_CLK#B37
LVDSB_CLKA37
LVDSB_DATA#_0A41
LVDSB_DATA#_1H38
LVDSB_DATA#_2G37
LVDSB_DATA_1G38
LVDSB_DATA_2F37
L_BKLT_ENG32
TVA_DACF25
TVB_DACH25
TVC_DACK25
TV_RTNH24
CRT_BLUEE28
CRT_DDC_CLKH32
CRT_DDC_DATAJ32
CRT_GREENG28
CRT_HSYNCJ29
CRT_TVO_IREFE29
CRT_REDJ28
CRT_IRTNG29
CRT_VSYNCL29
LVDSA_DATA_0H48
LVDSB_DATA_0B42
L_BKLT_CTRLL32
TV_DCONSEL_0C31
TV_DCONSEL_1E32
LVDSA_DATA#_3A40
LVDSA_DATA_3B40
LVDSB_DATA#_3J37
LVDSB_DATA_3K37
T72
C278 0.1U_0402_10V7K1 2
T50
R6830.1_0402_1%
1 2
R65
15
0_
04
02_1%
12
R762.21K_0402_1%
@ 1 2
C279 0.1U_0402_10V7K1 2
R406 0_0402_5%1 2
C600.1U_0402_10V6K
@1
2
R812.21K_0402_1%1 2
T73
R64 2.2K_0402_5%@ 1 2
R701.02K_0402_1%
12
R742.21K_0402_1%
@ 12
R832.21K_0402_1%
@ 1 2
C280 0.1U_0402_10V7K1 2
R782.21K_0402_1%1 2
R6930.1_0402_1%
1 2
C610.1U_0402_10V6K
@1
2
R754.02K_0402_1%
@ 1 2
T74
C281 0.1U_0402_10V7K1 2
R148
100K_0402_5%
1 2
R57
49.9_0402_1%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS_A_SM
+1.05VS_A_SM_CK
+1.8V_TXLVDS
+3VS+3VS_DAC_BG
+3VS_DAC_CRT
+3VS+3VS_TVDAC
+1.8V_TXLVDS
+1.8V
+1.05VS_HPLL
+1.05VS_MPLL
+VCCP
+1.05VS_PEGPLL +VCCP
+VCCP+V1.05VS_AXF
+VCCP+1.05VS_DMI
+1.8V+1.8V_SM_CK
+1.05VS_DPLLA+VCCP
+1.5VS+1.5VS_TVDAC
+VCC_PEG
+VCCP
+1.8V
+1.8V_LVDS
+1.5VS_PEG_BG
+1.5VS
+1.05VS_PEGPLL
+VCCP+1.05VS_DPLLB
+VCCP
+VCCP
+VCCP
+3VS
+VCCP_D
+3VS_HV
+VCCP
+3VS
+3VS
+1.5VS+1.5VS_QDAC
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_MPLL
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_DPLLA
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_PEGPLL
+1.05VS_HPLL
+1.8V_LVDS
+1.05VS_DMI
+VCC_PEG
+3VS_HV+1.8V_TXLVDS
+1.8V_SM_CK
+V1.05VS_AXF
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
M o n tev ina Blade UMA LA4101P 0.3
Cantiga(4/6)-PWRCustom
12 46Saturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
40 mils
73mA
2.68mA
852mA
64.8mA
720mA
24mA
139.2mA
50mA
414uA
13.2mA
64.8mA
26mA
321.35mA
118.8mA
124mA
105.3mA
1732mA
456mA
TVA 24.15mATVB 39.48mATVX 24.15mA
26mA
50mA
58.67mA
48.363mA
157.2mA
50mA
60.31mA
**RED Mark: Means UMA & dis@ Power select**~It check by INTEL Graphics DisableGuidelines~
Check Again!!!
C7
8
10
U_
08
05
_1
0V
4Z
1
2
C97
1U_0603_10V4Z
1
2
R97
0_0603_5%
1 2
C1
08
10
U_
08
05
_1
0V
4Z
1
2
C1
09
0.1
U_
04
02
_1
6V
4Z
1
2
C8
1
4.7
U_
08
05
_1
0V
4Z
1
2
C7
0
10
U_
08
05
_1
0V
4Z
1
2
C1
14
1U
_0
60
3_
10
V4
Z
1
2
C9
0
0.1
U_
04
02
_1
6V
4Z
1
2
R103
0_0603_5%
1 2
POWER
CRT
PLL
A PEG
A SM
TV
D TV/CRT
LVDS
VTTLF
PEG
SM CK
AXF
VTT
DMI
HV
A CK
A LVDS
HDA
U2H
CANTIGA ES_FCBGA1329
VTT V3
VTT U3
VTT V2
VTT U2
VCCA_PEG_BGAD48
VCCA_PEG_PLLAA48
VCCA_CRT_DACB27
VCCA_CRT_DACA26
VCCA_DPLLAF47
VCCA_DPLLBL48
VCCA_HPLLAD1
VCCA_LVDSJ48
VCCA_MPLLAE1
VCCA_TV_DACB24
VCCA_TV_DACA24
VCCD_PEG_PLLAA47
VTT U6
VTT T6
VTT U5
VTT T5
VTT T8
VTT U7
VTT T7
VCCD_HPLLAF1
VTT U13
VTT T13
VTT T12
VTT U11
VTT T11
VTT U10
VTT T10
VTT U9
VTT T9
VTT U8
VTT U12
VCCA_SM_CKAP28
VCCA_SM_CKAN28
VCCA_DAC_BGA25
VCCD_TVDACM25
VTTLF A8
VTTLF L1
VTTLF AB2
VCC_DMI AH48
VCC_DMI AF48
VCC_SM_CK BF21
VCC_SM_CK BH20
VCC_SM_CK BG20
VCC_SM_CK BF20
VCCD_LVDSM38
VCCD_QDACL28
VCC_AXF B22
VCC_AXF B21
VCC_AXF A21
VCCA_SMAR20
VCCA_SMAP20
VCCA_SMAN20
VCCA_SMAR17
VCCA_SMAP17
VCCA_SMAT16
VCCA_SMAR16
VCCA_SMAP16
VCC_TX_LVDS K47
VSSA_LVDSJ47
VCC_HV C35
VCC_HV B35
VCC_PEG V48
VCCD_LVDSL37
VCC_PEG U48
VCC_PEG V47
VCC_PEG U47
VCC_PEG U46
VCCA_SMAN17
VCCA_SM_CKAP25
VCCA_SM_CKAN25
VCCA_SM_CKAN24
VCCA_SM_CK_NCTFAM28
VCCA_SM_CK_NCTFAM26
VCCA_SM_CK_NCTFAM25
VCCA_SM_CK_NCTFAL25
VCCA_SM_CK_NCTFAM24
VCCA_SM_CK_NCTFAL24
VCCA_SM_CK_NCTFAM23
VTT T2
VTT V1
VTT U1
VCC_HV A35
VCC_DMI AH47
VCC_DMI AG47
VSSA_DAC_BGB25
VCCA_SM_CK_NCTFAL23
VCC_HDAA32
C7
9
1U
_0
60
3_
10
V4
Z
1
2
R93
0_0603_5%
1 2
C88
1000P_0402_50V7K
1
2
R9
2
0_
06
03
_5
%
@
12
C89
0.1U_0402_16V4Z
1
2
C6
8
0.0
22
U_
04
02
_1
6V
7K
1
2
C6
9
0.1
U_
04
02
_1
6V
4Z
1
2
R88
BLM18PG181SN1D_06031 2
R108
0_0603_5%1 2
+
C7
1
22
0U
_6
.3V
_M
1
2
C9
1
10
U_
08
05
_1
0V
4Z
1
2
C8
6
0.1
U_
04
02
_1
6V
4Z
1
2
C1
11
0.4
7U
_0
60
3_
10
V7
K
1
2
R112
100_0603_1%1 2
R91
BLM18PG181SN1D_06031 2
C1
04
1U
_0
60
3_
10
V4
Z
1
2
R1
09
0_
06
03
_5
%
@
12
C8
4
10
U_
08
05
_1
0V
4Z
1
2
R104
0_0603_5%
1 2
C9
5
10
U_
08
05
_1
0V
4Z
1
2
R95
0_0805_5%
1 2
R105
10_0402_5%
1 2
R107
0_0603_5%1 2
C99
0.1U_0402_16V4Z
1
2
C1
10
0.4
7U
_0
60
3_
10
V7
K
1
2
C7
5
0.0
22
U_
04
02
_1
6V
7K
1
2
+C9
8
22
0U
_D
2_
4V
M
1
2
C1
13
10
U_
08
05
_1
0V
4Z
1
2
C1
01
10
U_
08
05
_1
0V
4Z
1
2
C96
4.7U_0805_10V4Z
1
2
C8
3
10
U_
08
05
_1
0V
4Z
@ 1
2
C1
12
0.4
7U
_0
60
3_
10
V7
K
1
2
C1
07
0.1
U_
04
02
_1
6V
4Z
1
2
C7
4
10
U_
08
05
_1
0V
4Z
1
2
C1
20
0.1
U_
04
02
_1
6V
4Z
1
2
+
C7
7
22
0U
_D
2_
4V
M
@1
2
C8
2
2.2
U_
08
05
_1
6V
4Z
1
2
R94
10U_FLC-453232-100K_0.25A_10%1 2
R1
14
0_
06
03
_5
%
@ 12
C7
3
0.1
U_
04
02
_1
6V
4Z
1
2
R98
MBK2012121YZF_08051 2
+
C9
4
220U_D2_4VM
1
2
R96
0_0603_5%
@ 1 2
C100
10U_0805_10V4Z
1
2
R1
13
0_
06
03
_5
%
@ 12
C1
06
0.1
U_
04
02
_1
6V
4Z
1
2
C1
17
0.0
22
U_
04
02
_1
6V
7K
1
2
C1
18
0.1
U_
04
02
_1
6V
4Z
1
2
R106
0_0402_5%
1 2
C9
2
0.0
22
U_
04
02
_1
6V
7K
1
2
R99
0_0805_5%
1 2
+
C1
21
22
0U
_D
2_
4V
M
@1
2
C1
16
1000P
_0
40
2_
50
V7
K
1
2
C7
6
0.1
U_
04
02
_1
6V
4Z
1
2
C1
03
10
U_
08
05
_1
0V
4Z
1
2
C102
1U_0603_10V4Z
1
2
C8
5
0.1
U_
04
02
_1
6V
4Z
1
2
R100
0_0805_5%
1 2R
11
0
0_
06
03
_5
%
@
12
C7
2
4.7
U_
08
05
_1
0V
4Z
1
2
C8
0
0.4
7U
_0
60
3_
10
V7
K
1
2
R9010U_FLC-453232-100K_0.25A_10%
1 2
C9
3
0.1
U_
04
02
_1
6V
4Z
1
2
C8
7
10
U_
08
05
_1
0V
4Z
1
2
+
C1
15
22
0U
_D
2_
4V
M
@1
2
R101
MBK2012121YZF_0805
1 2
R111
BLM18PG181SN1D_06031 2
L1
BLM18PG121SN1D_06031 2
C1
05
0.1
U_
04
02
_1
6V
4Z
1
2
R102
0_0805_5%1 2
C1
19
0.0
22
U_
04
02
_1
6V
7K
1
2
R8
9
0_
06
03
_5
%
@ 12
D 3
CH751H-40PT_SOD323-2
2 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSM_LF2VCCSM_LF3
VCCSM_LF1
VCCSM_LF6VCCSM_LF7
VCCSM_LF4VCCSM_LF5
+VCCP
+V CCP
+V CCP
+VCCP
+1.8V
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cantiga(5/6)-PWR/GNDCus tom
13 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
3000mA
6326.84mA
Extnal Graphic: 1210.34mAintegrated Graphic: 1930.4mA
0317 change value
T42P AD
C129
4.7U_0603_6.3V6M
1
2
+ C135
33
0U
_D
2E
_2
.5V
M_R
7
1
2
C1
33
0.2
2U
_0
40
2_
10V4Z
1
2
C1
32
0.2
2U
_0
40
2_
10V4Z
1
2
+
C1
26
33
0U
_D
2E
_2
.5V
M_R
7
1
2
C1
41
0.2
2U
_0
60
3_10V
7K
1
2
C127
0.1U_0402_16V4Z
1
2
C1
44
1U
_0
60
3_
10V
4Z
1
2
C128
0.22U_0402_10V4Z
1
2
C1
30
10
U_
08
05
_10V4Z
1
2
POWER
VCC SM
VCC GFX
VCC GFX NCTF
VCC SM LF
U2G
CANTIGA ES_FCBGA1329
VCC_SMAY32
VCC_SMBF31
VCC_SMAW29
VCC_SMBD32
VCC_SMBC32
VCC_SMBB32
VCC_SMBA32
VCC_SMAW32
VCC_SMAV32
VCC_SMAU32
VCC_SMAT32
VCC_SMAR32
VCC_SMAP32
VCC_SMAN32
VCC_SMBH31
VCC_SMBG31
VCC_SMAN33
VCC_SMBG30
VCC_SMBH29
VCC_SMBG29
VCC_SMBF29
VCC_SMBD29
VCC_SMBC29
VCC_SMBB29
VCC_SMBA29
VCC_SMAY29
VCC_SMBH32
VCC_SMAV29
VCC_SMAU29
VCC_SMAT29
VCC_SMAR29
VCC_AXG_NCTF V23
VCC_AXG_NCTF AM21
VCC_AXG_NCTF AL21
VCC_AXG_NCTF AK21
VCC_AXG_NCTF W21
VCC_AXG_NCTF V21
VCC_AXG_NCTF U21
VCC_AXG_NCTF AM20
VCC_AXG_NCTF AK20
VCC_AXG_NCTF W20
VCC_AXG_NCTF V28
VCC_AXG_NCTF U20
VCC_AXG_NCTF AM19
VCC_AXG_NCTF AL19
VCC_AXG_NCTF AK19
VCC_AXG_NCTF AJ19
VCC_AXG_NCTF AH19
VCC_AXG_NCTF AG19
VCC_AXG_NCTF AF19
VCC_AXG_NCTF AE19
VCC_AXG_NCTF AB19
VCC_AXG_NCTF W26
VCC_AXG_NCTF AA19
VCC_AXG_NCTF Y19
VCC_AXG_NCTF W19
VCC_AXG_NCTF V19
VCC_AXG_NCTF U19
VCC_AXG_NCTF AM17
VCC_AXG_NCTF AK17
VCC_AXG_NCTF AH17
VCC_AXG_NCTF AG17
VCC_AXG_NCTF AF17
VCC_AXG_NCTF V26
VCC_AXG_NCTF AE17
VCC_AXG_NCTF AC17
VCC_AXG_NCTF AB17
VCC_AXG_NCTF Y17
VCC_AXG_NCTF W17
VCC_AXG_NCTF V17
VCC_AXG_NCTF AM16
VCC_AXG_NCTF AL16
VCC_AXG_NCTF AK16
VCC_AXG_NCTF AJ16
VCC_AXG_NCTF W25
VCC_AXG_NCTF AH16
VCC_AXG_NCTF AG16
VCC_AXG_NCTF AF16
VCC_AXG_NCTF AE16
VCC_AXG_NCTF AC16
VCC_AXG_NCTF AB16
VCC_AXG_NCTF AA16
VCC_AXG_NCTF V25
VCC_AXG_NCTF W24
VCC_AXG_NCTF V24
VCC_AXG_NCTF W23
VCC_SMAP29
VCC_SMBG32
VCC_SMBF32
VCC_AXG_NCTF W28VCC_SMAP33
VCC_AXGY26
VCC_AXGAE25
VCC_AXGAB25
VCC_AXGAA25
VCC_AXGAE24
VCC_AXGAC24
VCC_AXGAA24
VCC_AXGY24
VCC_AXGAE23
VCC_AXGAC23
VCC_AXGAB23
VCC_AXGAA23
VCC_AXGAJ21
VCC_AXGAG21
VCC_AXGAE21
VCC_AXGAC21
VCC_AXGAA21
VCC_AXGY21
VCC_AXGAH20
VCC_AXGAF20
VCC_AXGAE20
VCC_AXGAC20
VCC_AXGAB20
VCC_AXGAA20
VCC_AXGT17
VCC_AXGAM15
VCC_AXGAL15
VCC_AXGAJ15
VCC_AXGAH15
VCC_AXGAF15
VCC_AXGAB15
VCC_SM_LF AV44
VCC_SM_LF BA37
VCC_SM_LF AM40
VCC_SM_LF AV21
VCC_SM_LF AY5
VCC_SM_LF AM10
VCC_SM_LF BB13
VCC_AXGT16
VCC_AXGAG15
VCC_AXGAA15
VCC_AXGY15
VCC_AXGV15
VCC_AXGU15
VCC_AXGAN14
VCC_AXGAM14
VCC_AXGU14
VCC_AXGT14
VCC_AXG_SENSEAJ14
VSS_AXG_SENSEAH14
VCC_AXG_NCTF Y16
VCC_AXG_NCTF W16
VCC_AXG_NCTF V16
VCC_AXG_NCTF U16
VCC_SM/NCBA36
VCC_SM/NCBB24
VCC_SM/NCBD16
VCC_SM/NCBB21
VCC_SM/NCAW16
VCC_SM/NCAW13
VCC_SM/NCAT13
VCC_AXGAE15
C1
43
0.4
7U
_0
40
2_
6.3V
6K
1
2
C134
1U_0603_10V4Z
1
2
C1
24
10
U_
08
05
_10V
4Z
1
2
C1
22
10
U_
08
05
_10V4Z
1
2
C1
42
0.2
2U
_0
60
3_10V
7K
1
2
C1
39
0.1
U_
04
02
_16V
4Z
1
2
C136
10U_0805_10V4Z
1
2
C1
25
0.1
U_
04
02
_1
6V4Z
1
2
+
C1
31
22
0U
_D
2_
4VM
1
2
C1
45
1U
_0
60
3_
10V
4Z
1
2
C138
0.1U_0402_16V4Z
1
2
C1
23
0.0
1U
_0
40
2_16V
7K
1
2
POWER
VCC NCTF
VCC CORE
U2F
CANTIGA ES_FCBGA1329
VCC_NCTF AM32
VCC_NCTF AC30
VCC_NCTF AJ29
VCC_NCTF AK25
VCC_NCTF AA32
VCC_NCTF Y32
VCC_NCTF W32
VCC_NCTF U32
VCC_NCTF AM30
VCC_NCTF AL30
VCC_NCTF AK30
VCC_NCTF AG30
VCC_NCTF AF30
VCC_NCTF AE30
VCC_NCTF AL32
VCC_NCTF W30
VCC_NCTF V30
VCC_NCTF AK32
VCC_NCTF AH29
VCC_NCTF AG29
VCC_NCTF AE29
VCC_NCTF AL28
VCC_NCTF AK28
VCC_NCTF AL26
VCC_NCTF AK26
VCC_NCTF AJ32
VCC_NCTF AK24
VCC_NCTF AH32
VCC_NCTF AG32
VCC_NCTF AE32
VCC_NCTF AC32
VCC_NCTF AC29
VCC_NCTF AA29
VCC_NCTF Y29
VCC_NCTF W29
VCC_NCTF V29
VCC_NCTF U30
VCC_NCTF AL29
VCC_NCTF AK29
VCC_NCTF AH30
VCC_NCTF AB30
VCC_NCTF AA30
VCC_NCTF Y30
VCCAG34
VCCAC34
VCCAB34
VCCAA34
VCCY34
VCCV34
VCCU34
VCCAM33
VCCAK33
VCCAJ33
VCCAG33
VCCAF33
VCCAE33
VCCAC33
VCCAA33
VCCY33
VCCW33
VCCV33
VCCU33
VCCAH28
VCCAF28
VCCAC28
VCCAA28
VCCAJ26
VCCAG26
VCCAE26
VCCAC26
VCCAH25
VCCAG25
VCCAF25
VCCAG24
VCCAJ23
VCCAH23
VCCAF23
VCCT32
VCC_NCTF AK23
T43P AD
C1
40
0.1
U_
04
02
_16V
4Z
1
2
C137
10U_0805_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Cantiga(6/6)-PWR/GNDCus tom
14 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
VSS
U2 I
CANTIGA ES_FCBGA1329
VSSAU48
VSS A23
VSSAR48
VSSAL48
VSSBB47
VSSAW47
VSSAN47
VSSAJ47
VSSAF47
VSSAD47
VSSAB47
VSSY47
VSST47
VSSN47
VSSL47
VSSG47
VSSBD46
VSSBA46
VSSAV46
VSSAR46
VSSAM46
VSSV46
VSSR46
VSSP46
VSSH46
VSSF46
VSSBF44
VSSAH44
VSSAD44
VSSAA44
VSSY44
VSSU44
VSST44
VSSM44
VSSF44
VSSBC43
VSSAV43
VSSAU43
VSSAM43
VSSJ43
VSSC43
VSSBG42
VSSAY42
VSSAT42
VSSAN42
VSSAJ42
VSSAE42
VSSN42
VSSL42
VSSBD41
VSSAU41
VSSAM41
VSSAH41
VSSAD41
VSSAA41
VSSY41
VSSU41
VSST41
VSSM41
VSSG41
VSSB41
VSSBG40
VSSBB40
VSSAV40
VSSAN40
VSSH40
VSSE40
VSSAT39
VSSAM39
VSSAJ39
VSSAE39
VSSN39
VSSL39
VSSB39
VSSBH38
VSSBC38
VSSBA38
VSSAU38
VSSAH38
VSSAD38
VSSAA38
VSSY38
VSSU38
VSST38
VSSJ38
VSSF38
VSSC38
VSSBD36
VSS AM36
VSS AE36
VSS P36
VSS L36
VSS J36
VSS F36
VSS B36
VSS AH35
VSS AA35
VSS Y35
VSS U35
VSS T35
VSS BF34
VSS AM34
VSS AJ34
VSS AF34
VSS AE34
VSS W34
VSS B34
VSS A34
VSS BG33
VSS BC33
VSS BA33
VSS AV33
VSS AR33
VSS AL33
VSS AH33
VSS AB33
VSS P33
VSS L33
VSS H33
VSS N32
VSS K32
VSS F32
VSS C32
VSS A31
VSS AN29
VSS T29
VSS N29
VSS K29
VSS H29
VSS F29
VSS A29
VSS BG28
VSS BD28
VSS BA28
VSS AV28
VSS AT28
VSS AR28
VSS AJ28
VSS AG28
VSS AE28
VSS AB28
VSS Y28
VSS P28
VSS K28
VSS H28
VSS F28
VSS C28
VSS BF26
VSS AH26
VSS AF26
VSS AB26
VSS AA26
VSS C26
VSS B26
VSS BH25
VSS BD25
VSS BB25
VSS AV25
VSS AR25
VSS AJ25
VSS AC25
VSS Y25
VSS N25
VSS L25
VSS J25
VSS G25
VSS E25
VSS BF24
VSSBF37
VSSBB37
VSSAW37
VSSAT37
VSSAN37
VSSAJ37
VSSH37
VSSC37
VSSBG36
VSSAU36
VSS AT24
VSS AH24
VSS AB24
VSS L24
VSSAY46
VSS G24
VSS E24
VSS AG23
VSS B23
VSS AY24
VSS AJ24
VSS AF24
VSS R24
VSS K24
VSS J24
VSS F24
VSS BH23
VSS Y23
VSSAK15
VSS AD12
VSS AJ6
VSS
VSS NCTF
VSS SCB
NC
U2J
CANTIGA ES_FCBGA1329
VSSBG21
VSSAW21
VSSAU21
VSSAP21
VSSAN21
VSSAH21
VSSAF21
VSSAB21
VSSR21
VSSM21
VSSJ21
VSSG21
VSSBC20
VSSBA20
VSSAW20
VSSAT20
VSSAJ20
VSSAG20
VSSY20
VSSN20
VSSK20
VSSF20
VSSC20
VSSA20
VSSBG19
VSSA18
VSSBG17
VSSBC17
VSSAW17
VSSAT17
VSSR17
VSSM17
VSSH17
VSSC17
VSSBA16
VSSAU16
VSSAN16
VSSN16
VSSK16
VSSG16
VSSE16
VSSBG15
VSSW15
VSSA15
VSSBG14
VSSAA14
VSSC14
VSSBG13
VSSBC13
VSSBA13
VSSAN13
VSSAJ13
VSSAE13
VSSN13
VSSL13
VSSG13
VSSE13
VSSBF12
VSSAV12
VSSAT12
VSSAM12
VSSAA12
VSSJ12
VSSA12
VSSBD11
VSSBB11
VSSAY11
VSSAN11
VSSAH11
VSSY11
VSSN11
VSSG11
VSSC11
VSSBG10
VSSAV10
VSSAT10
VSSAJ10
VSSAE10
VSSAA10
VSSBH8VSSB9VSSG9VSSAD9VSSAM9VSSAN9 VSSBC9
VSSM10
VSSBF9
VSS AH8
VSS Y8
VSS L8
VSS E8
VSS B8
VSS AY7
VSS AU7
VSS AN7
VSS AJ7
VSS AE7
VSS AA7
VSS N7
VSS J7
VSS BG6
VSS BD6
VSS AV6
VSS AT6
VSSAC15
VSS AM6
VSS M6
VSS C6
VSS BA5
VSS AH5
VSS AD5
VSS Y5
VSS L5
VSS J5
VSS H5
VSS F5
VSS BE4
VSS BC3
VSS AV3
VSS AL3
VSS_NCTF AF32
VSS_NCTF AB32
VSS_NCTF V32
VSS_NCTF AJ30
VSS_NCTF AM29
VSS_NCTF AF29
VSS_NCTF AB29
VSS_NCTF U26
VSS_NCTF U23
VSS_NCTF AL20
VSS_NCTF V20
VSS_NCTF AC19
VSS_NCTF AL17
VSS_NCTF AJ17
VSS_NCTF AA17
VSS_NCTF U17
VSS_SCB BH48
VSS_SCB BH1
VSS_SCB A48
VSS_SCB C1
VSS_SCB A3
NC E1
NC D2
NC C3
NC B4
NC A5
NC A6
NC A43
NC A44
NC B45
NC C46
NC D47
NC B47
NC A46
NC F48
NC E48
NC C48
NC B48
VSS R3
VSS P3
VSS BA2
VSS AR2VSS AU2
VSS AP2
VSS F3
VSS AW2
VSS AE2VSS AF2VSS AH2VSS AJ2
VSS AD2
VSS AC2
VSS Y2
VSS M2
VSS K2
VSS AM1
VSS AA1
VSS P1
VSS H1
VSSBB8
VSSAV8
VSSAT8
VSS U24
VSS U28
VSS U25
VSS U29
VSSL12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V _DDR _MCH_REF
M_ CLK_DDR0
M_ CLK_DDR1
M_ CLK_DDR#0
M_ CLK_DDR#1
DDR _CKE1_DIMMA
DDR _CS0_DIMMA#
CLK_SMBCLK
D DR_A_MA1
DDR_A_MA10
D DR_A_MA3
D DR_A_MA9 D DR_A_MA7DDR_A_MA12
D DR_A_MA5
DDR _A_WE#
DDR_ A_D8
DDR _A_D17DDR _A_D16
DDR _A_D27DDR _A_D26
DDR _A_DQS1
DDR _A_DQS0
DDR _A_DQS2
DDR _A_DM3
DDR _A_DM1
DDR _A_DM2
DDR _A_DM0
DDR _A_DQS4
DDR _A_DQS6
DDR _A_DQS7
CLK_SMBDATA
DDR _CKE0_DIMMA
DDR_A_MA8
DDR _CS1_DIMMA#
DDR_A_MA11
D DR_A_MA2D DR_A_MA0
D DR_A_MA4
DDR_A_MA6
DD R_A_CAS#
D DR_A_BS1DD R_A_RAS#
DDR _A_D20DDR _A_D21
DDR _A_D53DDR _A_D52
DDR _A_D55
DDR _A_DM6
DDR _A_DM4
DDR _A_DM5
DDR _A_DM7
DDR_A_MA13
DDR _A_DQS5
D DR_A_BS0
D DR_A_BS2
DDR _A_DQS#0
DDR _A_DQS#1
DDR _A_DQS#2
DDR _A_DQS3DDR _A_DQS#3
DDR _A_DQS#4
DDR _A_DQS#5
DDR _A_DQS#6
DDR _A_DQS#7
M_ODT1
M_ODT0
DDR _A_D51DDR _A_D54DDR _A_D50
DDR _A_D49DDR _A_D48
DDR _A_D42
DDR _A_D39
DDR _A_D22DDR _A_D23
DDR _A_D12DDR _A_D13
DDR _A_D10 DDR _A_D14DDR _A_D11 DDR _A_D15
DDR_ A_D9
DDR_ A_D0DDR_ A_D1
DDR_ A_D3DDR_ A_D2
DDR_ A_D4
DDR_ A_D6
DDR_ A_D5
DDR_ A_D7
DDR _A_D18DDR _A_D19
DDR _A_D31DDR _A_D30
DDR _A_D28DDR _A_D29DDR _A_D25DDR _A_D24
DDR _A_D36
DDR _A_D38
DDR _A_D37
DDR _A_D35
DDR _A_D32DDR _A_D33
DDR _A_D34
DDR _A_D44DDR _A_D45
DDR _A_D40DDR _A_D41
DDR _A_D46
DDR _A_D60DDR _A_D61 DDR _A_D57
DDR _A_D56
DDR _A_D58DDR _A_D63
DDR _A_D59DDR _A_D62
DDR_A_MA14DDR _CKE1_DIMMA
D DR_A_MA0
D DR_A_MA4
D DR_A_BS2
D DR_A_BS1
DDR_A_MA6
DDR _CKE0_DIMMA
D DR_A_MA2
D DR_A_MA1
DD R_A_CAS#
DD R_A_RAS#
D DR_A_BS0
D DR_A_MA3
DDR_A_MA10
DDR _CS0_DIMMA#
M_ODT1DDR _CS1_DIMMA#
DDR _A_WE#
M_ODT0DDR_A_MA13
D DR_A_MA7
DDR_A_MA14
DDR_A_MA11
DDR _A_D47 DDR _A_D43
D DR_A_MA9DDR_A_MA12
D DR_A_MA5DDR_A_MA8
DDR_A _D[0..63]<10>
DDR_CKE0_DIMMA<9>
DDR_A_BS2<10>
DDR_A_BS0<10>DDR_A_WE#<10>
DDR_A_CAS#<10>
M_ODT1<9>
DDR_CS1_DIMMA#<9>
M_CLK_DDR0 <9>M_CLK_DDR#0 <9>
DDR_CKE1_DIMMA <9>
DDR_A_BS1 <10>DDR_A_RAS# <10>DDR_CS0_DIMMA# <9>
M_CLK_DDR#1 <9>
M_ODT0 <9>
V _DDR_MCH_REF <9,16>
M_CLK_DDR1 <9>
PM_EXTTS#0 <9>
CLK_SMBDATA<16,17>CLK_SMBCLK<16,17>
DDR_A_DQS#[0..7]<10>
DDR_A _DM[0..7]<10>
DDR_A _DQS[0..7]<10>
DDR_A_MA[0..14]<10>
+1.8V
+3VS
+1.8V
+1.8V
+0.9V
+0.9V
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
DDRII-SODIMM SLOT1Cus tom
15 46S aturday, January 05, 2008
2006/02/13 2006/03/10Compal Electronics, Inc.
Layout Note:Place these resistorclosely JP3,alltrace length Max=1.5"
Layout Note:Place nearJP3
Layout Note:Place one cap close to every 2pullup resistors terminated to +0.9VS
SO-DIMM A
5 10
C1
49
0.1
U_
04
02
_1
6V4Z
1
2
RP556_0404_4P2R_5%1 42 3
C1
55
2.2
U_
08
05
_1
6V4Z
1
2
RP6 56_0404_4P2R_5%1423
C1
48
0.1
U_
04
02
_1
6V4Z
1
2
C1
68
0.1
U_
04
02
_16V
4Z
1
2
RP2 56_0404_4P2R_5%1423
RP4 56_0404_4P2R_5%1423
C172
0.1
U_
04
02
_16
V4Z
1
2
C1
61
0.1
U_
04
02
_16V
4Z
1
2
RP756_0404_4P2R_5%1 42 3
C1
54
2.2
U_
08
05
_1
6V4Z
1
2
RP1156_0404_4P2R_5%
1 42 3
C1
64
0.1
U_
04
02
_16V
4Z
1
2
C1
59
0.1
U_
04
02
_16V
4Z
1
2
C1
51
0.1
U_
04
02
_1
6V4Z
1
2
C1
46
2.2
U_
08
05
_1
6V4Z
1
2
C171
2.2
U_
06
03
_6
.3V
4Z 1
2
C1
53
2.2
U_
08
05
_1
6V4Z
1
2
RP956_0404_4P2R_5%1 42 3
C1
63
0.1
U_
04
02
_16V
4Z
1
2
RP356_0404_4P2R_5%1 42 3
C1
57
0.1
U_
04
02
_1
6V4Z
1
2
C1
52
2.2
U_
08
05
_1
6V4Z
1
2
C1
47
2.2
U_
08
05
_1
6V4Z
1
2
C1
62
0.1
U_
04
02
_16V
4Z
1
2
RP13 56_0404_4P2R_5%1423
R1
16
10
K_
04
02_5
%
12
R1
15
10
K_
04
02_5
%
12
C1
66
0.1
U_
04
02
_16V
4Z
1
2
C1
60
0.1
U_
04
02
_16V
4Z
1
2
C1
67
0.1
U_
04
02
_16V
4Z
1
2
C1
58
0.1
U_
04
02
_16V
4Z
1
2
RP8 56_0404_4P2R_5%1423
C1
70
0.1
U_
04
02
_16V
4Z
1
2
RP10 56_0404_4P2R_5%1423
+
C1
50
33
0U
_D
2E
_2
.5V
M_R
7
1
2
C1
69
0.1
U_
04
02
_16V
4Z
1
2
RP12 56_0404_4P2R_5%1423
C1
65
0.1
U_
04
02
_16V
4Z
1
2
C1
56
0.1
U_
04
02
_1
6V4Z
1
2
JDIMM1
FOX_ASOA426-M4R-TRC ONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
RP156_0404_4P2R_5%1 42 3
R117 56_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR _B_DQS#4
DDR _B_D14
DDR _B_DQS4
D DR_B_BS2
D DR_B_MA2
DDR _CKE2_DIMMB
DDR_ B_D8
DDR _B_DM3
DDR _B_D45
D DR_B_MA3
DDR _B_D32
DDR _B_D40
DDR_ B_D6
D DR_B_MA7
DDR _B_D13
DDR_ B_D1
DDR _B_DQS#0
DDR _CS3_DIMMB#
M_ODT3
DDR_B_MA11
DDR _B_D47
DDR _B_WE#
DDR_ B_D7
DDR _B_D11
DDR_B_MA10
DDR _B_D34
DDR _B_D41
DDR _B_DQS5
M_ODT2
DDR _B_DQS2
DDR _B_DQS#7
DDR_B_MA6
DDR_ B_D9
DDR _B_D44
DDR _B_D62
DDR _B_DM7
D DR_B_BS0
D DR_B_MA5
DDR _B_D56
DDR _B_DQS#3
DDR _B_D10
DDR _B_D12
DDR _B_D19
DDR _B_D37
DDR _B_DQS7
DDR _B_D42
DDR _B_D36
DDR _CKE3_DIMMB
DDR _B_DQS0
DDR _B_D46
D DR_B_MA1
DDR_B_MA8
DDR _B_DQS#2
DDR _B_DQS#5
DDR_B_MA12
DDR _B_DQS3
DD R_B_RAS#
D DR_B_MA4
DDR _B_DM5
DDR _B_D35
DDR _B_D43
DDR_ B_D2
DDR_B_MA13
DDR _B_D33
DDR _B_DQS1
D DR_B_BS1
DDR _B_D59
DDR _B_DQS#6
DDR _B_DM4
DDR _B_DQS6
DDR _B_DQS#1
D DR_B_MA9
D DR_B_MA0
DDR_ B_D3
DDR _B_D15
DD R_B_CAS#
DDR _B_D18
DDR _CS2_DIMMB#
DDR _B_DM0
DDR _B_DM1
DDR_ B_D0
DDR _B_DM6
DDR _B_D60
DDR _B_DM2
DDR _B_D38DDR _B_D39
DDR _B_D31DDR _B_D30
DDR _B_D27
DDR _B_D28
DDR _B_D20DDR _B_D16DDR _B_D21DDR _B_D17
M_ CLK_DDR3M_ CLK_DDR#3
M_ CLK_DDR2M_ CLK_DDR#2
DDR_ B_D5DDR_ B_D4
DDR _B_D23DDR _B_D22
DDR _B_D29DDR _B_D24DDR _B_D25
DDR _B_D26
DDR _B_D61 DDR _B_D57
DDR _B_D58DDR _B_D63
V _DDR _MCH_REF
M_ODT3DDR _CS3_DIMMB#
DDR _B_WE#
D DR_B_MA5DDR_B_MA8
D DR_B_BS0
DD R_B_CAS#
D DR_B_MA0
DDR_B_MA10
D DR_B_BS1
DDR_B_MA14
DDR _CKE3_DIMMB
CLK_SMBCLKCLK_SMBDATA
DDR_B_MA14DDR_B_MA11
D DR_B_MA7DDR_B_MA6
D DR_B_MA4D DR_B_MA2
DD R_B_RAS#DDR _CS2_DIMMB#
M_ODT2DDR_B_MA13
D DR_B_MA1D DR_B_MA3
D DR_B_MA9DDR_B_MA12
D DR_B_BS2DDR _CKE2_DIMMB
DDR _B_D51DDR _B_D54
DDR _B_D49DDR _B_D48
DDR _B_D55DDR _B_D50
DDR _B_D52DDR _B_D53
DDR_CKE3_DIMMB <9>
DDR_CS2_DIMMB# <9>
V _DDR_MCH_REF <9,15>
DDR_B_WE#<10>
DDR_B_BS1 <10>DDR_B_RAS# <10>
DDR_B_CAS#<10>
M_ODT3<9>
DDR_CKE2_DIMMB<9>
DDR_CS3_DIMMB#<9>
DDR_B_BS2<10>
DDR_B_BS0<10>
M_ODT2 <9>
PM_EXTTS#1 <9>
M_CLK_DDR2 <9>M_CLK_DDR#2 <9>
M_CLK_DDR3 <9>M_CLK_DDR#3 <9>
CLK_SMBDATA<15,17>CLK_SMBCLK<15,17>
DDR_B_MA[0..14]<10>
DDR_B _D[0..63]<10>
DDR_B _DQS#[0..7]<10>
DDR_B _DM[0..7]<10>
DDR_B _DQS[0..7]<10>
+1.8V
+3VS+3VS
+1.8V
+1.8V
+0.9V
+0.9V
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
DDRII-SODIMM SLOT2
16 46S aturday, January 05, 2008
2006/02/13 2006/03/10Compal Electronics, Inc.
SO-DIMM B
Layout Note:Place nearJP10
Layout Note:Place one cap close to every 2pullup resistors terminated to +0.9VS
Layout Note:Place these resistorclosely JP3,alltrace length Max=1.5"
0612 add
5 10
5
RP2456_0404_4P2R_5%
1 42 3
R1
19
10
K_
0402_5%
12
RP2256_0404_4P2R_5%1 42 3
RP17 56_0404_4P2R_5%1423
C1
84
0.1
U_
04
02
_16V
4Z
1
2
RP1456_0404_4P2R_5%1 42 3
C1
83
2.2
U_
08
05
_16V
4Z
1
2
C1
80
0.1
U_
04
02
_16V
4Z
1
2
RP21 56_0404_4P2R_5%1423
C1
73
2.2
U_
08
05
_1
6V4Z
1
2
C1
89
0.1
U_
04
02
_16V
4Z
1
2
C1
75
2.2
U_
08
05
_16V
4Z
1
2
RP25 56_0404_4P2R_5%1423 C197
2.2
U_
06
03
_6
.3V
4Z 1
2
RP1656_0404_4P2R_5%1 42 3
C1
88
0.1
U_
04
02
_16V
4Z
1
2
JDIMM2
FOX_AS0A426-N8RN-7FC ONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SA0 198
SA1 200
C1
93
0.1
U_
04
02
_16V
4Z
1
2
C1
81
0.1
U_
04
02
_16V
4Z
1
2
R120 56_0402_5%
1 2
C1
90
0.1
U_
04
02
_16V
4Z
1
2
C1
78
0.1
U_
04
02
_16V
4Z
1
2
C1
76
2.2
U_
08
05
_16V
4Z
1
2
C1
82
0.1
U_
04
02
_1
6V4Z
1
2
C1
86
0.1
U_
04
02
_16V
4Z
1
2
C1
79
0.1
U_
04
02
_16V
4Z
1
2
C198
0.1
U_
04
02
_16
V4Z1
2
C1
94
0.1
U_
04
02
_16V
4Z
1
2
C1
92
0.1
U_
04
02
_16V
4Z
1
2
C1
77
2.2
U_
08
05
_16V
4Z
1
2
C1
95
0.1
U_
04
02
_16V
4Z
1
2
C1
87
0.1
U_
04
02
_16V
4Z
1
2
RP23 56_0404_4P2R_5%1423
RP15 56_0404_4P2R_5%1423
C1
74
2.2
U_
08
05
_16V
4Z
1
2
C1
96
0.1
U_
04
02
_16V
4Z
1
2
RP1856_0404_4P2R_5%1 42 3
C1
91
0.1
U_
04
02
_16V
4Z
1
2
RP26 56_0404_4P2R_5%1423
RP2056_0404_4P2R_5%1 42 3
C1
85
0.1
U_
04
02
_16V
4Z
1
2
R118
10K_0402_5%
1 2
RP19 56_0404_4P2R_5%1423
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
F S C
FSB
FSA
H_STP_CPU#H_STP_PCI#
R _CLKREQ#_7
C LK_48M_ICH
C LK_14M_ICH
CLK _ PCI_ICH
CL K_PCI_EC
CLK_DEBUG_PORT_0
CLK_XTAL_IN
CLK_XTAL_OUT
CLK_SMBCLK
CLK_SMBDATA
ITP_EN P CI_CLK3
ITP_EN
R EF1
FSAR _CLK_48M_CRUSB
R_CK P WRGDFSB
CLK_XTAL_OUTCLK_XTAL_IN
F S C
CLK_SMBDATACLK_SMBCLK
PCI2_TME27_SELP CI_CLK3
R_MCH _DREFCLKR_MC H_DREFCLK# S S C DREFCLK#
S S C DREFCLK
R_P CI E_ICHR_P C IE_ICH#
R_PCIE_SATAR_PCIE_SATA#
R_C LKREQ#_C
R _CLKREQ#_4
R _CLK_PCIE_LAN#
R_CLK _PCIE_NCARDR_CLK _PCIE_NCARD#
R_ CLK_PCIE_MCARD0#R_C LK_PCIE_MCARD0
R _CLK_PCIE_LAN
R_ CLK_PCIE_MCARD2#R_C LK_PCIE_MCARD2R _CLKREQ#_6R_MCH_3GPLL#R _MCH_3GPLL
R_ CPU_BCLKR_ CPU_BCLK#R_ MCH_BCLKR_ MCH_BCLK#
R_CPU_XDP#R _CPU_XDP
R_CLKREQ#_10R_ CLK_SRC11R _CLK_SRC11#
R _CLKREQ#_9P CI2_1
CPU_BSEL2<7>
MCH_CLKSEL2 <9>
CPU_BSEL1<7>
MCH_CLKSEL1 <9>
CPU_BSEL0<7>
MCH_CLKSEL0 <9>
H_STP_CPU# <22>
CLKREQ#_7<9>
ICH_SMBCLK<22,24,26>
ICH_SMBDATA<22,24,26>
CLK _PCI_ICH<20>
CLK_48M_ICH<22>
VGATE<22,43>CLK_ENABLE#<43>
CK _P WRGD<22>
CLK_14M_ICH<22>
CLK_SMBDATA<15,16>CLK_SMBCLK<15,16>
CLK_DEBUG_PORT_0<31>CLK_PCI_EC<32>
MCH_S SCDREFCLK <9>MCH_SSCDREFCLK# <9>
CLK _PCIE_ICH <22>CLK _PCIE_ICH# <22>
CLK_PCIE_SATA# <21>CLK_PCIE_SATA <21>
CLKREQ#_C <22>
CLKREQ#_4 <26>
CLK_PCIE_LAN# <25>CLK_PCIE_LAN <25>
CLK _PCIE_NCARD <26>CLK _PCIE_NCARD# <26>
CLK_PCIE_MCARD0# <26>CLK_PCIE_MCARD0 <26>
CLK_PCIE_MCARD2# <26>CLK_PCIE_MCARD2 <26>CLKREQ#_6 <26>
CLK_MCH_3GPLL <9>CLK_MCH_3GPLL# <9>CLK_MCH_BCLK#<9>
CLK_MCH_BCLK<9>CLK_CPU_BCLK#<6>CLK_CPU_BCLK<6>
CLK_CPU_XDP# <6>CLK_CPU_XDP <6>
CLKREQ#_10 <26>
H_STP_PCI# <22>
CLK _MCH_DREFCLK#<9>CLK _MCH_DREFCLK<9>
CLK_SRC11# <27>CLK_SRC11 <27>
CLKREQ#_9 <25>CLK_DEBUG_PORT_1<26>
+VCCP
+VCCP
+V CCP
+3VS_CK505
+V CCP
+3VS
+3VS
+3VS +3VS
+3VS
+3VS_CK505
+3VS_CK505
+1.05VS_CK505+1.05VS_CK505
+1.05VS_CK505
+3VS_CK505
+3VS_CK505
+1.05VS_CK505
+3VS
+1.05VS_CK505
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Clock Generator CK505
17 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Place close to U51
CPU
NB
XDP/ITP
100
PCIMHz
266
SRCMHzCLKSEL2
33.30
FSC REFMHz
DOT_96MHz
USBMHz
14.318 96.0 48.0
1331
200
166
333
Reserved
Routing the trace at least 10mil
SB, MINI PCI
1 = ITP/ITP#
PCI_CLK3
0 = SRC8/SRC8#
1 = Enable SRC0 & 27MHz(DIS)0 = Enable DOT96 & SRC1(UMA)
ITP_EN
Vendor suggests 22pF
NB (UMA)NB_SSC (UMA)
ICH
SATA
New Card
LAN
3G_PLL
MiniCard_2(WLAN)
No Debug port anymoreMiniCard_0
CPUMHzCLKSEL1
FSBCLKSEL0
FSA
48.0
48.0
48.0
48.0
48.0
48.0
96.0
96.0
96.0
96.0
96.0
96.0
14.318
14.318
14.318
14.318
14.318
14.318
33.3
33.3
33.3
33.3
33.3
33.3
100
100
100
100
100
100
100
400
00
00
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Change 33M and 48M damping to 39M by EMI request
C208
0.1U_0402_16V4Z
1
2
R176 0_0402_5%1 2
C210
0.1U_0402_16V4Z
1
2
C211
0.1U_0402_16V4Z
1
2
C207
0.1U_0402_16V4Z
1
2
R167 39_0402_1%
1 2
R1631K_0402_5%
@12
C209
10U_0805_10V4Z
1
2
R726 0_0402_5%1 2
C202
0.1U_0402_16V4Z
1
2
C2164.7P_0402_50V8C@ 12
R1431K_0402_5%
@
12
R162 475_0402_1%1 2
R1501K_0402_5%
1 2
R141 0_0402_5%@ 1 2
Q3A
2N7002DW-7-F_SOT363-6
6 1
2
C205
0.1U_0402_16V4Z
1
2
R178
2.2K_0402_5%
R164
10K_0402_5%
1 2
C199
10U_0805_10V4Z
1
2
R145 0_0402_5%
2MiniC@
1 2
R126 475_0402_1%1 2
T76
R142 0_0402_5%@ 1 2
R171
0_0402_5%1 2
CLRP1NO S HORT PADS
12
R179
2.2K_0402_5%
R134 0_0402_5%1 2
SLG8SP553VTR_QFN72_10x10
U3
VD
D_48
19
US
B_0/F
S_A
20
US
B_1/C
LK
RE
Q_A
#21
VS
S_48
22
VD
D_IO
23
SR
C_0/D
OT
_96
24
SR
C_0#/D
OT
_96#
25
VS
S_IO
26
VD
D_P
LL3
27
LC
DC
LK
/27M
28
LC
DC
LK
#/2
7M
_S
S29
VS
S_P
LL3
30
VD
D_P
LL3_IO
31
SR
C_2
32
SR
C_2#
33
VS
S_S
RC
34
SR
C_3
35
SR
C_3#
36
VD
D_C
PU
72
CP
U_0
71
CP
U_0#
70
VS
S_C
PU
69
CP
U_1
68
CP
U_1#
67
VD
D_C
PU
_IO
66
CLK
RE
Q_7#
65
SR
C_8/C
PU
_IT
P64
SR
C_8#/C
PU
_IT
P#
63
VD
D_S
RC
_IO
62
SR
C_7
61
SR
C_7#
60
VS
S_S
RC
59
CLK
RE
Q_6#
58
SR
C_6
57
SR
C_6#
56
VD
D_S
RC
55
PCI_STOP# 54
CPU_STOP# 53
VDD_SRC_IO 52
SRC_10# 51
SRC_10 50
CLKREQ_10# 49
SRC_11 48
SRC_11# 47
CLKREQ_11# 46
SRC_9# 45
SRC_9 44
CLKREQ_9# 43
VSS_SRC 42
CLKREQ_4# 41
SRC_4# 40
SRC_4 39
VDD_SRC_IO 38
CLKREQ_3# 37
CKPWRGD/PD#1
FS_B/TEST_MODE2
VSS_REF3
XTAL_OUT4
XTAL_IN5
VDD_REF6
REF_0/FS_C/TEST_7
REF_18
SDA9
SCL10
NC11
VDD_PCI12
PCI_113
PCI_214
PCI_315
PCI_4/SEL_LCDCL16
PCIF_5/ITP_EN17
VSS_PCI18
R154
0_0402_5%1 2
R1651K_0402_5%
1 2
R152 0_0402_5%1 2
R123
56_0402_5%
1 2
R18010K_0402_5%
12
R173 0_0402_5%1 2
R738 475_0402_1%1 2
R140 0_0402_5%1 2
C201
0.1U_0402_16V4Z
1
2
C2184.7P_0402_50V8C@ 12
R18310K_0402_5%
12
R138
0_0402_5%1 2
T44
C206
10U_0805_10V4Z
1
2
R175 0_0402_5%1 2
R136 0_0402_5%1 2R135 0_0402_5%1 2
R156 475_0402_1%
NewC@
1 2
R166 0_0402_5%1 2
C21418P_0402_50V8J
1
2
R1391K_0402_5%
@
12
C200
0.1U_0402_16V4Z
1
2
R133 475_0402_1%1 2
R170 0_0402_5%1 2
R153 0_0402_5%1 2
R18210K_0402_5%
@12
R158 33_0402_1%1 2
R1291K_0402_5%
1 2
R121
0_0805_5%
1 2
C21318P_0402_50V8J
1
2
R160 0_0402_5%
NewC@
1 2
C2155P_0402_50V8C@ 12
R146 475_0402_1%
2MiniC@
1 2
R1740_0402_5%
@
12
R18110K_0402_5%
@12
R137 0_0402_5%1 2
R168 0_0402_5%1 2
C212
0.1U_0402_16V4Z
1
2
R393 39_0402_1%
1 2
R130 0_0402_5%1 2
R159 0_0402_5%
NewC@
1 2
R127 0_0402_5%1 2
Y1
14.318MHZ_16PF_7A14300083
1 2
R124 0_0402_5%1 2
C204
0.1U_0402_16V4Z
1
2
C2174.7P_0402_50V8C@ 12
R177 0_0402_5%1 2
R172 0_0402_5%1 2
R147 33_0402_1%1 2
R1570_0402_5%
@
12
R725 0_0402_5%1 2
R128
2.2K_0402_5%
1 2 R132 0_0402_5%1 2
R155 39_0402_1%
1 2
R125 0_0402_5%1 2
C2195P_0402_50V8C@ 12
R161 33_0402_1%1 2
R131 0_0402_5%1 2
R122
0_0805_5%1 2
C203
0.1U_0402_16V4Z
1
2
Q3B
2N7002DW-7-F_SOT363-6
<BOM Structure>
3
5
4
R144 0_0402_5%
2MiniC@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GR EEN
HS Y N C_G_A
V S YNC_G_A D_V S YNC
D_HS Y NC
CRT _ VSYNC
CRT _HS YNC
3V DD CDA
3V DD CCL
D_DD CDATA
D_DDC CLK
BLUEC_ BLU
C_R ED
GR EEN
R E D
C_GRN
R E D
BLUE
R E D
GR EEN
BLUE
CRT _HSYNC<11>
CRT _VSYNC<11>3V DDCDA <11>
3V DDCCL <11>
M_RED<11>
M_GREEN<11>
M_BLUE<11>
D_DDCDATA <34>D_DDCCLK <34>
D_HS Y NC<34>
D_V S YNC<34>
R E D<34>
GREEN<34>
BLUE<34>
+CRT VDD+RCRT_VCC+5VS
+CRTVDD
+3VS+CRTVDD +CRTVDD
+5VS +5VS
+3VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
CRT Connector
18 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
W=40milsCRT Connector
Place close toJCRT1
CRT Termination/EMI Filter 11/07 Change CRT lounting NB-->Docking-->CRT connec tor
R186
2.2K_0402_5%
12
C230
10
P_
04
02_50V
8J
1
2
L2HLC0603CSCCR11JT_0603
1 2
C227
22
P_
04
02_50V
8J
@
1
2
Q5B
2N7002DW-7-F_SOT363-6
3
5
4
C226
22
P_
04
02_50V
8J
@
1
2
C225
22
P_
04
02_50V
8J
@
1
2
D 4
RB491D_SC59-3
2 1
R1872.2K_0402_5%
12
C2200.1U_0402_16V4Z
1
2
Q5A
2N7002DW-7-F_SOT363-6
6 1
2R1890_0603_5%1 2
L3HLC0603CSCCR11JT_0603
1 2
C2220.1U_0402_16V4Z
1 2
F1
1 .1A_6VDC_FUSE
21
C229
10
P_
04
02_50V
8J
1
2
D 5
DA
N2
17
T1
46
_S
C59
-3
@
2 31
U 5SN74AHCT1G125GW_SOT353-5
A2 Y 4OE
#1
G3
P5
L4HLC0603CSCCR11JT_0603
1 2
R1882.2K_0402_5%
12
R1840_0603_5%1 2
C223
5P_0402_50V8C
@1
2
D 6
DA
N2
17
T1
46
_S
C59
-3
@
2 31
R1
96
15
0_
04
02_1
%
12
C2210.1U_0402_16V4Z
1 2
U 4SN74AHCT1G125GW_SOT353-5
A2 Y 4OE
#1
G3
P5
JCRT1
SUYIN_070546FR015S263ZRC ONN@
61117
1228
1339
144
10155
1617
D7
DA
N2
17
T1
46
_S
C59
-3
@
2 31
C224
5P_0402_50V8C
@1
2
C228
10
P_
04
02_50V
8J
1
2
R1
97
15
0_
04
02_1
%
12
R185
2.2K_0402_5%
12
R1
95
15
0_
04
02_1
%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDC2 _CLK
LVDS_A2-
LVDS_ACLK+LVDS_ACLK-DDC2 _CLKDD C2_DATA
DM IC_DAT
DD C2_DATA
DA C_ BRIG
LVDS_A1-
DD C2_DATA
DDC2 _CLK
LVDS_ACLK-
BKOFF#
LVDS_A2+
LVDS_A1+
LVDS_ACLK+
LVDS_A0-
I NV_PWM
USB20_N4
DMI C_CLK
LVDS_A0+USB20_P4
+3V_LOGO
DM IC_DAT
DMI C_CLK
INV_PWM <32>
DA C_BRIG <32>BKOFF# <32>
LVDS_A2+ <11>LVDS_A2- <11>
LVDS_A1+ <11>LVDS_A1- <11>
LVDS_A0+ <11>LVDS_A0- <11>
LVDS_ACLK+ <11>LVDS_ACLK- <11>
DMIC_DAT <28>DMIC_CLK <28>
DDC2_DATA <11>
DDC2_CLK <11>
USB20_P4<22>USB20_N4<22>
E NA VDD<11>
GPIO20<22>
INV PWR_B++LCDVDD+3VS
+3VS
+USB_CAM
+5VALW +USB_CAM
+LCDVDD+5VALW+LCDVDD+LCDVDD
INVPWR_B+B+
+3VS
+5VS
+3VS
+5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
LCD CONN.
19 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
LVDS CONN & USB Camera + Dig Mic
0308_Install all cap for EMIrequest.
0831 EMI request
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm
USB Camera
Avoid Panel display garbage after power on.
0308_Reserve L10 and install L11.
Limited Current < 1A
+USB_CAM=1.25(1+R1091/R1093)
11/07 Change R727 to 0805 size
11/07 Change U42 to 3.9V LDO(Adjustable)
11/07 Change R1091 to 215K ,,,,R1093 to 100K
11/08 Change C1391 、、、、C1392 to 0805 size
11/09 EMI reserver
Must close JLVDS1pin 24 、、、、26
11/17 Delete LVDS B01/03 Change to 0.047u to meet T1 timing
C2356
80
P_
04
02_5
0V7K
12
C434680P_0402_50V7K
1
2
C238
0.047U_0402_16V7K
C232
0.1U_0402_16V4Z
1
2
U42
G916-390T1UF_SOT23-5
IN1
GND2
SHDN3
OUT 5
BYP 4
C1401 100P_0402_50V8J@ 1 2
C139210U_0805_6.3V6M
1
2
R1991M_0402_5%
12
C435680P_0402_50V7K
1
2
PJP6P A D-OPEN 2x2m
@
21
R1093100K_0402_1%
12
R1091215K_0603_1%
12
R198100_0402_5%
12
C231
0.1U_0402_16V4Z
1
2
C1402 100P_0402_50V8J@ 1 2
C1391
10U_0805_6.3V6M
1
2
L6FBMA-L11-201209-221LMA30T_0805
1 2
JLVDS1
ACES_88242-4001C ONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
GND41 GND 42
R200
100K_0402_5%
12
R201100K_0402_5%
12
C234
4.7
U_
08
05
_10
V4Z
1
2
R441 0_0402_5% @ 1 2
Q8B2N7002DW-7-F_SOT363-6
3
5
4
R2022.2K_0402_5%
12
C302
220P_0402_25V8J
@ 1
2
C1399 100P_0402_50V8J@ 1 2
C237
68
0P
_0
402
_50V
7K
12
R2032.2K_0402_5%
12
Q8A2N7002DW-7-F_SOT363-6
61
2
R727470_0805_5%
1 2
L5 0_0805_5%@
1 2
C303
220P_0402_25V8J
@1
2
PJP5P A D-OPEN 2x2m
21
C1400 100P_0402_50V8J@ 1 2
G
D S
Q7SI2301BDS-T1-E3_SOT23-3
2
1 3
C236
68
0P
_0
402
_50V
7K1
2
C2334.7U_0805_10V4Z
1
2
R4400_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI_CS1#_R
P CI_GNT3#
P C I_PIRQE#
P CI _PIRQG#
P CI_ PIRQH#
P CI_REQ2#
P CI_REQ3#
P CI_ PIRQD#
PCI_DEVSEL#
P CI _TRDY#
P CI_FRAME#
PCI_STOP#
P CI_PLOCK#
P CI_ IR DY#
P C I_PERR#
P C I_SERR#
P C I_PIRQA#
P CI_ PIRQC#
P C I_PIRQB#
P CI_REQ0#
P CI_REQ1#
P CI _PIRQF#
P CI_GNT0#
P CI_PLOCK#
PCI_RST#
CLK _ PCI_ICH
P C I_PERR#
PLT_RST#
CLK _ PCI_ICH
P C I_SERR#
PCI_DEVSEL#
PCI_PME#
PCI_STOP#
P CI_REQ3#
P CI_GNT0#
P CI _TRDY#P CI_FRAME#
P CI_ IR DY#
P CI_REQ2#
P CI_REQ1#
P CI_GNT3#
P C I_PIRQA#
P CI_ PIRQC#P C I_PIRQB#
P CI_ PIRQD#P CI _PIRQG#
P C I_PIRQE#P CI _PIRQF#
P CI_ PIRQH#
P CI_REQ0#
SPI_CS1#_R<22>
PCI_PME# <32>CLK _P CI_ICH <17>PLT_RST# <9,25,26,27>
P CI_RST# <31,32>
A CCEL_INT <24>
P CI_SERR# <32>
+3VS
+3VS
+3VALW
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
ICH9(1/4)-PCI/INT
20 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
0
Boot BIOS Location
PCI
PCI_GNT0# SPI_CS#1
1
Boot BIOS Strap
*LPC
SPI
A16 swap override Strap
PCI_GNT3#Low= A16 swap override EnbleHigh= Default *
1
3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistan ce.
Place closely pin D4
01
1
R286 8.2K_0402_5%
1 2
R288 8.2K_0402_5%
12
R281 8.2K_0402_5%1 2
R292 8.2K_0402_5%1 2
R293 8.2K_0402_5%1 2
R273 8.2K_0402_5%
1 2
R28010_0402_5%
@12
Interrupt I/F
PCI
U12B
ICH9-M ES_FCBGA676
AD0D11
AD1C8
AD2D9
AD3E12
AD4E9
AD5C9
AD6E10
AD7B7
AD8C7
AD9C5
AD10G11
AD11F8
AD12F11
AD13E7
AD14A3
AD15D2
AD16F10
AD17D5
AD18D10
AD19B3
AD20F7
AD21C3
AD22F3
AD23F4
AD24C1
AD25G7
AD26H7
AD27D1
AD28G5
AD29H6
AD30G1
AD31H3
PIRQA#J5
PIRQB#E1
PIRQC#J6
PIRQD#C4
REQ0# F1
GNT0# G4
REQ1#/GPIO50 B6
GNT1#/GPIO51 A7
REQ2#/GPIO52 F13
GNT2#/GPIO53 F12
REQ3#/GPIO54 E6
GNT3#/GPIO55 F6
C/BE0# D8
C/BE1# B4
C/BE2# D6
C/BE3# A5
IRDY# D3
PAR E3
PCIRST# R1
DEVSEL# C6
PERR# E4
PLOCK# C2
SERR# J4
STOP# A4
TRDY# F5
FRAME# D7
PLTRST# C14
PCICLK D4
PME# R2
PIRQE#/GPIO2 H4
PIRQF#/GPIO3 K6
PIRQG#/GPIO4 F2
PIRQH#/GPIO5 G2
R289 8.2K_0402_5%1 2
R275 8.2K_0402_5%
1 2
R296
1K_0402_5%
@
1 2
R284 8.2K_0402_5%
1 2C4258.2P_0402_50V
@1
2
R291 0_0402_5%GS@
1 2
R285 8.2K_0402_5%
1 2
R276 8.2K_0402_5%
1 2
R295
1K_0402_5%@
1 2
R272 8.2K_0402_5%
1 2
R278 8.2K_0402_5%
1 2
R294
1K_0402_5%
@1 2
R274 8.2K_0402_5%
1 2
R283 8.2K_0402_5%
1 2
R282 8.2K_0402_5%
1 2
R279 8.2K_0402_5%
1 2
R290 8.2K_0402_5%1 2
R287 8.2K_0402_5%
1 2
R277 8.2K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KB_RST#
GATEA20
I CH_RTCX1
S M_ INTRUDER#
ICH_ INTVRMENLAN100_SLP
SATA_LED#
SATA_TXP0_CSATA_TXN0_C
SATA_TXP0SATA_TXN0
HDA _S DOUT_CODEC
I CH_RTCX2
H DA_BITCLK
HDA _ SDIN0HDA _ SDIN1
HDA _S YNC
ICH _RTCRST#
H_ INIT#
H_ IG NNE#
H_ I NTR
H_N MI
H_STPCLK#
H_DPRSTP#H _DPRSTP_R#
H_SMI#
R_H_ FERR#
H_P WR GOOD
H_DPRSTP#
H_DPSLP#
T HR MTRIP_ICH#
KB_RST#
LPC_AD0
LPC_AD3LPC_AD2
LPC_FRAME#
GATEA20H_A20M#
LPC_AD1
I CH_RTCX1
I CH_RTCX2
H DA_BITCLK
H_DPSLP#
IC H_SRTCRST#
IC H_SRTCRST#
ICH_R SVD
LAN100_SLP
ICH_ INTVRMEN
SATA_TXP4_CSATA_TXN4_C
SATA_TXP4SATA_TXN4
HDA _SDOUT
H_F ERR#
S M_ INTRUDER#
SATA_TXP5_CSATA_TXN5_C
SATA_TXP5SATA_TXN5
CLK_PCIE_SATA#CLK_PCIE_SATA
SATA_TXP1_CSATA_TXN1_C
SATA_TXP1SATA_TXN1
HDA _ SDIN2
G LAN_COMP
H DARST#
HDA _ SDOUT_MDC
HDA _S DOUT_CODEC
SATA_RXN0_C<24>SATA_RXP0_C<24>SATA_TXN0<24>SATA_TXP0<24>
HDA _SDIN0<28>
SATA_LED#<33>
HDA _SDIN1<29>
H_DPSLP# <7>H_DPRSTP# <7,9,43>
H_F ERR# <6>
H_P WRGOOD <6,7>
H_ IGNNE# <6>
H_ INIT# <6>
H_NMI <6>H_SMI# <6>
H_STPCLK# <6>
H_THERMTRIP# <6,9>
LP C_AD[0..3] <26,31,32>
LPC_FRAME# <26,31,32>
H_A20M# <6>GATEA20 <32>
H_ INTR <6>KB_RST# <32>
ICH_RSVD <22>
SATA_RXN4_C <24>SATA_RXP4_C <24>
SATA_TXN4 <24>SATA_TXP4 <24>
HDA _SDOUT_MDC<29>HDA _S DOUT_CODEC<28>
SATA_RXN5_C <30>SATA_RXP5_C <30>
SATA_TXN5 <30>SATA_TXP5 <30>
CLK_PCIE_SATA# <17>CLK_PCIE_SATA <17>SATA_RXN1_C<24>
SATA_RXP1_C<24>SATA_TXN1<24>SATA_TXP1<24>
HDA _SDIN2<9>
HDA _SDOUT_NB<9>
HDA _BITCLK_CODEC<28>HDA_BITCLK_MDC<29>HDA_BITCLK_NB<9>
HDA _S YNC_NB<9>HDA _RST#_CODEC<28,32>HDA_RST#_MDC<29>HDA_RST#_NB<9>
HDA _S Y NC_MDC<29>HDA _S Y NC_CODEC<28>
+3VS
+RT CVCC
+3VS
+VCCP
+V CCP
+RT CVCC
+V CCP
BATT1.1
+3VL+RT CVCC
+1.5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
ICH9(2/4)_LAN,HD,IDE,LPCCus tom
21 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
XOR CHAIN ENTRANCE STRAP:RSVD
placed within 2"from ICH9M
within 2" from R379
0821 Change C528 and C516 to 15PF
0
1
ICH_RSVD HDA_SDOUT_CODEC
3/28 add 56ohm
Low = Internal VR DisabledHigh = Internal VR Enabled(Default)
ICH_INTVRMEN
ICH8M Internal VR Enable Strap(Internal VR for VccSus1.05, VccSus1.5,VccCL1.5)
ICH_LAN100_SLP Low = Internal VR DisabledHigh = Internal VR Enabled(Default)
ICH8M LAN100 SLP Strap(Internal VR for VccLAN1.05 and VccCL1.05)
P- HDD
ODD
W=20milsW=20mils
W=20mils
W=20mils
Place near ICH9
De-feature disable
e-SATA
Within 500 mils
0
0
0
1
1 1
Add 12p on HDA_SDOUT and HDA_SDOUT
C311 12P_0402_50V8J1 2
R298
10K_0402_5%1 2
C4320.01U_0402_50V7K
ESATA@
12
R301
10K_0402_5%1 2
T55P AD
D8
DAN202U_SC70
2
31
R316 33_0402_5%
1 2
R300 330K_0402_5%1 2
C4310.01U_0402_50V7K
1 2
R307
20K_0402_5%1 2
C312 12P_0402_50V8J1 2
R319 54.9_0402_1%1 2
C437
15P_0402_50V8J
1
2
R314 33_0402_5%
1 2
BATT1
CR2032 RTC BATTERY@
Y 2
32.768KHZ_12.5P_MC-146
1 4
2 3
C436
15P_0402_50V8J
1
2
R209 33_0402_5%
1 2
R302 180K_0402_5%1 2
T56P AD
R329
0_0402_5%
1 2
R32710_0402_5%
@12
R317 33_0402_5%
1 2
R32224.9_0402_1%
1 2
R31056_0402_5%
1 2
R320 33_0402_5%
1 2
R328
10M_0402_5%
1 2
R3090_0402_5%
1 2
R208 33_0402_5%
1 2
T54 P AD
R31124.9_0402_1%1 2
C821
0.01U_0402_50V7K
Multi@1 2
R313 33_0402_5%
1 2
C427
1U_0603_10V4Z
1
2
R330
1K_0402_5%
1 2
R318 33_0402_5%
1 2
R31556_0402_5%
12
R321 33_0402_5%
1 2
C8200.01U_0402_50V7K
Multi@1 2
R207 33_0402_5%
1 2
R326
1K_0402_5%
@1 2
C433
0.01U_0402_50V7K
1 2
R312 33_0402_5%
1 2
R30856_0402_5%
12
C429
0.01U_0402_50V7K
12
C426
0.1U_0402_16V4Z
1
2
R299 330K_0402_5%1 2
R303
0_
04
02_
5%
@
12
R306
56_0402_5%
@1 2
R325
1K_0402_5%
@1 2
JBATT1
ACES_85205-02001C ONN@
11
22
GND3
GND4
C4300.01U_0402_50V7K
ESATA@
12
R304
0_
04
02_
5%
@
12
C4280.01U_0402_50V7K
12
C43910P_0402_25V8K
@1
2
CLRP2S HORT PADS
12
R297 1M_0402_5%1 2
R204 33_0402_5%
1 2
R305
56_0402_5%
@1 2
RTC
LPC
CPU
LAN / GLAN
IHDA
SATA
U12A
ICH9-M ES_FCBGA676
FWH0/LAD0 K5
FWH1/LAD1 K4
FWH2/LAD2 L6
FWH3/LAD3 K2
FWH4/LFRAME# K3
LDRQ0# J3
LDRQ1#/GPIO23 J1
A20GATE N7
A20M# AJ27
DPRSTP# AJ25
DPSLP# AE23
FERR# AJ26
CPUPWRGD AD22
IGNNE# AF25
INIT# AE22
INTR AG25
RCIN# L3
NMI AF23
SMI# AF24
STPCLK# AH27
THRMTRIP# AG26
SATA4RXN AH11
SATA4RXP AJ11
SATA4TXN AG12
SATA4TXP AF12
SATA5RXN AH9
SATA5RXP AJ9
SATA5TXN AE10
SATA5TXP AF10
SATA_CLKN AH18
SATA_CLKP AJ18
SATARBIAS# AJ7
SATARBIAS AH7
RTCX1C23
RTCX2C24
RTCRST#A25
SRTCRST#F20
INTRUDER#C22
INTVRMENB22
LAN100_SLPA22
GLAN_CLKE25
LAN_RSTSYNCC13
LAN_RXD0F14
LAN_RXD1G13
LAN_RXD2D14
LAN_TXD_0D13
LAN_TXD_1D12
LAN_TXD_2E13
GLAN_COMPIB28
GLAN_COMPOB27
HDA_BIT_CLKAF6
HDA_SYNCAH4
HDA_RST#AE7
HDA_SDIN0AF4
HDA_SDIN1AG4
HDA_SDIN2AH3
HDA_SDIN3AE5
HDA_SDOUTAG5
HDA_DOCK_EN#/GPIO33AG7
HDA_DOCK_RST#/GPIO34AE8
SATALED#AG8
SATA0RXNAJ16
SATA0RXPAH16
SATA0TXNAF17
SATA0TXPAG17
SATA1RXNAH13
SATA1RXPAJ13
SATA1TXNAG14
SATA1TXPAF14
GPIO56B10
TP12 AG27
C438
2.2U_0603_6.3V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_LOW_BAT#
LINKALERT#
ICH_R I#
P M _CLKRUN#
C LK_14M_ICH
U SB_OC#4
U SB_OC#1U SB_OC#2
U SB_OC#6
U SB_OC#8U SB_OC#7
USB20_N6USB20_P6
USB20_N4USB20_P4USB20_N5USB20_P5
WXMIT_OFF#U SB_OC#5
T HERM_SCI#
USB20_P8USB20_N8
IC H_PCIE_WAKE#
DMI_ IRCOMP
CLK _PCIE_ICH#CLK _ PCIE_ICH
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
D MI_RXN0
D MI_RXN1
D MI_RXN2
D MI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
USB20_N0
USB20_N1USB20_P1
USB20_P0
USB_OC#10USB_OC#11
ME_EC_DATA1
ME_EC_CLK1
S4_STATE#
XDP_DBRESET#
GPIO10
USB20_P2USB20_N2
E C_LID_OUT#
CL KREQ#_C
USB20_P7USB20_N7
USB20_P9USB20_N9
U SB_OC#9U SB_OC#0
PM_BMBUSY#
E C _SCI#
EC_SMI#
GPIO14
GPIO37
GPIO21
GPIO36
GPIO49
S I RQ
M _PWROK
CK _P WRGD
SLP_S4#
GPIO39
CR _CPPE#
R_STP_CPU#
P M _CLKRUN#
SB_SPKR
XDP_DBRESET#
L AN_WOL_EN
O CP#
CL_RST#
CL_DATA0
ICH_ SUSCLK
GPIO21
EC_SMI#
VGATE
SUS_STAT#
ME_EC_CLK1LINKALERT#ICH_SMBDATA
GPIO36
GPIO18
GPIO10
C LK_14M_ICH
HD DHALT_LED#
GPIO57
CL_ VREF0_ICH
C L_CLK0
E C_LID_OUT#
ME_EC_DATA1
PWRBTN_OUT#
PM_PWROK
ICH_R I#
C LK_48M_ICH
C LK_48M_ICH
MCH_ICH _SYNC#
GPIO49
GPIO20
H_STP_PCI#
ICH_LOW_BAT#
ICH_R SVD
GPIO48
T HERM_SCI#
IC H_SMBCLK
S4_STATE#
IC H_PCIE_WAKE#
PM_BMBUSY#
R_EC_RSMRST#
GPIO38CL KREQ#_C
S I RQ
GPIO14
XMIT_OFF
CL_ VREF1_ICH
GPIO37
C R_WAKE#
SLP_S5#
SLP_S3#
PCIE_C_TXP3PCIE_C_TXN3PCIE_RXP3
SPI_CS1#_R
U SBRBIAS
USB_OC#10USB_OC#11
U SB_OC#7U SB_OC#8U SB_OC#9
U SB_OC#5U SB_OC#6
U SB_OC#4
U SB_OC#0U SB_OC#1U SB_OC#2WXMIT_OFF#
PCIE_C_TXP1PCIE_C_TXN1PCIE_RXP1PCIE_RXN1
PCIE_RXN3
GPIO57
GPIO39
O CP#
CR _CPPE#
GPIO18
HD DHALT_LED#
GPIO20
GPIO48
USB20_P3USB20_N3
PCIE_C_TXP5PCIE_C_TXN5PCIE_RXP5PCIE_RXN5
DIS /UMA
DIS /UMA 17/14
17/14
SPI_CLKSPI_SB_CS#
SPI_SISPI_SO_R
GLAN_RXP
GLAN_TXP_C
G LAN_RXN
GLAN_TXN_C
PCIE_C_TXP4PCIE_C_TXN4PCIE_RXP4PCIE_RXN4
SPI_SB_CS#
SPI_SI
SPI_SO_R
C R_WAKE#
EC_SCI#_SB
E C_SCI#_GPIO12
USB20_N6 <30>USB20_P6 <30>
USB20_N4 <19>USB20_P4 <19>USB20_N5 <26>USB20_P5 <26>
USB20_N8 <26>USB20_P8 <26>
XMIT_OFF <26>
DMI_RXP0 <9>DMI_RXN0 <9>
DMI_TXP0 <9>DMI_TXN0 <9>
CLK _PCIE_ICH# <17>CLK _PCIE_ICH <17>
DMI_RXP1 <9>DMI_RXN1 <9>
DMI_TXP1 <9>DMI_TXN1 <9>
DMI_RXP2 <9>DMI_RXN2 <9>
DMI_TXP2 <9>DMI_TXN2 <9>
DMI_RXP3 <9>DMI_RXN3 <9>
DMI_TXP3 <9>DMI_TXN3 <9>
USB20_N1 <30>USB20_P1 <30>
USB20_N0 <30>USB20_P0 <30>
ICH_SMBCLK<17,24,26>ICH_SMBDATA<17,24,26>
USB20_P2 <30>USB20_N2 <30>
CL_RST# <9>
USB20_P7 <30>USB20_N7 <30>
USB20_P9 <26>USB20_N9 <26>
CLK_48M_ICH <17>CLK_14M_ICH <17>
SLP_S3# <32>
SLP_S5# <32>
PM_PWROK <9,32>
PWRBTN_OUT# <32>
DP RSLPVR <9,43>
M_PWROK <9,32>
CK _P WRGD <17>
EC_RSMRST# <32>
CL_CLK0 <9>
CL_DATA0 <9>
XDP_DBRESET#<6>
E C_LID_OUT#<32>
H_STP_PCI#<17>H_STP_CPU#<17>
ICH_PCIE_WAKE#<25,26>S IRQ<32>T HERM_SCI#<32>
VGATE<17,43>
E C_SCI#<32>
MCH_ ICH_SYNC#<9>SB_SPKR<28>
ICH_RSVD<21>
EC_SMI#<32>
CLKREQ#_C<17>
OCP#<6>
SPI_CS1#_R<20>
WXMIT_OFF#<26>
PCIE_TXN1<26>PCIE_RXP1<26>PCIE_RXN1<26>
PCIE_TXP1<26>
PCIE_TXN3<26>PCIE_RXP3<26>
PCIE_TXP3<26>
BT_OFF<30>
PM_BMBUSY#<9>
PCIE_RXN3<26>
USB20_P3 <34>USB20_N3 <34>
PCIE_TXN5<27>PCIE_RXP5<27>PCIE_RXN5<27>
PCIE_TXP5<27>
EXP_CPPE#<26>
SLP_S4# <32>
GPIO20<19>
HDDHALT_LED# <33>
CR_CPPE#<27>
CR_WAKE#<27>
R_EC_RSMRST# <39>
SPI_SB_CS#<31>SPI_CLK<31,32>
SPI_SI<31>SPI_SO_R<31>
GLAN_RXN<25>
GLAN_TXP<25>
GLAN_RXP<25>GLAN_TXN<25>
PCIE_TXN4<26>PCIE_RXP4<26>PCIE_RXN4<26>
PCIE_TXP4<26>
+3VALW
+1.5VS
+3VALW
+3VS
+3VALW
+3VS
+3VS
+3VS
+3VALW
+3VALW
+3VS
+3VS +3VS
+3VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
ICH9(3/4)_DMI,USB,GPIO,PCIECus tom
22 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Place closely pinH1
Place closely pinAF3
Low -->defaultHigh -->No boot
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-8 MiniCard(WWAN/TV)
USB-1 Right side
NA lead free
Within 500 mils
R366
USB-2 Left side(with ESATA)
USB-3 Dock
USB-9 Express card
USB-0 Right side
Within 500 mils
TV Tuner
WLAN
USB-7 Finger Printer
Card Reader
11/09 Change Gsensor control from SB
Board ID
LAN
New Card
11/17 Swap PCIE LAN and New card
11/20 Add HDCP ROM for ICH9M
11/17 Add +3VALW GD to EC_RSMRST#to fix Battery mode can't boot issue
01/03 Change HDCP ROM to +3VS
R365 10K_0402_5%@1 2
C441
4.7P_0402_50V8C
@1
2
T58 P AD
T59P AD
R342
10_0402_5%
@
12
RP27
10K_1206_8P4R_5%
1 82 73 64 5
T57P AD
R74810K_0402_5%
12
R371 8.2K_0402_5%1 2
R349 8.2K_0402_5%1 2
R363453_0402_1%
12
R378 10K_0402_5%1 2
R381 8.2K_0402_5%1 2
R225 0_0402_5%1 2
C817 0.1U_0402_16V4Z 1 2
R364 8.2K_0402_5%1 2
R382 24.9_0402_1%1 2
R417 15_0402_5%
1 2
C442
0.1
U_
04
02
_16
V4Z
1
2
R345 0_0402_5%1 2
SMB
SYS / GPIO
GPIO
MISC
Controller Link
Power MGT
clocks
SATA
GPIO
U12C
ICH9-M ES_FCBGA676
SMBCLKG16
SMBDATAA13
LINKALERT#/GPIO60/CLGPIO4E17
SMLINK0C17
SMLINK1B18
RI#F19
SUS_STAT#/LPCPD#R4
SYS_RESET#G19
PMSYNC#/GPIO0M6
SMBALERT#/GPIO11A17
WAKE#E20
SERIRQM5
THRM#AJ23
VRMPWRGDD21
GPIO8A21
GPIO18K1
GPIO20AF8
SCLOCK/GPIO22AJ22
SATACLKREQ#/GPIO35L1
SLOAD/GPIO38AE19
SDATAOUT0/GPIO39AG22
SDATAOUT1/GPIO48AF21
GPIO49AH24
GPIO57/CLGPIO5A8
SPKRM7
MCH_SYNC#AJ24
TP3B21
SATA0GP/GPIO21 AH23
SATA1GP/GPIO19 AF19
SATA4GP/GPIO36 AE21
SATA5GP/GPIO37 AD20
CLK14 H1
CLK48 AF3
SUSCLK P1
SLP_S3# C16
SLP_S4# E16
SLP_S5# G17
S4_STATE#/GPIO26 C10
PWROK G20
DPRSLPVR/GPIO16 M2
BATLOW# B13
PWRBTN# R3
LAN_RST# D20
RSMRST# D22
CK_PWRGD R5
CLPWROK R6
SLP_M# B16
CL_CLK0 F24
CL_CLK1 B19
CL_DATA0 F22
CL_DATA1 C19
CL_VREF0 C25
CL_VREF1 A19
CL_RST0# F21
CL_RST1# D18
MEM_LED/GPIO24 A16
WOL_EN/GPIO9 C20
STP_PCI#A14
STP_CPU#E19
CLKRUN#L4
GPIO12C12
GPIO1AG19
GPIO6AH21
GPIO7AG21
GPIO13C21
GPIO17AE18
GPIO27A9
GPIO28D19
TP8AH20
TP9AJ20
TP10AJ21
GPIO10/SUS_PWR_ACK C18
GPIO14/AC_PRESENT C11
TP11A20
R343
10_0402_5%
@
12
C440
4.7P_0402_50V8C
@ 1
2
R383 0_0402_5%1 2
R374 10K_0402_5%1 2
C816 0.1U_0402_16V4Z 1 2
R34010K_0402_5%@
12
R366 1K_0402_5% @ 1 2R367
3.24K_0402_1%
1 2
R369 10K_0402_5%1 2
C445 0.1U_0402_16V4Z
2MiniC@
1 2
C451 0.1U_0402_16V4Z
NewC@
1 2
C449 0.1U_0402_16V4Z 1 2
R355 10K_0402_5%1 2
R341 8.2K_0402_5%1 2
R33910K_0402_5%
@
12
R331 2.2K_0402_5%1 2
R348 0_0402_5%1 2
R344 8.2K_0402_5%1 2
R372 1K_0402_5%1 2
C450 0.1U_0402_16V4Z
NewC@
1 2
R376 10K_0402_5%1 2
R354 100_0402_5% 1 2
T46P ADR360
3.24K_0402_1%
1 2R362 8.2K_0402_5%
1 2
R336 8.2K_0402_5%@ 1 2
R357 8.2K_0402_5%1 2
T47P AD
R332 2.2K_0402_5%1 2
R358 8.2K_0402_5%1 2
R335 10K_0402_5%1 2
C443
0.1
U_
04
02
_16
V4Z
1
2
R356 8.2K_0402_5%1 2
R416 15_0402_5%
1 2
C448 0.1U_0402_16V4Z 1 2
R361 8.2K_0402_5%1 2
R375 10K_0402_5%1 2
R337 10K_0402_5%@1 2
R350 8.2K_0402_5%1 2
R429 10K_0402_5%1 2
R74510K_0402_5%@
12
R334 8.2K_0402_5%1 2
R379 10K_0402_5%1 2
R338 8.2K_0402_5%@1 2
R333 10K_0402_5%1 2
R377 10K_0402_5%1 2
C452 0.1U_0402_16V4Z 1 2
R346 10K_0402_5%1 2
R370
100K_0402_5%
12
PCI - Express
Direct Media Interface
SPI
USB
U12D
ICH9-M ES_FCBGA676
DMI0RXN V27
DMI0RXP V26
DMI0TXN U29
DMI0TXP U28
DMI1RXN Y27
DMI1RXP Y26
DMI1TXN W29
DMI1TXP W28
DMI2RXN AB27
DMI2RXP AB26
DMI2TXN AA29
DMI2TXP AA28
DMI3RXN AD27
DMI3RXP AD26
DMI3TXN AC29
DMI3TXP AC28
DMI_CLKN T26
DMI_CLKP T25
DMI_ZCOMP AF29
DMI_IRCOMP AF28
USBP0N AC5
USBP0P AC4
USBP1N AD3
USBP1P AD2
USBP2N AC1
USBP2P AC2
USBP3N AA5
USBP3P AA4
USBP4N AB2
USBP4P AB3
USBP5N AA1
USBP5P AA2
USBP6N W5
USBP6P W4
USBP7N Y3
USBP7P Y2
USBP8N W1
USBP8P W2
USBP9N V2
USBP9P V3
USBP10N U5
USBP10P U4
USBP11N U1
USBP11P U2
PERN1N29
PERP1N28
PETN1P27
PETP1P26
PERN2L29
PERP2L28
PETN2M27
PETP2M26
PERN3J29
PERP3J28
PETN3K27
PETP3K26
PERN4G29
PERP4G28
PETN4H27
PETP4H26
PERN5E29
PERP5E28
PETN5F27
PETP5F26
PERN6/GLAN_RXNC29
PERP6/GLAN_RXPC28
PETN6/GLAN_TXND27
PETP6/GLAN_TXPD26
SPI_CLKD23
SPI_CS0#D24
SPI_CS1#GPIO58/CLGPIO6F23
SPI_MOSID25
SPI_MISOE23
OC0#/GPIO59N4
OC1#/GPIO40N5
OC2#/GPIO41N6
OC3#/GPIO42P6
OC4#/GPIO43M1
OC5#/GPIO29N2
OC6#/GPIO30M4
OC7#/GPIO31M3
OC8#/GPIO44N3
OC9#/GPIO45N1
OC10#/GPIO46P5
OC11#/GPIO47P3
USBRBIASAG2
USBRBIAS#AG1
R351 8.2K_0402_5%1 2
RP28
10K_1206_8P4R_5%
1 82 73 64 5
R399 10K_0402_5%1 2
R7390_0402_5%1 2
R74610K_0402_5%
12
R359 10K_0402_5%1 2
R74710K_0402_5%@
12
R373 10K_0402_5%1 2
RP29
10K_1206_8P4R_5%
1 82 73 64 5
R353100K_0402_5%
1 2
R226 0_0402_5%@ 1 2
R368453_0402_1%
12
R352 8.2K_0402_5%1 2
C453 0.1U_0402_16V4Z 1 2
R38422.6_0402_1%
12
R380 8.2K_0402_5%1 2
R430 10K_0402_5%1 2
C444 0.1U_0402_16V4Z
2MiniC@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH _V5REF_SUS
V CCC L1_05_ICH
ICH _V5REF_SUS
V CC SUS1_5_ICH_2
ICH_V 5 REF_RUN
V CC_LAN1_05_INT_ICH_1V CC_LAN1_05_INT_ICH_2
V CC SUS1_5_ICH_1
ICH_V 5 REF_RUN
+RT CVCC
+1.5VS
+3VS
+1.5VS
+5VS +3VS
+3VALW+5VALW
+1.5VS
+3VALW
+V CCP
+3VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+3VS
+1.5VS+1.5VS
+VCCP
+V CCP
+3VS
+1.5VS
+3VALW
+3VS
+3VALW
+1.5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
ICH9(4/4)_POWER&GNDCus tom
23 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
20 mils
20 mils
1634mA2mA
G3: 6uA
646mA
2mA
47mA
1342mA
11mA
1mA
19/73/73mA19/78/78mA
212mA
11mA
11mA
308mA
23mA
48mA
2mA
11mA
40 mils
0316 change design
0316 change design
23mA
80mA
(DMI)
20 mils
+1.5VALW
C4
69
0.1
U_
04
02
_16V
4Z
1
2
R390 CHB1608U301_06031 2
C4
77
10
U_
08
05
_10V
4Z
1
2 T67
R387
CHB1608U301_06031 2
C4
66
4.7
U_
06
03
_6
.3V6M
1
2
C481
1U_0603_10V4Z
1
2
CORE
VCCP_CORE
PCI
VCCPSUS
VCCPUSB
GLAN POWER
USB CORE
ATX
ARX
VCCA3GP
U12F
ICH9-M ES_FCBGA676
VCCRTCA23
V5REFA6
V5REF_SUSAE1
VCC1_5_B[01]AA24
VCC1_5_B[02]AA25
VCC1_5_B[03]AB24
VCC1_5_B[04]AB25
VCC1_5_B[05]AC24
VCC1_5_B[06]AC25
VCC1_5_B[07]AD24
VCC1_5_B[08]AD25
VCC1_5_B[09]AE25
VCC1_5_B[10]AE26
VCC1_5_B[11]AE27
VCC1_5_B[12]AE28
VCC1_5_B[13]AE29
VCC1_5_B[14]F25
VCC1_5_B[15]G25
VCC1_5_B[16]H24
VCC1_5_B[17]H25
VCC1_5_B[18]J24
VCC1_5_B[19]J25
VCC1_5_B[20]K24
VCC1_5_B[21]K25
VCC1_5_B[22]L23
VCC1_5_B[23]L24
VCC1_5_B[24]L25
VCC1_5_B[25]M24
VCC1_5_B[26]M25
VCC1_5_B[27]N23
VCC1_5_B[28]N24
VCC1_5_B[29]N25
VCC1_5_B[30]P24
VCC1_5_B[31]P25
VCC1_5_B[32]R24
VCC1_5_B[33]R25
VCC1_5_B[34]R26
VCC1_5_B[35]R27
VCC1_5_B[36]T24
VCC1_5_B[37]T27
VCC1_5_B[38]T28
VCC1_5_B[39]T29
VCC1_5_B[40]U24
VCC1_5_B[41]U25
VCC1_5_B[42]V24
VCC1_5_B[43]V25
VCC1_5_B[44]U23
VCC1_5_B[45]W24
VCC1_5_B[46]W25
VCC1_5_B[47]K23
VCC1_5_B[48]Y24
VCC1_5_B[49]Y25
VCCSATAPLLAJ19
VCC1_5_A[01]AC16
VCC1_5_A[02]AD15
VCC1_5_A[03]AD16
VCC1_5_A[04]AE15
VCC1_5_A[05]AF15
VCC1_5_A[06]AG15
VCC1_5_A[07]AH15
VCC1_5_A[08]AJ15
VCC1_5_A[09]AC11
VCC1_5_A[10]AD11
VCC1_5_A[11]AE11
VCC1_5_A[12]AF11
VCC1_5_A[13]AG10
VCC1_5_A[14]AG11
VCC1_5_A[15]AH10
VCC1_5_A[16]AJ10
VCC1_5_A[17]AC9
VCC1_5_A[18]AC18
VCC1_5_A[19]AC19
VCC1_5_A[20]AC21
VCC1_5_A[21]G10
VCC1_5_A[22]G9
VCC1_5_A[23]AC12
VCC1_5_A[24]AC13
VCC1_5_A[25]AC14
VCCUSBPLLAJ5
VCC1_5_A[26]AA7
VCC1_5_A[27]AB6
VCC1_5_A[28]AB7
VCC1_5_A[29]AC6
VCC1_5_A[30]AC7
VCCLAN1_05[1]A10
VCCLAN1_05[2]A11
VCCLAN3_3[1]A12
VCCLAN3_3[2]B12
VCCGLANPLLA27
VCCGLAN1_5[1]D28
VCCGLAN1_5[2]D29
VCCGLAN1_5[3]E26
VCCGLAN1_5[4]E27
VCCGLAN3_3A26
VCC1_05[01] A15
VCC1_05[02] B15
VCC1_05[03] C15
VCC1_05[04] D15
VCC1_05[05] E15
VCC1_05[06] F15
VCC1_05[07] L11
VCC1_05[08] L12
VCC1_05[09] L14
VCC1_05[10] L16
VCC1_05[11] L17
VCC1_05[12] L18
VCC1_05[13] M11
VCC1_05[14] M18
VCC1_05[15] P11
VCC1_05[16] P18
VCC1_05[17] T11
VCC1_05[18] T18
VCC1_05[19] U11
VCC1_05[20] U18
VCC1_05[21] V11
VCC1_05[22] V12
VCC1_05[23] V14
VCC1_05[24] V16
VCC1_05[25] V17
VCC1_05[26] V18
VCCDMIPLL R29
VCC_DMI[1] W23
VCC_DMI[2] Y23
V_CPU_IO[1] AB23
V_CPU_IO[2] AC23
VCC3_3[01] AG29
VCC3_3[02] AJ6
VCC3_3[07] AC10
VCC3_3[03] AD19
VCC3_3[04] AF20
VCC3_3[05] AG24
VCC3_3[06] AC20
VCC3_3[08] B9
VCC3_3[09] F9
VCC3_3[10] G3
VCC3_3[11] G6
VCC3_3[12] J2
VCC3_3[13] J7
VCC3_3[14] K7
VCCHDA AJ4
VCCSUSHDA AJ3
VCCSUS1_05[1] AC8
VCCSUS1_05[2] F17
VCCSUS1_5[1] AD8
VCCSUS1_5[2] F18
VCCSUS3_3[01] A18
VCCSUS3_3[02] D16
VCCSUS3_3[03] D17
VCCSUS3_3[04] E22
VCCSUS3_3[05] AF1
VCCSUS3_3[06] T1
VCCSUS3_3[07] T2
VCCSUS3_3[08] T3
VCCSUS3_3[09] T4
VCCSUS3_3[10] T5
VCCSUS3_3[11] T6
VCCSUS3_3[12] U6
VCCSUS3_3[13] U7
VCCSUS3_3[14] V6
VCCSUS3_3[15] V7
VCCSUS3_3[16] W6
VCCSUS3_3[17] W7
VCCSUS3_3[18] Y6
VCCSUS3_3[19] Y7
VCCSUS3_3[20] T7
VCCCL1_05 G22
VCCCL1_5 G23
VCCCL3_3[1] A24
VCCCL3_3[2] B24
C4
62
0.1
U_
04
02
_16
V4Z
1
2
C473
0.1U_0402_16V4Z
1
2
C487
10
U_
08
05
_10V
4Z
1
2
C482
4.7U_0603_6.3V6M
1
2
C460
10U_0805_10V4Z
1
2
C4
67
0.1
U_
04
02
_1
6V4Z
1
2
C4
79
0.1U_0402_16V4Z1
2
R385
CHB1608U301_06031 2
C475
0.1U_0402_16V4Z
1
2
C4861U_0603_10V4Z
@ 1
2
C463
10U_0805_10V4Z
1
2
+
C4
58
22
0U
_D
2_
4VM
1
2
C4
68
0.1
U_
04
02
_1
6V4Z
1
2
C457
0.1U_0402_16V4Z1
2
T68
R2120_0402_5%
@
12
C464
22
U_
08
05
_6
.3VA
M
1
2
R386
100_0402_5%
12
C461
0.01U_0402_16V7K
1
2
C459
10U_0805_10V4Z
1
2
T71
C484
0.1U_0402_16V4Z
1
2
C478
1U_0603_10V4Z
1
2
C4
80
0.1
U_
04
02
_16V
4Z
1
2
R391
CHB1608U301_0603
1 2
C472
0.1U_0402_10V6K
1
2
C4
70
0.1
U_
04
02
_16V
4Z
1
2
T65
C483
0.1U_0402_16V4Z
1
2
U12E
ICH9-M ES_FCBGA676
VSS[107] H5
VSS[108] J23
VSS[109] J26
VSS[110] J27
VSS[111] AC22
VSS[112] K28
VSS[113] K29
VSS[114] L13
VSS[115] L15
VSS[116] L2
VSS[117] L26
VSS[118] L27
VSS[119] L5
VSS[120] L7
VSS[121] M12
VSS[122] M13
VSS[123] M14
VSS[124] M15
VSS[125] M16
VSS[126] M17
VSS[127] M23
VSS[128] M28
VSS[129] M29
VSS[130] N11
VSS[131] N12
VSS[132] N13
VSS[133] N14
VSS[134] N15
VSS[135] N16
VSS[136] N17
VSS[137] N18
VSS[138] N26
VSS[139] N27
VSS[140] P12
VSS[141] P13
VSS[142] P14
VSS[143] P15
VSS[144] P16
VSS[145] P17
VSS[146] P2
VSS[147] P23
VSS[148] P28
VSS[149] P29
VSS[150] P4
VSS[151] P7
VSS[152] R11
VSS[153] R12
VSS[154] R13
VSS[155] R14
VSS[156] R15
VSS[157] R16
VSS[158] R17
VSS[159] R18
VSS[160] R28
VSS[161] T12
VSS[162] T13
VSS[163] T14
VSS[164] T15
VSS[165] T16
VSS[166] T17
VSS[167] T23
VSS[168] B26
VSS[169] U12
VSS[170] U13
VSS[171] U14
VSS[172] U15
VSS[173] U16
VSS[174] U17
VSS[175] AD23
VSS[176] U26
VSS[177] U27
VSS[178] U3
VSS[179] V1
VSS[180] V13
VSS[181] V15
VSS[182] V23
VSS[183] V28
VSS[184] V29
VSS[185] V4
VSS[186] V5
VSS[187] W26
VSS[188] W27
VSS[189] W3
VSS[190] Y1
VSS[191] Y28
VSS[192] Y29
VSS[193] Y4
VSS[194] Y5
VSS[195] AG28
VSS[196] AH6
VSS[197] AF2
VSS[198] B25
VSS_NCTF[01] A1
VSS_NCTF[02] A2
VSS_NCTF[03] A28
VSS_NCTF[04] A29
VSS_NCTF[05] AH1
VSS_NCTF[06] AH29
VSS_NCTF[07] AJ1
VSS_NCTF[08] AJ2
VSS_NCTF[09] AJ28
VSS_NCTF[10] AJ29
VSS_NCTF[11] B1
VSS_NCTF[12] B29
VSS[001]AA26
VSS[002]AA27
VSS[003]AA3
VSS[004]AA6
VSS[005]AB1
VSS[006]AA23
VSS[007]AB28
VSS[008]AB29
VSS[009]AB4
VSS[010]AB5
VSS[011]AC17
VSS[012]AC26
VSS[013]AC27
VSS[014]AC3
VSS[015]AD1
VSS[016]AD10
VSS[017]AD12
VSS[018]AD13
VSS[019]AD14
VSS[020]AD17
VSS[021]AD18
VSS[022]AD21
VSS[023]AD28
VSS[024]AD29
VSS[025]AD4
VSS[026]AD5
VSS[027]AD6
VSS[028]AD7
VSS[029]AD9
VSS[030]AE12
VSS[031]AE13
VSS[032]AE14
VSS[033]AE16
VSS[034]AE17
VSS[035]AE2
VSS[036]AE20
VSS[037]AE24
VSS[038]AE3
VSS[039]AE4
VSS[040]AE6
VSS[041]AE9
VSS[042]AF13
VSS[043]AF16
VSS[044]AF18
VSS[045]AF22
VSS[046]AH26
VSS[047]AF26
VSS[048]AF27
VSS[049]AF5
VSS[050]AF7
VSS[051]AF9
VSS[052]AG13
VSS[053]AG16
VSS[054]AG18
VSS[055]AG20
VSS[056]AG23
VSS[057]AG3
VSS[058]AG6
VSS[059]AG9
VSS[060]AH12
VSS[061]AH14
VSS[062]AH17
VSS[063]AH19
VSS[064]AH2
VSS[065]AH22
VSS[066]AH25
VSS[067]AH28
VSS[068]AH5
VSS[069]AH8
VSS[070]AJ12
VSS[071]AJ14
VSS[072]AJ17
VSS[073]AJ8
VSS[074]B11
VSS[075]B14
VSS[076]B17
VSS[077]B2
VSS[078]B20
VSS[079]B23
VSS[080]B5
VSS[081]B8
VSS[082]C26
VSS[083]C27
VSS[084]E11
VSS[085]E14
VSS[086]E18
VSS[087]E2
VSS[088]E21
VSS[089]E24
VSS[090]E5
VSS[091]E8
VSS[092]F16
VSS[093]F28
VSS[094]F29
VSS[095]G12
VSS[096]G14
VSS[097]G18
VSS[098]G21
VSS[099]G24
VSS[100]G26
VSS[101]G27
VSS[102]G8
VSS[103]H2
VSS[104]H23
VSS[105]H28
VSS[106]H29
C488
2.2
U_
06
03
_6
.3V
4Z
1
2
R388
10_0402_5%
12
R389
CHB1608U301_06031 2
C4
54
0.1
U_
04
02
_16
V4Z
1
2
R741150_0402_1%
12
T69
C4
71
0.1
U_
04
02
_16V
4Z
1
2
C455
0.1U_0402_16V4Z1
2
C456
2.2U_0603_6.3V4Z
1
2
C465
0.1U_0402_10V6K
1
2
T66
C4
76
1U
_0
60
3_
10V
4Z
1
2
C489
4.7U_0805_10V4Z
1
2
D9
CH751H-40_SC76
21
T70
D10
CH751H-40_SC76
21
C485
0.1
U_
04
02
_1
6V4Z 1
2
R740180_0402_1%1 2 C474
0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SATA_RXP0 SATA_RXP0_C
SATA_TXN0
SATA_RXN0_C
SATA_TXP0
SATA_RXN0
SATA_RXP4SATA_RXN4
SATA_TXP4
SATA_RXN4_CSATA_RXP4_C
SATA_TXN4
IC H_SMBCLK
ICH_SMBDATA
ICH_SMBDATA
G _CS#
IC H_SMBCLK
A CCEL_INT
SATA_RXN1 SATA_RXN1_CSATA_RXP1 SATA_RXP1_C
SATA_TXP1SATA_TXN1
SATA_RXN0_C <21>SATA_RXP0_C <21>
SATA_TXN0 <21>SATA_TXP0 <21>
SATA_RXN4_C <21>
SATA_TXN4 <21>SATA_TXP4 <21>
SATA_RXP4_C <21>
ICH_SMBDATA <17,22,26>
ICH_SMBCLK <17,22,26>
A CCEL_INT <20>
SATA_RXN1_C <21>SATA_RXP1_C <21>
SATA_TXP1 <21>SATA_TXN1 <21>
+3VS_HDD1
+5VS
+5VS
+5VS
+5VS
+3VS_HDD1
+3VS
+5VS
+3VS_ACL+3VS +3VS_ACL_IO
+3VS_ACL_IO
+3VS_ACL
+3VS_ACL
+3VS_ACL+3VS_ACL_IO
+3VS_ACL
+5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
HDD & CDROMCus tom
24 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Near CONN side.
Near CONN side.
HDD Connector
CD-ROM Connector
Placea caps. near ODD CONN.
Pleace near HDD CONN (JP3)
Pleace near HDD CONN
Multi Bay
Placea caps. near Multi Bay CONN.
ACCELEROMETER (ST)
0011101b
Must be placed in the center of the system.
VDDIO absolute manrating is VDD+0.1
ACCELEROMETER (Bosch)
C822 0.01U_0402_16V7K
Multi@
12
C7
13
0.1
U_
04
02
_1
6V4Z
GS
@
1
2
C4950.01U_0402_16V7K
12
C498
1U
_0
60
3_
10V
4Z
@1
2
C5100.01U_0402_16V7K
12
C300
10
U_
08
05
_10
V4Z
Multi@
1
2
C823 0.01U_0402_16V7K
Multi@
12
C497
0.1
U_
04
02
_1
6V4Z
@1
2
C4940.01U_0402_16V7K
12
R571 10K_0402_5%@1 2
C5110.01U_0402_16V7K
12
C297
0.1
U_
04
02
_1
6V4Z
Multi@
1
2
C4
90
10
U_
08
05
_10
V4Z
1
2
JP5
SUYIN_127382FR013GX09ZRC ONN@
GND 13
A+ 12
A- 11
GND 10
B- 9
B+ 8
GND 7
DP 6
V5 5
V5 4
MD 3
GND 2
GND 1
C496
10
00
P_
040
2_50
V7K
@1
2
Z ZZ2
PCB-MB
U29
LIS302DLTR_LGA14_3x5
GS@
SC
L / S
PC
14
GND2
Reserved3
GND4
GND5
CS
7
Vdd_IO1
Vdd6
SDA / SDI / SDO 13
SDO 12
Reserved 11
GND 10
INT 2 9
INT 1 8
C298
1U
_0
60
3_
10V
4Z
Multi@
1
2
C491
0.1
U_
04
02
_1
6V4Z
1
2
JP3
SUYIN_127072FR022G523_RVC ONN@
GND 1
A+ 2
A- 3
GND 4
B- 5
B+ 6
GND 7
V33 8
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14
V5 15
V5 16
GND 17
Reserved 18
GND 19
V12 20
V12 21
V12 22
D23
CH751H-40PT_SOD323-2
GS@
2 1
C515
10
U_
08
05
_10
V4Z
1
2
C493
0.1
U_
04
02
_1
6V4Z
1
2
JP12
TYCO_2023087C ONN@
GND 1
VCC515VCC516
TX- 3TX+ 2
VCC514
GND 4VCC313
RX- 5VCC312
RX+ 6VCC311
GND 7GND10
GND 8GND9
GND 17GND18
BMA150U14
BMA150_LGA12
@
RSVD 1
VDD 2
GND 3
INT4
CSB5
SCK6
SDO7
SDI8
VDDIO 9
RSVD 10
RSVD 11
RSVD 12
C299
10
U_
08
05
_10
V4Z
Multi@
1
2
C513
1U
_0
60
3_
10V
4Z
1
2
R392
0_0805_5%
@1 2
C492
0.1
U_
04
02
_1
6V4Z
1
2
R5700_0402_5%
GS@
1 2
C514
10
U_
08
05
_10
V4Z
1
2
R5640_0603_5%
GS@
1 2
R569 10K_0402_5%GS@12
C5120
.1U
_0
40
2_
16V
4Z
1
2
R5680_0402_5%
GS@
1 2
C7
14
10
U_
08
05
_6
.3V
6M
GS
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
L AN_CS
LA N_DI
LAN_ACTIVITY#
L AN_MDI1-
L AN_MDI0+
ISOLATEB
LAN_X2LAN_X1
ISOLATEB
PCIE_PTX_IRX_P2
PCIE_PTX_IRX_N2
LA N_DOLA N_DILAN_SK_LAN_LINK#L AN_CS
LAN_SK_LAN_LINK#
LA NG ND
RJ 45_MIDI1-
RJ 45_MIDI0+
LAN_ACTIVITY#
RJ 45_MIDI1+
RJ 45_MIDI0-
L AN_MDI1+
RJ45_CT0L AN_MDI0-L AN_MDI0+
LAN_CT1
R J45_CT0_C
RJ 45_MIDI0+
LAN_CT0
RJ45 _GND
RJ 45_MIDI1-
R J45_CT1_C
RJ 45_MIDI1+RJ45_CT1
L AN_MDI1-
RJ 45_MIDI0-
LAN_X2LAN_X1
VCTRL12
L AN_MDI0-
LA N_DO
LAN_SK_LAN_LINK#
VCTRL12
L AN_MDI1+
GLAN_TXP<22>
GLAN_TXN<22>
CLK_PCIE_LAN#<17>CLK_PCIE_LAN<17>
CLKREQ#_9<17>
PLT_RST#<9,20,26,27>
ICH_PCIE_WAKE#<22,26>
GLAN_RXP<22>
GLAN_RXN<22>
LA N_POWER_OFF<32>
RJ45_MIDI0+ <34>
RJ45_MIDI1+ <34>
RJ45_MIDI0- <34>
RJ45_MIDI1- <34>
+3V_LAN
+LAN_VDD12
+EVDD12
+EVDD12
+LAN_VDD12+3VS
+LAN_VDD12
+3V_LAN
+3V_LAN
+3V_LAN
+3VALW
+3V_LAN
+3V_LAN
+3V_LAN
+LAN_VDD12
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered DateCompal Electronics, Inc.
Montevina Blade UMA LA4101P 0.3
RTL8102EL LAN
Cus tom
25 46Saturday, January 05, 2008
2007/08/28 2007/06/30
Close to Pin1,37,29
Close to Pin45Close to Pin19
Place Close to Chip
40 mils
LAN Conn.
10/29 update
Change the PCB Footprint fromY_KDS_1BX25000CK1A_2P toY_6X25000017_2P
10/09 update
Close to Pin10,13,30,36
Close to Pin48
Check??
C253
0.1
U_
04
02
_1
6V4Z
1
2
R21615K_0402_5%
R69375_0402_1%
1 2
RTL8102EL
U44
RTL8102EL-GR_LQFP48_7X7
AVDD33 1
MDIP0 2
MDIN0 3
NC 4
MDIP1 5
MDIN1 6
GND7
NC 8
NC 9
DVDD12 10
NC 11
NC 12
RSET46
VCTRL12A 48
GND47
CKXTAL242CKXTAL141
NC 40
NC 44
LED0 38
VDD33 37
NC 43
DVDD12 13
GND14
HSIP15
HSIN16
REFCLK_P17
REFCLK_M18
VDDTX 19
HSOP20
HSON21
GNDTX22
NC23
NC24
LED1/EESK 35LED2/EEDI/AUX 34LED3/EEDO 33
EECS 32
DVDD12 36
GND31
DVDD12 30
VDD33 29
ISOLATEB28
PERSTB27
LANWAKEB26
CLKREQB25
NC 39
VCTRL12D 45
C244
27P_0402_50V8J
1
2
C265
10
U_
08
05
_10
V4Z
@ 1
2
R697 300_0402_5%12
C261
0.1
U_
04
02
_1
6V4Z
1
2
R69475_0402_1%
1 2
U45
AT93C46-10SI-2.7_SO8
CS1SK2 DI3DO4
VCC 8NC 7NC 6
GND 5
R2151K_0402_1%
12
C245
27P_0402_50V8J
1
2
C250
0.1
U_
04
02
_1
6V4Z
1
2
C255
0.1U_0402_16V4Z
@
1
2
C26868P_0402_50V8K@
1
2
PJP4
P AD-OPEN 4x4m
1 2
C254
0.1
U_
04
02
_1
6V4Z
1
2
C2560.1U_0402_16V4Z
1
2
C266
1U
_0
40
2_
6.3
V4Z
1
2
C248 0.01U_0402_16V7K
1 2
R695 3.6K_0402_5%1 2
C259
1000P_1206_2KV7K
1
2
R218 10K_0402_5%
1 2
C26968P_0402_50V8K
@
1
2
C257 0.01U_0603_100V7-M
1 2
C264
0.1
U_
04
02
_1
6V4Z
1
2
C240 0.1U_0402_16V7K 12
C247 0.01U_0402_16V7K
1 2
C262
10
U_
08
05
_10
V4Z
@ 1
2
C258 0.01U_0603_100V7-M
1 2
R698 300_0402_5%12
C241 0.1U_0402_16V7K 12
G
DS
Q19SI2301BDS-T1-E3_SOT23-3
2
13
C251
0.1
U_
04
02
_1
6V4Z
1
2
R688 2.49K_0402_1%1 2
U46
LEF8423A-R
RD+1
RD-2
CT3
CT6
TD+7
TD-8 TX- 9TX+ 10CT 11
CT 14RX- 15RX+ 16
NC4
NC5NC 13
NC 12
C272
4.7U_0805_10V4Z
1
2
JRJ45
FOX_JM36113-P1122-7FC ONN@
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Green LED-12
Green LED+11
Yellow LED-14
Yellow LED+13
SHLD1 15
SHLD1 16
DETECT PIN1 9
DETCET PIN2 10
C249
0.1
U_
04
02
_1
6V4Z
1
2R696 10K_0402_5%
12
Y3
25MHz_20pF_6X25000017
12
C263
0.1
U_
04
02
_1
6V4Z
1
2
C271
0.1U_0402_16V4Z
1
2
C252
0.1
U_
04
02
_1
6V4Z
1
2
C267
0.1
U_
04
02
_1
6V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XMIT_OFF#PLT_RST#
IC H_SMBCLKICH_SMBDATA
XMIT_OFF#
CLKREQ#_4
PCIE_PME#_R
PERST#
EXP_CPPE#
EXP_CPPE#
USB9-
IC H_SMBCLKICH_SMBDATA
USB9+
M_WXMIT_OFF#
CLKREQ#_10
C H_DATA
M_WXMIT_OFF#
CH_ CLK
P CIE_C_RXN1
ICH_SMBDATA
PCIE_C_RXP1
IC H_SMBCLK
PLT_RST#
IC H_PCIE_WAKE#
CL K_PCIE_MCARD2#CL K_PCIE_MCARD2
PCIE_C_RXP3P CIE_C_RXN3
CLKREQ#_6CH_ CLK
PCIE_TXN3PCIE_TXP3
C H_DATAIC H_PCIE_WAKE#
EXP_CPPE#
PLT_RST#
PERST#
SUSP#
S Y SON
U IM_RST
UIM _PWRUIM_DATAUI M_CLK
UIM_VPP
U IM_RST
UIM _PWRUIM_DATAUI M_CLK
UIM_VPP
PCIE_TXN1PCIE_TXP1
UIM_DATA
UI M_CLK
PLT_RST#
UIM _PWR
CLK _PCIE_NCARD<17>
ICH_PCIE_WAKE#<22,25>
ICH_SMBDATA<17,22,24>ICH_SMBCLK<17,22,24>
USB20_P9<22>USB20_N9<22>
PCIE_TXN4<22>PCIE_TXP4<22>
PCIE_RXP4<22>PCIE_RXN4<22>
WXMIT_OFF#<22>
CLK_PCIE_MCARD0<17>
PCIE_RXN1<22>PCIE_RXP1<22>
CLK_PCIE_MCARD0#<17>
CLK _PCIE_NCARD#<17>
CLKREQ#_10<17>CLKREQ#_6<17>
CLK_PCIE_MCARD2<17>
PCIE_TXN3<22>PCIE_TXP3<22>
PCIE_RXP3<22>PCIE_RXN3<22>
CH_CLK<30>CH_DATA<30>
CLK_PCIE_MCARD2#<17>
CLKREQ#_4<17>
PLT_RST#<9,20,25,27>
S Y S ON<32,33,36,41>
SUSP#<28,32,36,38,40,41>
LPC_FRAME# <21,31,32>LPC_AD3 <21,31,32>LPC_AD2 <21,31,32>
LPC_AD0 <21,31,32>LPC_AD1 <21,31,32>
WL_LED# <33>
USB20_P5 <22>USB20_N5 <22>USB20_P8 <22>
USB20_N8 <22>
EXP_CPPE#<22>
CLK_DEBUG_PORT_1<17>
PCIE_TXP1<22>PCIE_TXN1<22>
WWA N_POWER_OFF<32>
WW_LED# <33>
XMIT_OFF<22>
+3VS_WLAN
+3VALW
+3VALW
+3VALW
+3VS_WLAN
+3VS_PEC
+1.5VS_PEC
+3V_PEC
+3VS_PEC
+1.5VS_PEC
+3V_PEC
+1.5VS_PEC
+1.5VS_WLAN
+3VS_WLAN
+1.5VS_WLAN
+3VS_WLAN
+1.5VS_WLAN
+3VALW +3VS_WWAN
+3VS_WWAN
+3VS_WWAN
+3VS_WWAN
+3VS_WWAN
+1.5VS_WLAN
+3VALW
+1.5VS_WLAN
+3VS_WLAN
+3VS_PEC
+3V_PEC
+1.5VS_PEC
+1.5VS
+3VALW
+3VALW
+3VS
+1.5VS_WLAN
+3VS +3VS_WLAN
+1.5VS
+1.5VS_WLAN
+3VALW+3VS_WWAN
+1.5VS_WLAN
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
WLAN, WWAN, New Card
26 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
Mini Card 2---WLANMini Card 0--TV tuner/WWAN/Robson
Close toJEXP
Near to Express Card slot.
0811 Pins 37 and 43 connect to GND and remove +1.5V S
0821 Change +3VS to +3VS_WWAN
New Card
internal pull high to 3.3Vaux-inEC need setting at Hi-Z & output Low
Express Card Power Switch
SIM card Connector
11/17 Reserve UIM_DATAPU to UIM_PWR
01/03 Prevent WLAN leakage
01/03 New card PTH connector GND
R437 0_0402_5%NewC@
1 2
D11
CH751H-40_SC762MiniC@
21
R702 0_0402_5% DE BUG@1 2
R421 0_0402_5%
2MiniC@
1 2
R431 0_0805_5%1 2
R43310K_0402_5%
@
12
C579 0.1U_0402_16V4ZNewC@
1 2
R703 0_0402_5% DE BUG@1 2
C568
0.1
U_
04
02
_1
6V4Z 1
2
C5760.1U_0402_16V4ZNewC@
1 2 C5770.1U_0402_16V4Z
NewC@
1
2
R4190_0402_5%
2MiniC@
1 2
R426 0_0402_5%@ 1 2
JEXP1
SANTA_130801-5_LTC ONN@
GND1
USB_D-2
USB_D+3
CPUSB#4
RSV5
RSV6
SMB_CLK7
SMB_DATA8
+1.5V9
+1.5V10
WAKE#11
+3.3VAUX12
PERST#13
+3.3V14
+3.3V15
CLKREQ#16
CPPE#17
REFCLK-18
REFCLK+19
GND20
PERn021
PERp022
GND23
PETn024
PETp025
GND26
GND27
GND28GND 29
GND 30 C5844.7U_0805_10V4ZNewC@
1
2
C5784.7U_0805_10V4ZNewC@
1
2
R439 100K_0402_5% 1 2
C5824.7U_0805_10V4ZNewC@
1
2
C5810.1U_0402_16V4Z
NewC@
1
2
D19
CH751H-40_SC76
21
R428 0_0603_5%
2MiniC@
1 2
C575
4.7U_0805_10V4Z
2MiniC@
1
2
G
D S
Q52AP2305GN2MiniC@
2
1 3
R427 0_0603_5%
2MiniC@
1 2
G
D
S
Q102N7002_SOT23-3
@2
13
R436 0_0402_5%NewC@
1 2
R434100K_0402_5%
@
12
R699 0_0402_5% DE BUG@1 2
C572
0.1
U_
04
02
_16
V4Z
2MiniC@
1
2
R424 0_0402_5%1 2
C566
0.1U_0402_16V4Z
1
2
C82418P_0402_50V8J
@1
2
R425 0_0402_5%1 2
JP4
ACES_88266-07001C ONN@
11
22
33
44
55
66
77G1 8
G2 9
C573
0.01U_0402_16V7K
2MiniC@
1
2
R700 0_0402_5% DE BUG@1 2
C574
0.1U_0402_16V4Z
2MiniC@
1
2
C570
0.1U_0402_16V4Z
1
2
R423 0_0402_5%1 2
R438
0_0402_5%NewC@
1 2
R750
47K_0402_5%
@1 2
C569
0.01U_0402_16V7K
1
2
R420 0_0402_5% @ 1 2
C571
4.7U_0805_10V4Z
1
2
U16
R5538D001-TR-F_QFN20_4X4~D
NewC@
3.3Vin2
3.3Vin43.3Vout 3
3.3Vout 5
SYSRST#6
SHDN#20
STBY#1
PERST# 8
OC# 19
RCLKEN18
AUX_IN17 AUX_OUT 15
CPPE#10
CPUSB#9
NC 16
GND 7
1.5Vin12
1.5Vin141.5Vout 11
1.5Vout 13
R418
0_1206_5%
@1 2
C5830.1U_0402_16V4Z
NewC@
1
2
R701 0_0402_5% DE BUG@1 2
C567
4.7U_0805_10V4Z
1
2 R432 0_0805_5%1 2
R422 0_0402_5%2MiniC@
1 2
JP6
FOX_AS0B226-S40N-7FC ONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
GND153
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
JP7
FOX_AS0B226-S40N-7FC ONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
GND153
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
R435
0_0402_5%1 2
C580 0.1U_0402_16V4ZNewC@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
P REXT
P C I E _ C_RXN5P C I E _C_RXP5
X D _RE#
X D _CLE
XDCD1#_MSCD#
X D C D 0 # _SDCD#
X D_ALEX D _RB#X D _RE#X D_D7X D_D6
X D_D4X D_D5
X D W P # _ SDWP#S D C L K _ MSCLK_XDCE#
X D _CLE
S D C MD _ MS BS_XDWE#
X D _ SD_MS_D1X D _ SD_MS_D2
X D _ SD_MS_D0
X D _ SD_MS_D3
X D C D 0 # _SDCD#X D C D 1 #_MSCD#
C R _ L ED#
X IN
X D C D 0 # _SDCD#X D C D 1 #_MSCD#
X D W P # _ SDWP#X D _RB#
X D CE#
S D C L KS D C L K _ MSCLK_XDCE#MS C LK
X D _ CD#
X D CE#
S D C L K
MS C LK
X D _ SD_MS_D3X D _ SD_MS_D2
X D _CLE
S D C MD _ MS BS_XDWE#
X D CE#
X D_D4X D_D5
X D_D7X D_D6
X D _ CD#X D_ALE
X D _ SD_MS_D0
X D _RB#
X D _ SD_MS_D1
X D W P # _ SDWP#
X D _RE#
C R _ L ED#
X D _ SD_MS_D0S D C L K
X D C D 0 # _SDCD#S D C MD _ MS BS_XDWE#
X D _ SD_MS_D3X D _ SD_MS_D2X D _ SD_MS_D1
X D _ SD_MS_D2X D _ SD_MS_D1X D _ SD_MS_D0MS C LK
X D W P # _ SDWP#
S D C MD _ MS BS_XDWE#X D C D 1 #_MSCD#X D _ SD_MS_D3
X D_D4X D_D5X D_D6X D_D7
X D_ALE
P C IE_TXN5<22>
P C I E_RXN5<22>
P CIE_TXP5<22>
P L T_RST#<9,20,25,26>
C L K _ SRC11#<17>C L K _ SRC11<17>
P C I E_RXP5<22>
C R _ W A KE#<22>
C R _ C P PE#<22>
+ 3VS
+ 3VS
+ 1 . 8VS_CR
+ 1 . 8VS_CR
+ 3VS
+ 3VS
+ V C C _OUT
+ 3VS
+ V C C _4IN1+ V C C _ OUT
+ V C C _4IN1
+ 1 . 8VS_CR + 1.8VS
+ V C C _4IN1
+ 5VS
+ V C C _4IN1+ V C C _OUT
+ 3VS
+ V C C _4IN1
Tit le
Size D o c u ment Number R e v
D a te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montev ina Blade UMA LA4101P 0 .3
USB CardReader&CONNC u s t om
27 46S a turday, January 05, 2008
2007/08/28 2006/10/06Compal Electronics, Inc.
reserved power circuit
40mil
Use 0603 type and over 20mils trace width on both side
use for PWR_EN#
8mA sink current
White LED: VF=3V, IF = 5mA, Res = 56ohm
Card Reader Connector
09/26 Must change P mos FET
09/26 (JMicron)recommend change to 0805 Size
09/26 (JMicron)recommend +VCC_OUT >30mil
09/26 (JMicron)recommend C1328/1000pF close to U36 pin5
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)
09/26 (JMicron)recommend place C1329/0.1uF near by C1328
09/26 (JMicron)recommend add atest point for pin 13 1、、、、 4
09/26 (JMicron)recommendwidth/length: 12mil /<250mil for PREXT signal(pin 7)
11/07 Change to 10K(vender)
11/07 Change to 8.2K(vender)
11/07 Stuff for JMB385 internal LDO
11/07 Don't stuff for JMB385 internal LDO
11/07 Change U37 correct PCBFootprint SOT23
11/07 BOM delete for JMB385 internal LDO
White
11/09 don't support DIM function
11/09 Add D18 for cardreader wake up
11/17 Update CIS library
01/03 Change Cardreader LED control
01/03 Change Cardreader LED control
C 788100P_0402_25V8K
@12
C 13261 0U_0805_10V4Z
1
2 C 13270 .1U_0402_16V4Z
1
2
U 3 7
G5250C2T1U_SOT23-5
@
IN3
EN4 OUT 1
OUT 5
GND2
C 1047270P_0402_50V7K
1
2
T78R 707100_0402_5%
@1 2
R 1944.7K_0402_5%
12
C 13330 .1U_0402_16V4Z
1
2
C 13360 .1U_0402_16V4Z
1
2
R 1042 4.7K_0402_5%
1 2
D 4 1
D A N 2 0 2U_SC70
2
31
C 13300 .1U_0402_16V4Z
1
2
R 402 8.2K_0402_5%1 2
R 1041 4.7K_0402_5%
1 2
R 972 10K_0402_5%1 2
C 13281000P_0402_50V7K
1
2
R 1050150K_0402_5%@
12
R 712 22_0402_5%1 2
G
D
S
Q1012N7002_SOT23-3 2
13
C 790100P_0402_25V8K
@1 2
R 1048 10K_0603_5%1 2
C 13320 .1U_0402_16V4Z
1
2
R 710 22_0402_5%1 2
R 404 0_0402_5%1 2
C 13340 .1U_0402_16V4Z
1
2
R 708100_0402_5%
@1 2
C 13250.1U_0805_50V7M
12
C 13350 .1U_0402_16V4Z
1
2
R 711 22_0402_5%1 2
R 1043 10K_0402_5%
12
R 1046 200K_0402_5%
1 2
C 789100P_0402_25V8K
@1 2
R 719470_0402_5%
12
C 132410U_0805_10V4Z
1
2
C 1322 0 .1U_0402_16V4Z12
R 1044 10K_0402_5%
12
D 15H T- F1 96BP5_WHITE
21
C 1321 0 .1U_0402_16V4Z12
R 7040_0603_5%1 2
R 706100_0402_5%
@12
C 13290 .1U_0402_16V4Z
1
2
JMB385
U 36
J MB 3 8 5 - L G EZ 0 A _ L Q F P4 8 _ 7 X7
XRSTN1
XTEST2
APCLKN3
APCLKP4 APVDD 5
APGND 6
APREXT7
APRXP8 APRXN9
APV18 10
APTXN11
APTXP12
SEEDAT13
SEECLK14
CR1_CD1N15
CR1_CD0N16
CR1_PCTLN17
DV18 18
DV33 19
DV33 20
CR1_LEDN21
MDIO14 22MDIO13 23
GND 24
MDIO12 25MDIO11 26MDIO10 27MDIO9 28MDIO8 29
TAV33 30
GND 31
GND 32
GND 33
NC 34
NC 35
NC 36
DV18 37
PCIES_EN38
PCIES39
MDIO7 40MDIO6 41MDIO5 42MDIO4 43
DV33 44
MDIO3 45MDIO2 46MDIO1 47MDIO0 48
R 7 05
0_0805_5%
@1 2
C 13311 U_0603_10V4Z
1
2
7 IN 1 CONN
J R E A D 1
T A IT W _ R 0 1 5 - B 1 0 - LMCONN@
XD-WP33
XD-D47
MS-DATA3 24
MS-DATA0 17
SD-DAT2 30
SD-DAT0 14
SD-CMD 25
MS-DATA1 15
XD-D65 SD-DAT3 29
SD-DAT1 12
XD-ALE35
XD-D032
SD_CLK 20
XD-D29
MS-INS 22
MS-DATA2 19
MS-SCLK 26
XD-RE38
MS-BS 13
XD-D56
XD-D74
XD-D110
XD-CE37
XD-R/B39
XD-D38
XD-WE34
MS-VCC 28
7IN1 GND11
XD-CLE36
7IN1 GND31
SD-VCC 21XD-VCC3
XD-CD40 SD-CD-SW 1
SD-WP-SW 2
7IN1 GND41
7IN1 GND42
SD-DAT4 27
SD-DAT5 23
SD-DAT6 18
SD-DAT7 16
D 1 8
C H 751H-40PT_SOD323-221
R 7 09 10K_0603_5%1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDA _S Y NC _CODEC
HDA _RST#_CODEC
MONO_ INR
MIC_EXTR
MIC_EXTLSENSEB#
V C_REFA
LINE_OUT_L
L I NE_OUT_R
VREFOUT_B
HDA _BITCLK_CODEC
E A P D_CODEC
SENSE
HDA _BITCLK_CODEC
HP_OUTL
HP _OUTR
HDA _S DOUT_CODEC
HDA _S DI N0_CODEC
MIC _INL
MIC_ I NR
DOC K_MICL
DOCK _ MICR DOCK _M ICR_C
DOCK _MICL_C
EC_BEEP
S PDIF_OUT
MIC_EXT_L <29>
MIC_EXT_R <29>
MIC_IN_L <29>
MIC_ IN_R <29>
SUSP#<26,32,36,38,40,41>
GNDA <29,34>
LINE_OUT_L <29>
L INE_OUT_R <29>
VREFOUT_B <29>
HDA _BITCLK_CODEC<21>
HDA _S DOUT_CODEC<21>
HDA _SDIN0<21>
HDA _S Y NC_CODEC<21>
HDA _RST#_CODEC<21,32>
SB_SPKR<22>
SENSE_B#<34>
E A P D_CODEC <32>
EXTMIC_DET# <29>JACK_DET# <29,34>
HP_OUTL <29>
HP _OUTR <29>
DMIC_CLK<19>
DMIC_DAT <19>
INTMIC_DET# <29>
DOCK_MIC_L <34>
DOCK _MIC_R <34>
EC_BEEP<32>
S PDIF_OUT <34>
+3VS +V DDA_CODEC
+3V DD_CODEC +5VALW +V DDA_CODEC
+1.5VS_HDA +1.5VS
+3V DD_CODEC
+1.5VS_HDA
+V DDA _CODEC_R
+V DDA _CODEC_R
+V DDA _CODEC_R
+V DDA _CODEC_R
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Codec_IDT9271B7
Cus tom
28 46S aturday, January 05, 2008
2007/08/28 2006/07/26
HP Jack & Dock
SENSE A SENSE B
Port Resistor Port Resistor
A 39.2K
B 20K
C 10K
D 5.11K
E
F
G
H
20K
39.2K
5.11K
10K
Internal SPKR.
Internal MIC
Jack MIC
CODEC POWER
GNDAGND
W=40Mil300mA
(4.75V(4.56~4.94V))
11/07 Stuff 0 Ohm for AGND and GND
11/07 Change R1059 39.2K
11/07 Change to 4.75V LDO
11/08 Change C1352 C135、、、、 4 (recommend)
DOCK MIC
1/10*Vinneed close toCodec
11/09 reserve EC_BEEP
01/03 Change SPDIF to SPDIF1
C1359
0.1U_0402_16V4Z
@1 2
R1051
BLM18BD601SN1D_06031 2
R1059 39.2K_0402_1%1 2
R734 10K_0402_5%1 2
C1
34
01
U_
06
03
_10
V4Z
1
2
R1063 39.2K_0402_1%1 2
U39
G9191-475T1U_SOT23-5
IN1
GND2
SHDN3
OUT 5
BYP 4
R1065
0_1206_5%1 2
C13471U_0603_10V4Z
12
C1358
0.1U_0402_16V4Z
@1 2
R1052
BLM18BD601SN1D_06031 2
C1349 0.1U_0402_16V4Z1 2
C1360
0.1U_0402_16V4Z
@1 2
C1
34
3
2.2
U_
08
05
_16V
4Z
1
2
C13530.1U_0402_16V4Z
1
2
R1061 10K_0402_5%1 2
C1351 1U_0603_10V6K 1 2
C1
34
2
0.1
U_
04
02
_16V
4Z
1
2
R683 10K_0402_1%
1 2
R1057 20K_0402_1%1 2
C1346 0.1U_0402_16V4Z1 2
R1053
0_0603_5%
1 2
R1056 5.1K_0402_1%1 2
C1350 1U_0603_10V6K 1 2
C1
33
90
.1U
_0
40
2_
16V
4Z
1
2
C1362
0_0402_5%1 2
C1344
0.1U_0402_16V4Z
1
2
C135510U_0805_10V4Z
1 2
R7361.21K_0402_1%
12
R105533_0402_5%
1 2
C1356 1U_0603_10V6K 1 2
R105447_0402_5%
@ 12
C1361
0.1U_0402_16V4Z
@1 2
R1060 47K_0402_5%1 2
R1058 22_0402_5%
1 2
R7351.21K_0402_1%
12
C1352 0.022U_0402_16V7K1 2
C1357 1U_0603_10V6K 1 2
C1348 0.1U_0402_16V4Z1 2
C1
33
71
U_
06
03
_10
V4Z 1
2
R733 10K_0402_5%1 2
U38
92HD71B7X5NLGXA1X8_QFN48_7X7
DVDD_CORE1
BITCLK6
VOL_DN/DMIC_1/GPIO 2 4
SDO5
VOL_UP/DMIC_0/GPIO 1 2
DVDD_IO3
SDI_CODEC8
DVSS**7
PCBEEP12
RESET#11
SYNC10
DVDD_CORE*9
SENSE_A 13
PORTE_L 14
PORTE_R 15
PORTF_L 16
PORTF_R 17
NC18
NC19
NC20
PORTB_L 21
PORTB_R 22
PORTC_L 23
PORTC_R 24
PORTD_R 36
PORTD_L 35
SENSE_B / NC34
CAP233
MONO_OUT32
VREFOUT-E / GPIO 4 31
GPIO 3 30
VREFOUT-C 29
VREFOUT-B 28
VREFFILT27
AVSS1*26
AVDD1*25
SPDIF OUT0 48
EAPD/ SPDIF OUT 0 or 1 / GPIO 0 47
DMIC_CLK46
SPDIF OUT1 / GPIO 7 45
GPIO 6 44
GPIO 5 43
AVSS2**42
PORTA_R 41
NC / OTP40
PORTA_L 39
AVDD2**38
NC37
C13410.1U_0402_16V4Z
1 2
R10640_0603_5%@
12
R44547K_0402_5%@
1 2
C134533P_0402_50V8K
@1
2
R1062 5.1K_0402_1%1 2
C1354 0.022U_0402_16V7K1 2
C1
33
80
.1U
_0
40
2_
16V
4Z
1
2
R596
0_1206_5%1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDA _S Y NC_MDC
HDA _ SDOUT_MDC
HDA _S DIN1_MDC
MIC_EXT_L
MIC_EXT_R
MIC_EXT_LMIC_EXT_R
HP _OUT_RHP_OUT_L
HP_DET#EXTMIC_DET#
CIR_ IN
HP _OUT_R
HP_OUT_L
SPKL-
SPKL+
SPKR-
EC_MUTE#
SPKR+
HP_DET#
JACK_DET# HP_DET#
SPKR+
SPKL+SPKL-
SPKR-
HDA _SDIN1<21>HDA_BITCLK_MDC <21>
HDA _SDOUT_MDC<21>
HDA_RST#_MDC<21>
HDA _S Y NC_MDC<21>
MIC_ IN_R<28>MIC_IN_L<28>
ANA_MIC_DET<32>
HP _OUTR<28>
HP_OUTL<28>
VREFOUT_B<28>
MIC_EXT_R<28>
MIC_EXT_L<28>
EXTMIC_DET#<28>
CIR_ IN<32,34>
INTMIC_DET#<28>
JACK_DET#<28,34>
LINE_OUT_L<28>
L INE_OUT_R<28>
EC_MUTE#<32>
DOCK_LOUT_R <34>
DOCK_LOUT_L <34>
+1.5VS
+3VS
+3VS
+3VS
+V DDA_CODEC
+5VL
+V DDA _CODEC
+3VS
B++3VALW
+5VS
+5VS+5VAMP
+3VALW
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
AMP & Audio Jack
Cus tom
29 46S aturday, January 05, 2008
2007/08/28 2006/07/26
MDC 1.5 Conn.
Audio/B & CIR
INTMIC IN
HP OUT
EXTMIC IN
HP OUT For M/B
Keep 10 mil width
15.6 dB
MDC Standoff
GAIN0 GAIN1 Av(inv)
0
1
6dB
10dB
15.6dB
21.6dB
0
1
0
0
1
1
11/07 Add 10K PU
11/07 Add Capacitor avoid DC lever to Docking audio
11/17 Change to15.6 dB
HP OUT For Docking
12/18 Shut down pop noise
11/07Change JP60 PCBFootprint fromACES_85204-04001_4P toACES_88231-04001_4P
SPEAKER
8/31EMI request
Q18B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
C6
19
10
00
P_
040
2_50
V7K
1
2
C287 0.022U_0603_25V7K1 2
C2700.01U_0402_25V7KDOCK@
1
2
C6
21
4.7
U_
08
05
_1
0V4Z
@
1
2
Q17B
2N7002DW-7-F_SOT363-6
DOCK@
3
5
4
+C785150U_B_6.3VM_R40M
1 2
C291 0.022U_0603_25V7K1 2
C61810P_0402_25V8K
@1 2
R396100K_0402_5%
12
R1105 0_0603_5%1 2
C288 0.022U_0402_16V7K1 2
G
D
S
Q462N7002_SOT23-3
DOCK@2
13
C13791U_0603_10V4Z
1 2
R67610K_0402_5%
DOCK@
12
C292 0.022U_0402_16V7K1 2
+
C295
150U_B_6.3VM_R40MDOCK@1 2
C284
0.1U_0402_16V4Z
1
2
U40
TPA6017A2_TSSOP20
GN
D4
1G
ND
311
GN
D2
13
GN
D1
20
VD
D16
PV
DD
115
RIN-17
BYPASS 10
NC 12
LOUT- 8
LOUT+ 4
ROUT- 14
ROUT+ 18
RIN+7
LIN-5
LIN+9
GAIN0 2
GAIN1 3
PV
DD
26
SHUTDOWN19T
HE
RM
AL P
AD
21
R1104 0_0603_5%1 2
Connector for MDC Rev1.5
JP8
ACES_88018-124G
C ONN@
GND11
IAC_SDATA_OUT3
GND25
IAC_SYNC7
IAC_SDATA_IN9
IAC_RESET#11
RES0 2
RES1 4
3.3V 6
GND3 8
GND4 10
IAC_BITCLK 12
GN
D13
GN
D14
GN
D15
GN
D16
GN
D17
GN
D18
R477 33_0402_5%1 2
+
C296
150U_B_6.3VM_R40MDOCK@1 2
R397100K_0402_5%
12
R684
0_0402_5%
12
R394
0_1206_5%
1 2
C1
37
5
10
0P
_0
402
_50V
8J
1
2
H12HOLEA
1
R678330K_0402_5%DOCK@
12
R95110K_0402_5%
12
R10784.7K_0402_5%
12
R1103 0_0603_5%1 2
C1
37
7
10
0P
_0
402
_50V
8J
1
2
D56PSOT24C_SOT23-3
@
231
C285 0.022U_0603_25V7K1 2
H14HOLEA
1
C787
1U_0603_10V4Z
1 2
R409 47_0402_5%DOCK@
1 2
R681 10K_0402_5%12
R10794.7K_0402_5%
Main@
12
C1
37
6
10
0P
_0
402
_50V
8J
1
2
R192
0_0402_5%
OPP@
1 2
C286 0.022U_0402_16V7K1 2
R685
4.7K_0402_5%
12
C282
10U_0805_10V4Z
1
2
D55PSOT24C_SOT23-3
@
231
Q16A
2N
70
02
DW
-7-F
_S
OT
363-
6
DOCK@
61
2
R47810_0402_5%
@12
R1102 0_0603_5%1 2
C2931U_0805_25V6K
1
2
JP51
ACES_88231-04001C ONN@
11
22
33
44
GND15
GND26
R410 47_0402_5%DOCK@
1 2
C283
0.1U_0402_16V4Z
1
2
C1
37
8
10
0P
_0
402
_50V
8J
1
2
R686
4.7K_0402_5%
12
C289 0.022U_0603_25V7K1 2
C6
20
0.1
U_
04
02
_1
6V4Z
1
2
R40110K_0402_5%
12
Q16B
2N
70
02
DW
-7-F
_S
OT
363-
6
DOCK@
3
5
4
R398100K_0402_5%@
12
Q18A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
R395100K_0402_5%
@
12
R10770_0402_5%
12
C290 0.022U_0402_16V7K1 2
JP49
ACES_87213-1400GC ONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
R476 0_0603_5%@ 1 2
Q17A
2N7002DW-7-F_SOT363-6
DOCK@
6 1
2+C786
150U_B_6.3VM_R40M
1 2
JP60
E&T_3806-F04N-02RC ONN@
11
22
33
44
GND15
GND26
R475 0_0603_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
U SB20_N6_R
U SB20_N6_R
USB20_P6_R
USB20_P6_R
USB20_P2_RU SB20_N2_R
SATA_TXN5SATA_TXP5
SATA_TXP5
SATA_RXN5SATA_RXP5
SATA_TXN5
U SB20_N7_RUSB20_P7_R
USB_EN#
USB_EN#
USB_EN#
USB20_N2
USB20_P2
USB20_N0<22>USB20_P0<22>
USB20_N1<22>USB20_P1<22>
BT_OFF<22>
USB20_N6 <22>
CH_CLK <26>
BT_LED <33>CH_DATA <26>
USB20_P6 <22>
USB20_N2<22>
SATA_RXN5_C<21>SATA_RXP5_C<21>
SATA_TXP5<21>
USB20_P2<22>
SATA_TXN5<21>
USB20_P7<22>USB20_N7<22>
USB_EN#<32>
+5VALW
US B _VCCC
+5VALW
+5VALW
+5VALW
+3VALW +3VAUX_BT
+5VALW
+3VAUX_BT
+5VALW
US B _VCCC
+3VS
+3VALW
+3VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
USB, BT, eSATA
30 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
W=100mils
Need change to New version
0612 no install
20070209 Add for FPR
Finger printer
Left side USB Connector Left side ESATA/USB combination Connector
BT Connector
USB cable connector for Right side
11/07 Change PCB Footprintto ACES_85201-06051_6P
01/03 Change BT power to +3VS
U41
TPS2061IDGNR_MSOP8
GND1
IN2
OC# 5OUT 6
OUT 8
IN3
EN#4
OUT 7
C1
38
31
00
0P
_0
402_
50V
7K
1
2
R1086 1K_0402_5%@ 1 2
D45
PRTR5V0U2X_SOT143-4@
GND 1
IO1 2
IO23
VIN4
C7560.1U_0402_16V4Z
FP@1
2
C1390
0.1U_0402_16V4Z1 2
C1
38
20
.1U
_0
40
2_
16V
4Z
1
2
R635 0_0402_5%
FP@
1 2
C1387
0.01U_0402_16V7K
1
2
R1081 0_0402_5%1 2
C1388
0.1U_0402_16V4Z
1
2
R1085 0_0402_5%12G
DS
Q105 SI2301BDS_SOT23
2
13
USB
ESATA
JP53
TYCO_1759576-1C ONN@
VBUS1
D-2
D+3
GND4
GND5
A+6
A-7
GND8
B-9
B+10
GND11
GND12
GND13
GND14
GND15
R1092
47K_0402_5%1 2
R634 0_0402_5%
FP@
1 2
R1087 1K_0402_5%@ 1 2
R1083 10K_0402_5%1 2
D47
PRTR5V0U2X_SOT143-4@
GND 1
IO1 2
IO23
VIN4
+
C1
38
01
50
U_
D_
6.3
VM 1
2
JP24
ACES_85201-06051C ONN@
GND7
GND8
11
22
33
44
55
66R405
0_0402_5%
@1 2
C1384 0.01U_0402_16V7K
ESATA@
12
R236
0_0603_5%
@1 2
G
DS
Q31SI2301BDS_SOT23
@
2
13
C13861U_0603_10V4Z
1
2
R1084 0_0402_5%12
C1381
4.7U_0805_10V4Z
1
2
R235
0_0603_5%
1 2
JP55
ACES_87213-1000GC ONN@
11
22
33
44
55
66
77
88
99
1010
GND111
GND212
R627 0_0603_5%F P@
1 2
R1090100K_0402_5%
12
D46
PRTR5V0U2X_SOT143-4@
GND 1
IO1 2
IO23
VIN4
D30PACDN042_SOT23-3~D
@
231
JP57
ACES_88231-08001C ONN@
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
GND1 9
GND2 10
R1080 0_0402_5%1 2
C1385 0.01U_0402_16V7K
ESATA@
12
R628
0_0603_5%
@1 2
C1389
4.7U_0805_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
F RD#
S PI_CLK_R
SPI_SOS P I_FWR#
SPI_FSEL#
SPI_HOLD#_0SPI_SO_JP18SPI_SI_JP18
ON/ OFFBTNLED#
V CC1P WRGDSPI_CLK_JP18SPI_CS#_JP18
ON/ OFFBTNLED#
V CC1P WRGD
ON /OFFBTN_LED#
SPI_SI_JP18
SPI_HOLD#_0
SPI_CLK_JP18
SPI_CS#_JP18
SPI_SO_JP18
F WR#
SPI_CLK
FSEL#
F RD#
HOL D#
V CC1_ PWRGD
SPI_SB_CS#
SPI_SI
SPI_CLK
SPI_WP#
S PI_HOLD#
SPI_SO_RSPI_SO_L
SPI_WP#
S PI_HOLD#
SPI_FSEL#
S PI_CLK_R
S P I_FWR#
SMB_EC_CK1<32,33,37>SMB_EC_DA1<32,33,37>
SPI_CLK<22,32>
F RD# <32>F WR#<32>
FSEL#<32>
P CI_RST#<20,32>
LPC_AD0<21,26,32>LPC_AD1<21,26,32>LPC_AD2<21,26,32>LPC_AD3<21,26,32>
LPC_FRAME#<21,26,32>
CLK_DEBUG_PORT_0<17>
ON/OFFBTN_LED#<32,33>
V CC1_PWRGD<32>
SPI_SI<22>
SPI_SB_CS#<22>
SPI_SO_R <22>
+3VALW+3VALW
+3VL
B+
+3VALW
+3VS
+3VS
+3VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
BIOS ROM
31 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASHWIESO_G6179-100000_8P
20mils
SPI ROM
LPC Debug Port
Change from +3VL to +3VS. 6/9
Removed +3VS. 6/13
Connect pin3 & 23together and pin 24to GND in 6/29.
11/07 Add 0 Ohm for debug port
11/16 Change TO +3VALW
11/17 Add SB HDCP ROM
12/27EMI request
01/03 Change HDCP ROM to +3VS
R552100K_0402_5%
12
U 6
SST25LF080A_SO8-200mil
S1
VCC8
Q 2
HOLD7
VSS 4
D5
C6
W3
R231
33_0402_5%
@12
R415
15_0402_5%
1 2
R566 0_0402_5%DE B UG@
1 2
R556 0_0402_5%1 2
JP18
ACES_87216-2404_24PC ONN@
Ground1
LPC_PCI_CLK2
Ground3
LPC_FRAME#4
+V3S5
LPC_RESET#6
+V3S7
LPC_AD08
LPC_AD19
LPC_AD210
LPC_AD311
VCC_3VA12
PWR_LED#13
CAPS_LED#14
NUM_LED#15
VCC1_PWRGD16
SPI_CLK17
SPI_CS#18
SPI_SI19
SPI_SO20
SPI_HOLD#21
Reserved22
Reserved23
Reserved24
R4131K_0402_5%@
12
C711
0.1U_0402_16V4Z
1
2
C308
15P_0402_50V8J
@
12
R555 0_0402_5%
1 2
R565 0_0402_5%DE B UG@
1 2
R559 0_0402_5%DE B UG@
1 2
R553 0_0402_5%1 2
R562 0_0402_5%DE B UG@
1 2
R232
33_0402_5%
@12
R560 0_0402_5%DE B UG@
1 2
C309
15P_0402_50V8J
@
12
R4123.3K_0402_5%
1 2 R563 0_0402_5%DE B UG@
1 2
C3040.1U_0402_16V4Z
1
2
R230
33_0402_5%
@12
R4113.3K_0402_5%
1 2
U27
WIESON G6179 8P SPI
S1
VCC8
Q 2
HOLD7
VSS 4
D5
C6
W3
U28
AT24C16AN-10SI-2.7_SO8
A0 1
A1 2
SDA5SCL6
VCC8
A2 3
GND 4
WP7
R554 0_0402_5%1 2
R414
15_0402_5%
1 2
C307
15P_0402_50V8J
@
12
C7120.1U_0402_16V4Z
1
2
R558 0_0402_5%DE B UG@
1 2
R5613.3K_0402_5%
1 2
R557100K_0402_5%
12
ON/ OFFBTN
KSI7
KSO12KSO13KSO14
KSO4
KSO8
KSO6
KSO3
KSO0KSO1
KSO9
KSO2
KSO7
KSO5
KSO11KSO10
SMB_EC_CK2SMB_EC_DA2
U RXUTX
SLP_S3#SLP_S5#EC_SMI#
LPC_FRAME#
L I D_SW#
S I RQ
GATEA20KB_RST#
LPC_AD2LPC_AD1
LPC_AD3
LPC_AD0
EC
AG
ND
PCI_RST#
UTXLA N _POWER_OFF_R
CL K_PCI_EC
ECRST#
KSI3
C RY 1
C RY 2
KSI0KSI1
KSI6KSI5
KSI2
KSI4
KSO15
SMB_EC_CK1SMB_EC_DA1
SUSP#
L I D_SW#
EC_PME#
SMB_EC_CK1
SMB_EC_CK2SMB_EC_DA2
SMB_EC_DA1
ON/ OFFBTN
CO NA#
BAT_LED#
IRE F
E CA G ND
I NV_PWMF AN_PWM
BATT_TEMP
M _PWROK
EC_RSMRST#
BKOFF#
E C _ON
A DP_IA D P_ID
V R _ON
DA C_ BRIG
ENBKL
STD_ADP
TP_BTN#
AC_SET
A C_ IN
F S TCHG
F RD#
BATT_OVP
S Y SON
PM_PWROK
A C OFF
T HERM_SCI#
ON /OFFBTN_LED#
EC_PME#
NU M_LED#
EC_MUTE#
CAPS_LED#
TP_CLKTP_DATA
V CC1_ PWRGD
DI M_LED
I2 C_INT
D OCK_VOL_UP#DOCK _VOL_DWN#
ESB_DAT_RESB_CLK_R
TP_LED#
SUSP#PWRBTN_OUT#
ANA_MIC_DET
V CTRL
MUTE_LED
USB_EN#
E A P D_CODEC
WL_BLUE_LED#
A C_ IN A CIN
NM I_DBG# P C I_SERR#
CIR_ IN
PCI_RST#
KSO12
KSO11
KSO10
KSO6
KSO3
KSO5
KSO4
KSO0
KSO2
KSO1
KSI3
KSI2
KSI4
KSI5
KSI1
KSI6
KSO13
KSI7
KSI0
KSO14
KSO15
KSO9
KSO7
KSO8
KSO13
KSO2
KSI2
KSO4
KSO8
KSO10
KSI5
KSO3
KSO15
KSO11
KSO5
KSO0
KSI4
KSO1
KSO7
KSI0
KSO14
KSI7
KSI3
KSO6
KSO12
KSI6
KSI1
KSO9
NM I_DBG#
TP_BTN#
ESB_CLK_RESB_DAT_R
A D P_ID
WWA N_ POWER_OFF
SLP_S4#
S Y SON
LA N _POWER_OFF_R
LA N _POWER_OFF_R
EC_BEEP
BATT_OVP
D OCK_VOL_UP#
DOCK _VOL_DWN#
EC_PME#
F WR#SPI_CLKFSEL#
LPC_FRAME#<21,26,31>S IRQ<22>
LPC_AD1<21,26,31>LPC_AD2<21,26,31>
LPC_AD0<21,26,31>
LPC_AD3<21,26,31>
CLK_PCI_EC<17>P CI_RST#<20,31>
E C_SCI#<22>
SMB_EC_DA1<31,33,37>SMB_EC_CK1<31,33,37>
SMB_EC_CK2<6>SMB_EC_DA2<6>
L ID_SW#<33>
GATEA20<21>KB_RST#<21>
SLP_S3#<22>SLP_S5#<22>
PCI_PME#<20>
DOCK_SLP_BTN#<34>
EC_SMI#<22>
ON/OFFBTN<33>
CONA#<34>
A COFF <38,39>
C IR_ IN <29,34>
F RD# <31>
BATT_OVP <37>
F AN_PWM <6>
DA C_BRIG <19>
S Y S ON <26,33,36,41>
EC_RSMRST# <22>
E C_ON <39>
BAT_LED# <33>
V R_ON <43>
A DP_I <38>
T HERM_SCI# <22>
ON/OFFBTN_LED# <31,33>
INV_PWM <19>
E C_LID_OUT# <22>
TP_CLK <33>TP_DATA <33>
P M_PWROK <9,22>B KOFF# <19>M_PWROK <9,22>
F S TCHG <38>STD_ADP <38>
TP_BTN# <33>
AC_SET <38>IRE F <38>
A DP _ID <37>
ENBKL <11>
CAPS_LED# <33>
V CC1_PWRGD <31>
DIM_LED<36>NUM_LED#<33>
I2C_INT <33>
DOCK_VOL_UP# <34>DOCK _VOL_DWN# <34>
EC_MUTE# <29>
TSATN#<9> TP_LED# <33>
SUSP# <26,28,36,38,40,41>PWRBTN_OUT# <22>
BATT_TEMP <37>
ANA_MIC_DET <29>
V CTRL <38>
MUTE_LED <34>
USB_EN# <30>
E A P D_CODEC <28>
WL_BLUE_LED# <33>
P CI_SERR# <20>
ESB_DAT<33>ESB_CLK<33>
A CIN <38>
WWA N_POWER_OFF<26>
SLP_S4# <22>
HDA _RST#_CODEC<21,28>
LA N_POWER_OFF<25>
EC_BEEP <28>
WL_BLUE_BTN<33>
F WR# <31>
FSEL# <31>SPI_CLK <22,31>
+E C_AVCC
+3VL_EC
+EC_AVCC
+3VL_EC
+3VL
+5V_TP
+3VL +3VL_EC
+3VALW
+3VL
+5VL +3VS
+3VL
+3VL
+3VL
+3VS
+3VL
+5VL
+5VL
+3VS
+3VL +3VL
+3VALW
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
EC KB926/KB Conn.
32 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
For EMI
EC DEBUG portFor CRevision
14" INT_KBDCONN.( TYPE "D"KB)
VendorRecommend
11/07 Add SYSON and SUSP# PD
11/07 Correct direction pretect leakage
11/07 Add SLP_S4# to South bridge
11/07 Connect DOCK_SLP_BTN# to ON/OFFBTN
11/09 don't stuff when use C0
11/09 Add HDA_RST# to EC
11/09 Delete CLKRUN#
11/09 PU +5VL move to M/B
11/09 EC recommend
11/17 Change to +3VALW
11/15 Delete PCI_PME#
01/03 Change to +3VS
C807 100P_0402_50V8J@ 1 2
R5920_0402_5%
1 2
R5934.7K_0402_5%
1 2
C793 100P_0402_50V8J@ 1 2
C815 100P_0402_50V8J@ 1 2
R577 4.7K_0402_5%1 2
C72315P_0402_50V8J1 2
C801 100P_0402_50V8J@ 1 2
C718
0.1U_0402_16V4Z1
2
R580 10K_0402_5%1 2
C802 100P_0402_50V8J@ 1 2
Y5
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC3
NC2
R443
0_0402_5%
1 2
R403 0_0402_5%1 2
C808 100P_0402_50V8J@ 1 2
R5880_0402_5%
1 2
D13
CH751H-40PT_SOD323-2
2 1
C794 100P_0402_50V8J@ 1 2
C722
15P_0402_50V8J
@1 2
R11004.7K_0402_5%
12
C7244.7U_0603_6.3V6K
1
2
R731 0_0402_5%1 2
C72515P_0402_50V8J
1 2
R572
0_0805_5%1 2
R578 47K_0402_5% 1 2
C809 100P_0402_50V8J@ 1 2
LPC & MISC
Int. K/B Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U30
KB926QFB0_LQFP128_14X14
GA20/GPIO001
KBRST#/GPIO012
SERIRQ#3
LFRAME#4
LAD35
PM_SLP_S3#/GPIO046
LAD27
LAD18
VC
C9
LAD010
GN
D11
PCICLK12
PCIRST#/GPIO0513
PM_SLP_S5#/GPIO0714
EC_SMI#/GPIO0815
LID_SW#/GPIO0A16
SUSP#/GPIO0B17
PBTN_OUT#/GPIO0C18
EC_PME#/GPIO0D19
SCI#/GPIO0E20
INVT_PWM/PWM1/GPIO0F 21
VC
C22
BEEP#/PWM2/GPIO10 23
GN
D24
EC_THERM#/GPIO1125
FANPWM1/GPIO12 26
ACOFF/FANPWM2/GPIO13 27
FAN_SPEED1/FANFB1/GPIO1428
FANFB2/GPIO1529
EC_TX/GPIO1630
EC_RX/GPIO1731
ON_OFF/GPIO1832
VC
C33
PWR_LED#/GPIO1934
GN
D35
NUMLED#/GPIO1A36
ECRST#37
CLKRUN#/GPIO1D38
KSO0/GPIO2039
KSO1/GPIO2140
KSO2/GPIO2241
KSO3/GPIO2342
KSO4/GPIO2443
KSO5/GPIO2544
KSO6/GPIO2645
KSO7/GPIO2746
KSO8/GPIO2847
KSO9/GPIO2948
KSO10/GPIO2A49
KSO11/GPIO2B50
KSO12/GPIO2C51
KSO13/GPIO2D52
KSO14/GPIO2E53
KSO15/GPIO2F54
KSI0/GPIO3055
KSI1/GPIO3156
KSI2/GPIO3257
KSI3/GPIO3358
KSI4/GPIO3459
KSI5/GPIO3560
KSI6/GPIO3661
KSI7/GPIO3762
BATT_TEMP/AD0/GPIO38 63
BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65
AD3/GPIO3B 66
AV
CC
67
DAC_BRIG/DA0/GPIO3C 68
AG
ND
69
EN_DFAN1/DA1/GPIO3D 70
IREF/DA2/GPIO3E 71
DA3/GPIO3F 72
CIR_RX/GPIO40 73
CIR_RLC_TX/GPIO41 74
AD4/GPIO42 75
SELIO2#/AD5/GPIO43 76
SCL1/GPIO4477
SDA1/GPIO4578
SCL2/GPIO4679
SDA2/GPIO4780
KSO16/GPIO4881
KSO17/GPIO4982
PSCLK1/GPIO4A 83
PSDAT1/GPIO4B 84
PSCLK2/GPIO4C 85
PSDAT2/GPIO4D 86
TP_CLK/PSCLK3/GPIO4E 87
TP_DATA/PSDAT3/GPIO4F 88
FSTCHG/SELIO#/GPIO50 89
BATT_CHGI_LED#/GPIO52 90
CAPS_LED#/GPIO53 91
BATT_LOW_LED#/GPIO54 92
SUSP_LED#/GPIO55 93
GN
D94
SYSON/GPIO56 95
VC
C96
SDICS#/GPXOA00 97
SDICLK/GPXOA01 98
SDIDO/GPXOA02 99
EC_RSMRST#/GPXO03 100
EC_LID_OUT#/GPXO04 101
EC_ON/GPXO05 102
EC_SWI#/GPXO06 103
ICH_PWROK/GPXO06 104
BKOFF#/GPXO08 105
WL_OFF#/GPXO09 106
GPXO10 107
GPXO11 108
SDIDI/GPXID0 109
PM_SLP_S4#/GPXID1 110
VC
C111
ENBKL/GPXID2 112
GN
D113
GPXID3 114
GPXID4 115
GPXID5 116
GPXID6 117
GPXID7 118
SPIDI/RD# 119
SPIDO/WR# 120
VR_ON/XCLK32K/GPIO57 121
XCLK1122
XCLK0123 V18R 124
VC
C125
SPICLK/GPIO58 126
AC_IN/GPIO59 127
SPICS# 128
C803 100P_0402_50V8J@ 1 2
C795 100P_0402_50V8J@ 1 2
C715
0.1U_0402_16V4Z
1
2
R10994.7K_0402_5%
12
R227 33_0402_5%
1 2
C726 0.1U_0402_16V4Z
1 2
R720 10K_0402_5%1 2
D16
CH751H-40PT_SOD323-2
2 1
R732 0_0402_5%1 2
R72110K_0402_5%
12
R58510K_0402_5%@
12
C810 100P_0402_50V8J@ 1 2
C804 100P_0402_50V8J@ 1 2
C796 100P_0402_50V8J@ 1 2
R5818.2K_0402_5%
12
C716
0.1U_0402_16V4Z1
2
R19110K_0402_5%OPP@
12
R582 4.7K_0402_5%@ 1 2
R228 33_0402_5%
1 2
R573 4.7K_0402_5%1 2
R71410K_0402_5%
12
C797 100P_0402_50V8J@ 1 2
C805 100P_0402_50V8J@ 1 2
R58310K_0402_5%
12 C811 100P_0402_50V8J@ 1 2
R40710K_0402_5%
12
R576
33_0402_5%
@1 2
C719
1000P_0402_50V7K1
2
R591 0_0603_5% @1 2
C717
1000P_0402_50V7K
1
2
J1
JOPEN
12
L300_0603_5%
12
C812 100P_0402_50V8J@ 1 2
C301
100P_0402_50V8J
12
R713100K_0402_5%
12
R586 10K_0402_5%
12
C806 100P_0402_50V8J@ 1 2
R229 33_0402_5%
1 2
C798 100P_0402_50V8J@ 1 2
R5890_0402_5%
@ 1 2
JP20
ACES_85205-0400C ONN@
1 1
2 2
3 3
4 4
JP19
ACES_85201-2405C ONN@
123456789101112131415161718192021222324
R574 4.7K_0402_5%1 2
C813 100P_0402_50V8J@ 1 2
C791 100P_0402_50V8J1 2
R71510K_0402_5%
12
R40810K_0402_5%
12
R4420_0402_5%
@1 2
C799 100P_0402_50V8J@ 1 2
C792 100P_0402_50V8J@ 1 2
D14
CH751H-40PT_SOD323-2
21
R575 4.7K_0402_5%1 2
R2330_0805_5%
12
L31
0_0603_5%
1 2
C721 0.1U_0402_16V4Z12
R1900_0402_5%OPP@
1 2
C814 100P_0402_50V8J@ 1 2
R579 10K_0402_5%1 2
R59520M_0402_5%
@
12
C7200.01U_0402_16V7K
1 2
R2138.2K_0402_5%
12
C800 100P_0402_50V8J@ 1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
TP_DATATP_CLK
S Y SON
TP_DATATP_CLK
ON /OFFBTN_LED#
ON /OFFBTN_LED#ON/ OFFBTN
W L_LED
ESB_CLKESB_DAT
WL_BLUE_LED#
SMB_EC_CK1
SMB_EC_DA1
ESB_CLK
TP_LED#
TP_BTN# <32>
S Y S ON<26,32,36,41>
SATA_LED#<21>
BAT_LED#<32>
I2C_INT<32>
CAPS_LED#<32>
TP_CLK <32>TP_DATA <32>
NUM_LED#<32>
WL_LED#<26>
HDDHALT_LED#<22>
WW_LED#<26>
ESB_DAT<32>ESB_CLK<32>
WL_BLUE_BTN<32>
BT_LED<30>
WL_BLUE_LED# <32>
L ID_SW#<32>
SMB_EC_CK1<31,32,37>
SMB_EC_DA1<31,32,37>
ON/OFFBTN<32>ON/OFFBTN_LED#<31,32>
TP_LED# <32>
+5V_TP
+5VALW +5V_TP
+5VALW_LED
+5VS_LED
+5VS_LED
+5V_TP
+5VS_LED
+3VS
+5VALW_LED
+5VALW_LED
+5VS_LED
+3VS
+3VS
+3VL +5VALW_LED
+3VS
+3VALW
+5VS_LED
+5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
KBD, ON/OFF, SW, CIR
33 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
BatteryCharge LED
HDD LED
Cap lock
T/P Board Conn
EMI request
On (TP_LED#=L)-> WhiteOff (TP_LED#=H)-> Amber
TP ON/OFF TouchPAD ON/OFF LED
Capacitor Sensor Conn
Keyboard backlight Conn
T/P Board (Inculde T/P_ON/OFF)System LED
SystemPower LED
ON/OFF Button Connector
Lid Switch Connector
AMBER
11/07 Change part number
White
White
White
White
Mini card LED
11/20 Reserve WW_LED function
Cypress
ENE
AMBER White
01/03 Keyboard backlight reserve a 0805 size resist or
01/03 Change Lid switch connector type
01/03 EMI request
R1095
470_0402_5%
1 2
JP23
ACES_85201-04051C ONN@
1 1
2 2
3 3
4 4G15
G26
JP59
ACES_85201-1005NC ONN@
11
22
33
44
55
66
77
88
99
1010
GND11
GND12
R716100K_0402_5%
12
R1097
470_0402_5%
1 2D52
HT-F196BP5_WHITE
21
R56 0_0402_5%Main@ 1 2
G
D
SQ42N7002_SOT23-3
2
13
C313
4.7U_0603_6.3V6K1
2
R717100K_0402_5%
12
R729 0_0402_5%1 2
R510_0805_5%Main@
12
D17
HT-F196BP5_WHITE
21
D28PSOT24C_SOT23-3@
231
R149 0_0402_5%Main@ 1 2
White
Amber
D53
QSMF-C16E_AMBER-WHITE
21
43
10K
47K Q14DTA114YKAT146_SOT23-3
2
13
R609200_0402_5%
12
R980
470_0402_5%
1 2
R530_0805_5%OPP@
12
R718
10K_0402_5%
12
C731100P_0402_50V8J@
1
2
S W1TJG-533-V-T/R_6P
3
2
1
4
5 6
R691 0_0603_5%
1 2
JP11
ACES_85201-04051CONN@
11
22
33
44G1 5
G2 6
R151 0_0402_5%OPP@ 1 2
R728470_0402_5%
GS@1 2
R730 0_0402_5%1 2
C730100P_0402_50V8J
@
1
2
R61210K_0402_5%
@
12
R19310K_0402_5%
12
JP9
ACES_85201-04051C ONN@
11
22
33
44 G1 5
G2 6
Q11B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
R205
0_0805_5%
1 2
R169 0_0402_5%OPP@ 1 2
R610820_0402_5%
12
C7290.1U_0402_16V4Z@
1
2
R234
33_0402_5%
@12
JP10
ACES_85201-04051C ONN@
11
22
33
44G1 5
G2 6
10K
47K Q20DTA114YKAT146_SOT23-3
2MiniC@2
13
Q11A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
C310
15P_0402_50V8J
@
12
G
DS
Q23SI2301BDS-T1-E3_SOT23-32
13
R1098470_0402_5%
1 2 White
Amber
D12QSMF-C16E_AMBER-WHITE
21
43
R61110K_0402_5%
@
12
G
D
S
Q242N7002_SOT23-3@2
13
R110110K_0402_5%
12
D50
HT-F196BP5_WHITE
21
DOCK _P WRON
D OCK_PRESENT
DOC K_MIC_L_C
DOCK _ MIC_R_C
DOC K_MIC_L_C
D OCK_LOUT_LR_V OL_DWN#DOC K_LOUT_RR_VOL_UP#
S PDIFO_L
R E DGR EENBLUED_DD CDATAD_DDC CLKD_HS Y NCD_V S YNCUSB20_N3USB20_P3
+V_BATTERY
RJ 45_MIDI0+RJ 45_MIDI0-RJ 45_MIDI1+RJ 45_MIDI1-
V G A_GND
JACK_DET#DOCK_SLP_BTN#MUTE_LEDDOCK _P WRONCIR_ IN
S PDIFO_L
A UDIO_ I GNDD OCK_PRESENT
DOC K_MIC_L_CDOCK _ MIC_R_CD OCK_LOUT_LDOC K_LOUT_RA UDIO_ OGND
R_V OL_DWN#R_VOL_UP#
S Y SON#<36,42>
CONA#<32>
SENSE_B# <28>
DOCK _MIC_R<28>
DOCK_MIC_L<28>
S PDIF_OUT <28>
R E D<18>GREEN<18>BLUE<18>D_DDCDATA<18>D_DDCCLK<18>D_HS Y NC<18>D_V S YNC<18>USB20_N3<22>USB20_P3<22>
RJ45_MIDI0+<25>RJ45_MIDI0-<25>RJ45_MIDI1+<25>RJ45_MIDI1-<25>
JACK_DET# <28,29>DOCK_SLP_BTN# <32>MUTE_LED <32>
CIR_ IN <29,32>
DOCK_LOUT_R <29>DOCK_LOUT_L <29>
DOCK _VOL_DWN# <32>DOCK_VOL_UP# <32>
+3VALW
+5VS
+3VL
+3VS
+1.5VS_HDA
+DOCKVIN
B+
+DOCKVIN
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
DOCK CONN.Cus tom
34 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
Atlas/ Saturn Dock
DOCK_PWR_ON Spec0V = Notebook S4/S5, Dock off2.5V = Notebook S3, Dock on4V = Notebook S0, Dock on
Dock PRESENT
Need 600 Ohm 500 mA
MIC_Dock
11/12 Change to +3VL
GNDA GNDA
GNDA GNDA
GNDA
11/17 Reserve
11/17 Recommend
12/18 Correct GND
12/18 Correct GND
11/07 Delete TVout function from Docking
GNDA
GNDA
C7341000P_0402_50V7KDOCK@
1
2
R62510K_0402_5%DOCK@
12
R620 2K_0402_5%1 2
R974 1K_0402_5%DOCK@
1 2
R979
22_0402_5%DOCK@
1 2
C64
0.1U_0402_16V7K
DOCK@1 2
C757
1U_0603_10V6KDOCK@
1
2
C745
10
00
P_
040
2_50
V7K
DOCK@
1
2
C3061000P_0402_50V7K@
1 2
R72233_0402_5%
@
12
C3051000P_0402_50V7K@
1 2
C754220P_0402_50V7K
DOCK@
1
2
R723
0_0603_5%
DOCK@1 2
G
D
SQ272N7002_SOT23-3DOCK@
2
13
L37FBM-11-160808-601-T_0603
DOCK@1 2
G
D
S
Q292N7002_SOT23-3DOCK@
2
13
G
D
S
Q552N7002_SOT23-3
@ 2
13
R62610K_0402_5%
DOCK@
12
R978110_0402_5%DOCK@
12
D57
DAN202U_SC70DOCK@
2
31
C755220P_0402_50V7KDOCK@
1
2
C819220P_0402_25V8J
DOCK@
1
2
EB
C
Q32MMBT3904_NL_SOT23-3
DOCK@2
31
R618 200_0402_5%
DOCK@
1 2
L36FBM-11-160808-601-T_0603
DOCK@
1 2
R6232K_0402_5%DOCK@
12
G
D
SQ582N7002_SOT23-3
DOCK@
2
13
R632
10K_0402_5%DOCK@
1 2
R977
220_0402_5%
DOCK@1 2
PJP3
P AD-OPEN 2x2m
21
C741
0.0
1U
_0
40
2_1
6V7K
DOCK@
1
2
EB
C
Q30MMBT3904_NL_SOT23-3DOCK@
2
31
R97610K_0402_5%DOCK@
12
R617 200_0402_5%
DOCK@
1 2
JDOCK1
FOX_QL1122L-H212AR-7FC ONN@
CRT_Green40
TV composite 33CRT_Blue34
TV ground 31
Vsync26CIR input 29
USB-28
USB+22
PWR_ON 27
Digital gnd24
MDI0-6
MDI3-18
Mute_LED 25
DDC_Clock30DDC_DATA36
Digital gnd 39
TV chroma 35TV Luma 37
CRT_Red38
Hsync32
MDI3+20
MD2I-14
MDI2+16
MDI1-10
MDI1+12
Sleep Botton 23
Jack Detect 21
VOL_up 19
VOL_down 17
MDI0+8
Battery out2
Battery out4
SPDIF 15
Audio Output gnd 13
Left headphone 9Right headphone 11
Mic_Right 7
Dock_present 1Mic gnd 3Mic_Left 5
GND 41
GND 42
GND 43
GND 44GND45
GND46
R62110K_0402_5%
12
C744
10
00
P_
040
2_50
V7K
DOCK@
1
2
R975 1K_0402_5%DOCK@
1 2
R63347K_0402_5%
DOCK@
12
C740
0.0
1U
_0
40
2_1
6V7K
DOCK@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI_TX_1-
H DMI_DETECT
HD MIDAT
HDM ICLK
HDMI_TX_2-
H DMI_DETECT
HDMI_TX1+
HDM ICLK-
HDMI_TX2-
HDMI_TX_0+HDM ICLK+
HDMI_TX_2+
HDMI_TX1-
HDMI_TX2+
HDMI_TX0+
HDMI_TX0-
TMDS_B_HPD
TMDS_B_HPD#
TMDS_B_HPD
HDM I_CLK-
HD MI_CLK+
HDM ICLKHD MIDAT
+5VS_HDMI
HDMI_TX1+
HDMI_TX2+
HDMI_TX1-
HDMI_TX2-
HDM I_CLK-
HDMI_TX0-HDMI_TX0+
HD MI_CLK+
HDM ICLK-
HDM ICLK+
HDMI_TX_1+
HDMI_TX_1-
HDMI_TX_2+
HDMI_TX_2-
HDMI_TX_0+
HDMI_TX_0-
HDMI_TX_0-
HDMI_TX_1+
HDMIDAT_NB<9>
HDMICLK_NB<9>
TMDS_B_DATA1 <11>
TMDS_B_DATA0 <11>TMDS_B_DATA0# <11>
TMDS_B_DATA1# <11>
TMDS_B_CLK<11>TMDS_B_CLK#<11>
TMDS_B_DATA2<11>TMDS_B_DATA2#<11>
TMDS_B_HPD# <11>
+3VS_LS
+3VS_LS+3VS_LS
+3VS_LS
+3VS_LS
+3VS_LS +3VS_LS
+3VS_LS+3VS_LS
+3VS_LS
+3VS_LS
+3VS_LS+3VS
+3VS_LS
+5VS
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
HDMI LS & Conn.Cus tom
35 46S aturday, January 05, 2008
2007/08/28 2006/03/10Compal Electronics, Inc.
HDMI Connector
Follow IntelFeedback putting2.2K ohm
Follow Vendor Feedback
11/07 correct TMDS_B_HPD# connection to North bridg e
11/07 Enable DDC_EN pin
11/07 Follow recommend change to 3.9K
Vendor suggests 4K PU
01/03 Reserver 0 ohm co lay with common choke
R214 0_0402_5%
1 2
D32SKS10-04AT_TSMA
21
C774330P_0402_50V7K
1
2
C770
0.5P_0402_50V8B
@
R652 0_0402_5%@ 12
JHDMI1
SUYIN_100042MR019S153ZLC ONN@
D2+1
GND 2
D2-3D1+4
GND 5
D1-6D0+7
GND 8
D0-9CK+10
GND 11
CK-12
CEC 13
Reserved 14SCL15SDA16
DDC/CEC_GND 17
+5V18
HP_DET19
GND 20
GND 21
GND 22
GND 23
R657
68_0402_5%
@1 2
R6502.2K_0402_5%
12
R217 0_0402_5%
1 2
R654 0_0402_5% @ 12
L39
WCM-2012-900T_0805
@
11 2 2
3 344
R648 0_0603_5%1 2
C771
0.5P_0402_50V8B
@
R219 0_0402_5%
1 2
R659
68_0402_5%
@1 2
G
D
S
Q28
2N7002_SOT23-3
2
13
R6492.2K_0402_5%
12
C7730.1U_0402_16V4Z
1
2
L42
WCM-2012-900T_0805
@
11 2 2
3 344
R220 0_0402_5%
1 2
R655 0_0402_5%12
R74220K_0402_5%
12
R4
93
.9K
_0
402
_1%
12
R656
68_0402_5%
@1 2
L40
FBML10160808121LMT_0603
1 2
R206 0_0402_5%
1 2
R74320K_0402_5%
12
L38
WCM-2012-900T_0805
@
11 2 2
3 344
R221 0_0402_5%
1 2
R5
03
.9K
_0
402
_1%
12
R665
1K_0402_1%1 2
R6531K_0402_5%12
CH7318A-BF-TR_QFN48_7X7
U43
GND1
VCC3V2
FUNCTION13
FUCNTION24
GND5
ANALOG1(REXT)6
HPD_SOURCE7
SDA_SOURCE8
SCL_SOURCE9
ANALOG210
VCC3V11
GND12
OU
T_D
4+
13
OU
T_D
4-
14
VC
C3V
15
OU
T_D
3+
16
OU
T_D
3-
17
GN
D18
OU
T_D
2+
19
OU
T_D
2-
20
VC
C3V
21
OU
T_D
1+
22
OU
T_D
1-
23
GN
D24
GND 36
FUNCTION4 35
FUNCTION3 34
VCC3V 33
DDC_EN 32
GND 31
HPD_SINK 30
SDA_SINK 29
SCL_SINK 28
GND 27
VCC3V 26
OE* 25
IN_D
4+
48
IN_D
4-
47
VC
C3V
46
IN_D
3+
45
IN_D
3-
44
GN
D43
IN_D
2+
42
IN_D
2-
41
VC
C3V
40
IN_D
1+
39
IN_D
1-
38
GN
D37
C772
0.5P_0402_50V8B
@
R66610K_0402_1%
12
R211 0_0402_5%
1 2
D31RB411D T146 _SOT23-3
21
R651 0_0402_5%12
L41
WCM-2012-900T_0805
@
11 2 2
3 344
C769
0.5P_0402_50V8B
@
R7447.5K_0402_1%
12
R222 0_0402_5%
1 2
R658
68_0402_5%
@1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SUSP S Y SON#SUSP
S Y SON
S Y SON#
DI M_LED
SUSP#
SUSP SUSP
SUSP
D IM_LED#
R U NON
SUSPSUSP
D IM_LED#
RUNO N_3VS
SUSP
SUSP
R U NON
S Y S ON<26,32,33,41>
DIM_LED<32>
SUSP# <26,28,32,38,40,41>
S Y SON#<34,42> SUSP <42>
+3VL
+5VS+5VALW +3VS+3VALWB+
+3VL
+5VS +3VS +1.8V+1.5VS +VCCP +0.9V
+5VALW +5VALW_LED
+1.8VS+1.8V
+1.8VS
+5VS_LED+5VS
B+
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
DC/DC Interface
36 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
Discharge circuit
+5VALW to +5VS Transfer +3VALW to +3VS Transfer DIM LED
11/07 BOM Delete +1.8VS for Cardreader internal LDO
+1.8V to +1.8VS Transfer
01/03 Sparate+5VSand +3VS powertiming
H15HOLEA
1
R639
100K_0402_5%
12
Q13A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
R640
100K_0402_5%
12
H2HOLEA
1
C765
0.01U_0402_16V7K
1
2
Q12B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
H19HOLEC
1
H16HOLEA
1
G
D
S
Q352N7002_SOT23-3
2
13
R638
470_0402_5%
12
H7HOLEA
1
H 3HOLEA
1
R642
470_0402_5%
12
U33
AO4466_SO8
S 1
S 2
S 3
G 4
D8
D7
D6
D5
Q12A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
Q6B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
H17HOLEA
1
C762
10
U_
08
05
_10V
4Z
1
2
C767
0.1
U_
04
02
_1
6V4Z
@1
2
G
DS
Q33
SI2301BDS-T1-E3_SOT23-3
2
13
Q34B
2N7002DW-7-F_SOT363-6
3
5
4
Q34A
2N7002DW-7-F_SOT363-6
61
2
H4HOLEA
1
C761
0.1
U_
04
02
_16
V4Z
1
2
R646
470_0402_5%
12
H20HOLEC
1
Q6A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
H18HOLEA
1
FM11
C766
10
U_
08
05
_10
V4Z
@1
2
R645
470_0402_5%
12
R63710K_0402_5%
12
R223
330K_0402_5%
12
H 5HOLEA
1
H 8HOLEA
1
FM21
R636
330K_0402_5%
12
C2940.1U_0402_16V4Z
1
2
G
D
S
Q44
2N7002_SOT23-3
@2
13
C764
10U_0805_10V4Z
1
2
C763
0.1U_0402_16V4Z
1
2
H 6HOLEA
1
H9HOLEA
1
Q9B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
G
DS
Q15
SI2301BDS-T1-E3_SOT23-3
2
13
C760
10
U_
08
05
_10
V4Z
1
2
C7580.1U_0402_16V4Z
1
2
C759
10U_0805_10V4Z
1
2
FM31
FM41
C768
10
U_
08
05
_10
V4Z
@1
2
H10HOLEA
1
Q9A
2N
70
02
DW
-7-F
_S
OT
363-
6
61
2
R644
470_0402_5%
12
H 1HOLEA
1
R224470_0402_5%@
12
Q13B
2N
70
02
DW
-7-F
_S
OT
363-
6
3
5
4
R647
470_0402_5%
@
12
U32
AO4466_SO8
S 1
S 2
S 3
G 4
D8
D7
D6
D5
R643
470_0402_5%
12
U34
AO4466_SO8
@
S 1
S 2
S 3
G 4
D8
D7
D6
D5
R641
470_0402_5%
12
C650.01U_0402_16V7K@
1
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMDEC_SMC
SMB_EC_DA1
SMB_EC_CK1
ADP _SIGNAL
ADPINADPIN
ENTRIP1 <39>
BATT_OVP <32>
ENTRIP2 <39>
SMB_EC_CK1 <31,32,33>
SMB_EC_DA1 <31,32,33>
BAT_ID <38>
BATT_TEMP <32>
ADP_ID <32>
AC_LED <38>
+5VS
+5VALW
BATT
+5VALW
VMB
+3VL
BATT
VIN +DOCKVIN
+3VALW
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
M ontevina Blade UMA LA4101P 0.3
DC Connector/CPU_OTP
37 46Saturday, January 05, 2008
2007/05/29 2008/05/29Compal Electronics, Inc.
CPU
Recovery at 47 +-3 degree C
PH1 under CPU botten side :CPU thermal protection at 90 +-3 degree C
PQ3TP0610K-T1-E3_SOT23-3
2
13
PL2SMB3025500YA_2P
12
PR
44
99
K_
040
2_1% 1
2
PC
41
00
P_
04
02
_50V
8J 12
PU1ALM358ADT_SO8
+3
-20 1
P8
G4
PC
51
00
0P
_0
402
_50V
7K1
2
G
D
S
PQ1SSM3K7002FU_SC70-3
2
13
PR210K_0402_5%
12
PR310K_0402_5%
1 2
PC81000P_0402_50V7K
12
PU1B
LM358ADT_SO8
+5
-60 7
P8
G4
PC31000P_0402_50V7K
12
PC
10
.01
U_
04
02
_25V
7K
12
PR171K_0402_5%
12
PR8100_0402_5%
12
PR747K_0402_1%1 2
PC
60
.01
U_
04
02
_25V
7K 12
PC10
0.22U_0603_10V7K
12
PL4HCB2012KF-121T50_0805
1 2
PR166.49K_0402_1%1 2
PR1015K_0402_1%1 2
PR14100_0402_5%
12
PH110K_TH11-3H103FT_0603_1%
12
PR13
100_0402_5%
12
PL1SMB3025500YA_2P
1 2
PR15150K_0402_1%
12
PR510K_0402_5%
12
PC12
@1000P_0402_50V7K
12
PJP1
ACES_88334-057N
1 1
3 34 45 5
2 2
G
D
S
PQ2SSM3K7002FU_SC70-3
2
13
PC111000P_0402_50V7K
12
PD1
@PJSOT24C_SOT23-3
2 31
PL3HCB2012KF-121T50_0805
1 2
[email protected]_SOT23-3
231
PR11150K_0402_1%
1 2
PD2@SM05_SOT23
2
31
PC
21
00
P_
04
02
_50V
8J
12
PC90.01U_0402_50V4Z
12
PR
61
05
K_
040
2_1% 1
2P
R1
34
0K
_0
402_
1% 12
PD4
RLZ3.6B_LL34
12
PR122.55K_0402_1%
12
PJP2
SUYIN_200275MR008GXOLZR
1 1
3 34 45 56 6
GND 9
GND 10
2 2
7 78 8
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
D L_CHG
D H_ CHG
LX_CHG
P A C IN
C H GEN#
BST_CHG
R E GNV A DJ
BA
TT
ACDET
ACSET
IAD
AP
T
C H GEN#
FSTCHG#
ACDET
P A C IN
ACOFF#
ACOFF#
P A C IN
ACSET
IREF <32>
VCTRL<32>
ADP_I<32>
BAT_ID <37>
AC_SET<32>
S USP#<26,28,32,36,40,41>
ACIN <32>
STD_ADP <32>
FSTCHG<32>
ACOFF <32,39>
AC_LED<37>
V IN
P4
BATT
V IN
V IN
BATT
B+
P2
CHG_B+
CHG_B+
P2
V IN
+3VL
BQ24740VREF
1.24VREF
BQ24740VREF
+3VL
+3VL
+3VL
1.24VREF
P2
V IN
+3VLP
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Charger
38 46Saturday, January 05, 2008
2007/05/29 2008/05/29Compal Electronics, Inc.
Charge Detector
PD103RLZ4.3B_LL34
12
PC
124
0.1
U_
0603
_25V
7K
12
PC
129
47
0P
_040
2_50
V7K
12
PC119
1U_0603_10V6K
12
PC1021U_0603_6.3V6M
1 2
PR
138
10
0K
_040
2_1%
12
PR1020.012_2512_1%1 2
PC1250.1U_0603_25V7K
12
[email protected]_0402_16V7K
12
PC1230.1U_0402_10V7K 1
2
PC
116
4.7
U_
0805
_25V
6-K
12
PC
114
4.7
U_
0805
_25V
6-K
12
PR126100K_0402_1%
12
PC133470P_0402_50V7K
12
PC135470P_0603_50V8J
12
PQ110
AO4466_SO8
365 7 8
2
4
1
PR
128
10K
_040
2_5%
12
PC
101
47
P_
0402
_50V
8J
12
PR122681K_0402_1%1 2
PR
129
10
K_0
402_
1%1
2
PC
132
@1
00
0P_0
402_
50V
7K
12
PC111
0.1U_0402_10V7K
1 2
PC
130
27
0P
_040
2_50
V7K
12
PR
106
20
0K
_040
2_5%
12
PC
108
0.1
U_0
603_
25V
7K
12
PC
115
4.7
U_
0805
_25V
6-K
12
PQ101AM4835EP-T1-PF_SO8
365
78
2
4
1
PR117100K_0402_5%1 2
PR13310K_0603_0.1%
12
PR12710K_0402_1%
12
PR10147K_0402_5%
1 2
PR121200K_0402_1%
12
PR140100K_0402_5%
12
G
D
S
PQ113SSM3K7002FU_SC70-3
2
13
[email protected]_0603_25V7K
12
PR1231M_0402_5%1 2
PC
106
0.2
2U
_060
3_16
V7K
12
PR13410K_0402_5%
12G
D
S
PQ112SSM3K7002FU_SC70-3
2
13
PC1171U_0603_10V6K
12
PC128
@180P_0402_50V8J
1 2G
D
S
PQ107SSM3K7002FU_SC70-3
2
13
PC
105
4.7
U_0
805_
25V
6-K
12
PR12547_1206_5%
12
PR139100K_0402_5%
1 2
PR13720K_0402_1%
1 2PC127
22P_0402_50V8J
12
PR115100K_0402_1%
12
PQ108AO4466_SO8
365 7 8
2
4
1
PC
113
4.7
U_
0805
_25V
6-K
12
PC1260.047U_0402_16V7K
12
PR131133K_0402_1%
12
PC
134
10
00P
_040
2_50
V7K
12
PQ105DTC115EUA_SC70-3
2
13
PR13649.9K_0402_1%
1 2
G
D
S
PQ109
SSM3K7002FU_SC70-32
13
G
D
S
PQ111SSM3K7002FU_SC70-3
2
13
PQ106DTC115EUA_SC70-3
2
13
PR1040_0402_5%
1 2
PR109150K_0402_5%
12
PR13510K_0603_0.1%
12
PC
120
0.2
2U
_060
3_10
V7K 1
2PR118
10K_0402_5%1 2
PC112
1U_0603_6.3V6M
1 2
PC1101U_0805_25V6K1 2
PL10210U_LF919AS-100M-P3_4.5A_20%1 2
PR10810_1206_5%1 2
PR120
133K_0402_1%
12
PR1100_0402_5%1 2
PC
104
4.7
U_0
805_
25V
6-K
12
PR1302.15K_0402_1%1 2
PC
103
4.7
U_0
805_
25V
6-K
12
PR
132
100K
_040
2_5%
12
G
D
S PQ114SSM3K7002FU_SC70-3
2
13
PC
122
@0
.1U
_060
3_25
V7K
12
PU102B
LM393DG_SO8
+5
-6 O 7
P8
G4
PR10747K_0402_1%1 2
PC1180.1U_0402_10V7K
1 2
PR11639K_0402_5%
12
BQ24740RHDR_QFN28_5X5PU101
AC
P3
LPM
D4
CH
GE
N1
AC
N2
AC
DE
T5
AC
SE
T6
IADSLP8
SR
P19
BA
T17
IAD
AP
T15
PGND 22
SR
SE
T16
ISYNSET14
VADJ12
VDAC11
LPR
EF
7
VREF10
DP
MD
ET
21
LODRV 23
CE
LLS
20
SR
N18
AGND9
REGN 24
EXTPWR13
PH 25
HIDRV 26
BTST 27
PVCC 28
TP 29
PU102ALM393DG_SO8
+3
-2 O 1
P8
G4
PR1414.7_1206_5%
12
PL101HCB2012KF-121T50_0805
1 2
PC
121
10
0P
_040
2_50
V8J 1
2
PD101
1SS355_SOD323-2
1 2
PR1241K_0402_5%1 2
PR1113K_0402_1%
1 2
PU104
LMV431ACM5X_SOT23-5
NC 2
REF4
NC 1
CATHODE 3
ANODE5
PR10510K_0402_5%
12
PD102
RLS4148_LL34-2
12
PQ103AM4835EP-T1-PF_SO8
3 65
78
2
4
1
PR1120.015_1206_1%1 2
PQ104DTA144EUA_SC70-3
2
13
PR11947K_0402_5%
12
PR114@0_0402_5%
1 2
PR113143K_0402_1%
12
PC
131
@1
00
0P_0
402_
50V
7K
12
PQ102AM4835EP-T1-PF_SO8
3 65
78
2
4
1
PR10347K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LX_3V
U G_5V
LG_5V
LX_5V
LG_3V
UG
1_
5V
EN
TR
IP2
EN
TR
IP1
U G_3V
BST_3V BST_5V
U G1_3V
EC_ON <32>
ENTRIP2<37>ENTRIP1<37>
R_EC_RSMRST# <22>
ACOFF<32,38>
B++
+5VALWP
VL
+3VALWP
B++
B++
2VREF_51125
B+
+3VL+3VLP
+3VLP
2VREF_51125
VL +5VALWP
+3VALW
+5VALW
+3VALWP
+5VLVL
+3VL
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
M ontevina Blade UMA LA4101P 0.3
3.3VALWP/5VALWP
39 46Saturday, January 05, 2008
2007/05/29 2008/05/29Compal Electronics, Inc.
(4.5A,180mils ,Via NO.= 9)
(3A,120mils ,Via NO.= 6)PJP303
PAD-OPEN 4x4m
1 2
PC
30
51
0U
_1
20
6_2
5V6M
12
PC
30
61
0U
_0
80
5_
6.3V
6M
12
PL30310U_LF919AS-100M-P3_4.5A_20%
1 2
PL3024.7UH_SIQB74B-4R7PF_4A_20%
12
PC
31
80
.02
2U
_0
40
2_2
5V7K
12
PC3080.1U_0402_10V7K1 2
PC
31
6@
0.1
U_
04
02
_25
V4K
12
PC
31
11
0U
_0
80
5_1
0V6K
12
PC
31
5@
68
0P
_0
60
3_50
V7K
12P
R3
11
62
0K
_0
402_
5% 12
PC
30
42
20
0P
_0
402
_50V
7K 12
PJP301
PAD-OPEN 2x2m
2 1
PR314100K_0402_5%
12
+
PC
30
92
20
U_
6.3
VM
_R15
1
2
PQ302AO4466_SO8
365 7 8
2
4
1
PJP304
PAD-OPEN 2x2m
2 1
+
PC
31
01
50
U_
D_
6.3
VM
1
2
PQ304FDS6690AS_NL_SO8
365 7 8
2
4
1
PR306147K_0402_1% 1 2
PC
30
34
.7U
_0
80
5_
25V
6-K
12
G
D
S
PQ308SSM3K7002FU_SC70-3
2
13
PR30113.7K_0402_1%1 2
PR317604K_0402_1%
1 2
PC
31
4@
68
0P
_0
60
3_50
V7K
12
PU30274LVC1G14GW_SOT353-5
A2 Y 4
P5
NC
1
G3
PR
31
5@
4.7
_1
20
6_5% 1
2
PC
30
12
20
0P
_0
402
_50V
7K1
2
PR3080_0402_5%1 2
PJP302
PAD-OPEN 4x4m
1 2
PR30320K_0402_1%1 2
PC3070.1U_0402_10V7K
1 2
PR
31
6@
4.7
_1
20
6_5% 1
2
SP8K10S-FD5_SO8
PQ301
D121G 8
G23
1S/2D 5
D11
1S/2D 7
S241S/2D 6
PR307
0_0402_5%1 2
PC
31
20
.1U
_0
60
3_
25V
7K
12
G
D
S
PQ306SSM3K7002FU_SC70-3
2
13
PR318
0_0805_5%
1 2
PL301HCB2012KF-121T50_0805
1 2
G
D
S
PQ305SSM3K7002FU_SC70-3
2
13
PR313100K_0402_5%
1 2
PR305174K_0402_1% 1 2
PU301
TPS51125RGER_QFN24_4X4
VR
EF
3
TO
NS
EL
4
EN
TR
IP1
1
VF
B1
2
VF
B2
5
EN
TR
IP2
6
VREG38
DRVL1 19
VR
EG
517
GN
D15
VBST1 22
VIN
16
SK
IPS
EL
14
DRVL212
LL211
VO27
DRVH210 DRVH1 21
PGOOD 23
LL1 20
VC
LK18
VBST29
VO1 24
EN
013
P PAD25
G
D
S
PQ307
SSM3K7002FU_SC70-3
2
13
PR30230.9K_0402_1% 1 2
PC
30
20
.22
U_
06
03
_10V
7K
12
PR30420K_0402_1% 1 2
PC
31
7@
0.1
U_
04
02
_25
V4K
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DL_1.05V
1.05V_B+
+ 5VALW
LX_1.05V
BST1_1.05VBST_1.05V
D H_1.05V
SUSP#<26,28,32,36,38,41>
+VCCP+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+5VALW
+1.05V_VCCP
B+
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
M ontevina Blade UMA LA4101P 0.3
1.05V_VCCP
40 46Saturday, January 05, 2008
2007/05/29 2008/05/29Compal Electronics, Inc.
(6A,240mils ,Via NO.=12)
PR403316_0402_1%
12
PL401
HCB1608KF-121T30_06031 2
+
PC
40
82
20
U_
6.3
VM
_R15
1
2
PR40925.5K_0402_1%
12
PJP401
PAD-OPEN 4x4m
1 2
PR404255K_0402_1%
1 2
PR40618.7K_0402_1%
1 2
PR408
10.5K_0402_1%1 2
PC401@1000P_0402_50V7K
12
PR4020_0402_5%
1 2
PR4074.7_1206_5%
12
PR410@10K_0402_5%
12
PQ402FDS6690AS_NL_SO8
365 7 8
2
4
1
PC
40
52
20
0P
_0
402
_50V
7K
12
PC
41
4@
0.1
U_
04
02
_25
V4K
12
PR405
0_0402_5%12
PC406@680P_0402_50V7K
12
PC412220P_0603_50V8J
12
PR411
0_0402_5%1 2
PC
40
44
.7U
_0
80
5_
25V
6-K
12
PU401
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_PS
V1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12
GN
D7
PG
ND
8
TRIP 11
V5DRV 10
VB
ST
14
TP
15
PC4154.7U_0805_10V6K
12
PQ401AO4466_SO8
365 7 8
2
4
1
PC4020.1U_0402_10V7K
1 2
PC
40
34
.7U
_0
80
5_
25V
6-K
12
PR4010_0402_5%1 2
PL4022.2UH_PCMC063T-2R2MN_8A_20%
1 2
PC4091U_0603_10V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BST_1.8V
+1.8VP
LG_1.8V
UG1_1.8V
LG_1.5V
U G_1.8V
BST_1.5V
LX_1.5V
U G_1.5VUG1_1.5V
LX_1.8V
+1.5VSP
SUSP#<26,28,32,36,38,40>SYSON <26,32,33,36>
B+++
+1.8VP
B+
+1.5VSP
+5VALW
B+++
+1.8V+1.8VP
+1.5VS+1.5VSP
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
M ontevina Blade UMA LA4101P 0.3
1.5VSP/1.8VP
41 46Saturday, January 05, 2008
2007/05/29 2008/05/29Compal Electronics, Inc.
(7A,280mils ,Via NO.= 14)
(4A,160mils ,Via NO.=8)
PR50414.3K_0603_0.1%1 2
PR50173.2K_0402_1%
1 2
PJP502
PAD-OPEN 4x4m
1 2
PC5094.7U_0805_6.3V6K
12
PC
50
44
.7U
_0
80
5_
25V
6-K
12
PR5080_0402_5%12
PC
51
64
.7U
_0
80
5_
25V
6-K
12
PR5060_0402_5%
12
PC
52
1@
0.1
U_
04
02
_25
V4K
12
PC519@680P_0603_50V7K
12
PQ504
AO4466_SO8 36 578
2
4
1
PR50275K_0402_1%
1 2
PC
52
0@
0.1
U_
04
02
_25
V4K
12
PR5143.3_0402_5%
1 2
+
PC
51
7
22
0U
_B
2_
2.5V
M
1
2
PR51116.5K_0402_1%
12
PC5104.7U_0805_6.3V6K 1
2
PU501
TPS51124RGER_QFN24_4x4
GN
D3
TO
NS
EL
4
VO
11
VF
B1
2
VF
B2
5
VO
26
EN28
DR VL1 19
TR
IP1
17
V5F
ILT
15
VBST1 22
V5I
N16
TR
IP2
14
DR VL212
LL211
PGOOD27
DR VH210 DR VH1 21
EN1 23
LL1 20
PG
ND
118
VBST29
PGOOD1 24
PG
ND
213
P PAD25
PC5130.1U_0402_16V7K
12
+
PC
50
8
22
0U
_D
2_
4V
Y_
R25
M
1
2
PQ503FDS6690AS_NL_SO83
65 7 82
4
1
PQ501AO4466_SO8
365 7 8
2
4
1
PR5070_0402_5%
12
PC518@680P_0603_50V7K
12
PC
50
52
20
0P
_0
402
_50V
7K
12
PC5070.1U_0402_10V7K
1 2
PL5013.3UH_PCMC063T-3R3MN_6A_20%
1 2
[email protected]_0402_16V7K
12
PR5090_0402_5%
12
PC
50
14
.7U
_0
80
5_
25V
6-K
12
PR5120_0402_5%
1 2
PR51017.8K_0402_1%1 2
PL502HCB2012KF-121T50_0805
12
PC5060.1U_0402_10V7K
12
PQ502AO4466_SO8
36 578
2
4
1
PR5050_0402_5%
12
PJP501
PAD-OPEN 4x4m
1 2
PC
50
22
20
0P
_0
402
_50V
7K
12
PR517100K_0402_5%
12
PC5141U_0603_10V6K
12
[email protected]_1206_5%
12
PL5033.3UH_PCMC063T-3R3MN_6A_20%
12
PC5154.7U_0805_10V6K
12
[email protected]_1206_5%
12
PR50310.2K_0603_0.1%1 2
PR51310K_0402_5% 12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SUSP<36>
SYSON#<34,36>
+5VALW
+0.9VP
+1.8V
+ 0.9VP + 0.9V
Tit le
Size D o c u ment Number R e v
D a te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montev ina Blade UMA LA4101P 0 .3
0.9VP/1.1V_PCIE
42 46S a turday, January 05, 2008
2006/11/23 2007/11/23Compal Electronics, Inc.
(2A,80mils ,Via NO.= 4)
P R 6011K_0402_1%
12
P C 60510U_0805_6.3V6M
12G
D
S
P Q601S S M3K7002FU_SC70-3
2
13
PC
60
2@
10
U_
08
05
_1
0V
4Z
12
PC
60
40
.1U
_0
40
2_
16
V7
K
12
P C 6011 0U_0805_10V4Z
12
P R 6040_0402_5%
1 2
P C 6031U_0603_16V6K
12
P C 606@ 0.1U_0402_16V7K
12
P R 602@ 0_0402_5%
1 2
P JP601
P A D - O P EN 3x3m
1 2
P U 601
G 2 9 92F1U_SO8
VOUT4
NC5
GND2
VREF3
VIN1
VCNTL6
NC7
NC8
TP9
P R 6031K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UGA T E_CPU2-2
V S UM
V S UM
B OO T_CPU1
UGA T E_CPU1-1
LG ATE_CPU1
B OO T_CPU2
LG ATE_CPU2
UGA T E_CPU2-1
P HA S E_CPU2
VR_TT#
V CC_P RM
IS E N1V CC_P RM
V CC_P RM
P HA S E_CPU1
IS E N1IS E N2
V S UM
IS E N2
UGA T E_CPU1-2
CP
U_
VID
5
<7>
CP
U_
VID
3
<7>
CP
U_
VID
4
<7>
CP
U_
VID
6
<7>
CP
U_
VID
0
<7>
CP
U_
VID
1
<7>
CP
U_
VID
2
<7>
CLK_ENABLE#<17>
H_DPRSTP#<7,9,21>
DP RS LPVR<9,22>
VR
_O
N
<3
2>
V SSSENSE<7>
V CCS E NSE<7>
H_P SI#<7>
VGATE<17,22>
+3VS
+3VS
CPU_B+
+5VS
+VCC_CORE
+5VS
B+
CPU_B+
CPU_B+
Title
Size Documen t Number R e v
Da te: Sheet o f
0 .3
+CPU_CORE
Cus tom
43 46S a tu rday , January 05, 2008
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
P C2310.22U_0603_10V7K
12
P R221@0_0402_5%
1 2
P R244 3.57K_0402_1%
1 2
P C211
0.22U_0603_10V7K
1 2
P R201 499_0402_1%1 2
P H20110KB_0603_5%_ERTJ1VR103J
12
PC
23
8@
0.1
U_
04
02
_2
5V
4K
12
PL2020 .36UH_PCMC104T-R36MN1R17_30A_20%
12
P R204 0_0402_5%1 2
PR
21
00
_0
40
2_
5%1
2
P Q205F DS6676AS_SO8
365 7 8
2
4
1
P C2150.022U_0603_25V7K1 2
PR
23
11
0K
_0
40
2_
1%1
2
P R226 13K_0402_1%1 2
PR
21
30
_0
40
2_
5%1
2
P R234 1_0603_5%
1 2
PC
20
11
U_
06
03
_6
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6M
12
PR
22
94
.7_
12
06
_5
% 12
P R243 1K_0402_1%
1 2
PR
20
80
_0
40
2_
5%1
2
PR
21
93
.65
K_
08
05
_1
% 12
PC
23
34
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_0
80
5_
25
V6
-K1
2P C2020.022U_0402_16V7K
12
P C230 0.1U_0402_16V7K1 2
P R238
255_0402_1%1 2
PQ203F DS6676AS_SO8
365 7 8
2
4
1
IS L6262ACRZ-T_QFN48_7X7
P U201
PGOOD1
PSI#2
PMON3
RBIAS4
VR_TT#5
NTC6
SOFT7
OCSET8
VW9
COMP10
FB11
FB212
VD
IFF
13
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EN
14
RT
N15
DR
OO
P16
DF
B17
VO
18
VS
UM
19
VIN
20
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D21
VD
D22
ISE
N2
23
ISE
N1
24
NC 25
BOOT2 26
UGATE2 27
PHASE2 28
PGND2 29
LGATE2 30
PVCC 31
LGATE1 32
PGND1 33
PHASE1 34
UGATE1 35
BOOT1 36VID
037
VID
138
VID
239
VID
340
VID
441
VID
542
VID
643
VR
_ON
44
DP
RS
LPV
R45
DP
RS
TP
#46
CLK
_EN
#47
3V3
48
GN
D49
P R232
1_0402_5%
12
P C232 0.22U_0402_6.3V6K12
PC
23
54
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80
5_
25
V6
-K1
2
P C226 820P_0603_50V7K1 2
PR
20
70
_0
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5%1
2
P C220
470P_0402_50V7K
12
P Q201AO4474_SO8
S1
S2
S3
G4
D8
D7
D6
D5
P C2090.22U_0603_10V7K
1 2
PC
21
34
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_0
80
5_
25
V6
-K 12
PR
21
20
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40
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5%1
2
PL203
0 .36UH_PCMC104T-R36MN1R17_30A_20%12
PR
21
84
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12
06
_5
% 12
PC
21
94
70
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06
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0V7K
12
+
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20
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0.4
4
1
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22
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_0
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P C2170.22U_0603_10V7K
1 2
P C2280.01U_0603_50V7K
12
P R233 @0_0603_5%1 2
PC
20
72
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_0
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7K1
2
PR
23
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04
02
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12
PC
21
24
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_0
80
5_
25
V6
-K 12
P R2142.2_0603_5%
1 2
P C224 1000P_0402_50V7K1 2
P R2021_0603_5%
12
PR
24
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11
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04
02
_1%
12
P [email protected]_0603_50V7K
12
PC
20
64
.7U
_0
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V6
-K1
2
P R2272.2_0603_5%
1 2
PC
21
42
20
0P
_0
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2_
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7K1
2
P C2250.1U_0603_25V7K
12
PR
23
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08
05
_1
%
12
P R222 147K_0402_1%1 2
PR
24
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_0
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1%1
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P R206 0_0402_5%1 2
P C222 220P_0402_50V7K
1 2
P R23910_0603_5%
1 2
PR
21
6
1.9
1K
_0
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2_
1%
12
PR
20
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2
PR
20
90
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23
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PC
23
44
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25
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2
P R240 1K_0402_1%
1 2
P C218 1000P_0402_50V7K
1 2
P Q206F DS6676AS_SO8
365 7 8
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4
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P C2211U_0402_6.3V6K
12
+
PC
24
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_2
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0.4
4 1
2
P C2032 .2U_0603_6.3V6K
12
P C2161000P_0402_50V7K1 2
P R203 0_0402_5%1 2
PC
20
54
.7U
_0
80
5_
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V6
-K1
2
PQ204AO4474_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PQ202F DS6676AS_SO8
365 7 8
2
4
1
P R2231_0402_5%
12
PL201SMB3025500YA_2P
12
PC
23
7@
0.1
U_
04
02
_2
5V
4K
12
P R228 6.81K_0402_1%1 2
PC
23
64
.7U
_0
80
5_
25
V6
-K1
2
P R235 97.6K_0402_1%1 2
P R215
@499_0402_1%
12
P R225
0_0603_5%1 2
PC
21
04
70
P_
06
03
_5
0V7K1
2
P C223
0.22U_0603_10V7K
1 2
PC
24
02
20
0P
_0
40
2_
50V
7K
12
P C229 180P_0402_50V8J1 2
PR
21
10
_0
40
2_
5%1
2
+
PC
23
96
8U
_2
5V
_M
_R
0.4
4 1
2
PC
24
24
70
P_
04
02
_5
0V7K
1
2
P R2170_0603_5%1 2
P R224@0_0603_5%1 2
PC
20
81
00
0P
_0
40
2_
50V
7K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
PIR
44 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
Item (Reason for change)Fixed Issue PAGE Modify List Date
1 11/21C41、C42、C43、C44 Change ESR=7m ohmTransation Fail 08
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Phase
SI-1
Disable TV out function from Docking 11、34 R61 R62、 、R63 change to 75 Ohm、TV_DCONSEL_0、TV_DCONSEL_1 connect to GND
Update Connetor LibraryCRT(JCRT1)、HDMI(JHDMI1)、ESATA(JP53)、Finger print(JJP24)、FAN(JP2)、Speaker(JP60)、Multibay(JP12)、Dual LED(D53、D12)
Delete LVDS B channel 11、19 Schematic Delete
USB camera Footprint error 19 Change U42 to G916-390T1UF SOT23, it adjustable mode, R1091=215K,R1093=100K 11/07
11/17
11/17
11/07
Reserve Card reader D3E function 22、27 GPIO6= CR_CPPE#,GPIO22=CR_WAKE#
Swap PCIE LAN and New card 22 Swap PCIE4 and PICE6
11/17
11/17
Add HDCP ROM for ICH9M 22、31 Add HDCP ROM for ICH9M
Change G sensor control from SB、LED drive by +5VS 22、33 Change G sensor control from SB
11/17
11/17
Avoid Battery mode can't boot issue 22、39 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue 11/17
11/17Add G sensor ST and Bosch 24 Add G sensor ST and Bosch
Change LAN solution (Marvell to Realtek) 25
LAN can't work 25 U46 Change to correct transformer type
Change LAN solution (Marvell to Realtek) 11/17
11/17
Cardreader schematic review and update, add D3E function 27 R709-->10K R402、 -->8.2K、R704-->Stuff、R705-->@、U37-->@、Cardreader LED-->+5VS、add D3E function 11/17
Jack can't detect normal 28 R1059 change from 39.2 to 39.2K
Speaker work un normal 28 Add and Stuff C1362、R1065、R596
11/17
11/17
HP audio team recommend 28、29 C285~C292、C1352、C1354 change to 0.022U、Amp output setup to 15.6 dB、Reserve C305、C306 for GNDA and GND
Audio jack can't detect normal 29 Add Pull up resistor R401 to +3VALW
11/17
11/17
Docking HP audio test fail 29 Add C295�BC296 to avoid DC level, and add R409、R410 to reduce HP out level
Leakage problem 32 Correct direction pretect leakage 11/07
11/17
EC pin define update 32Delete EC_PME#、SYSON PU、SUSP# PU、LID_SW# change to +3VALW、Delete CLKRUN#、R582->@ for C0 chip、CIRPU+5VL、add 100P to BATT_OVP(EC recommend)
11/07
Can't Hibernation(SLP_S4#) 32 Connect SLP_S4# to SB
EC can't receive docking present CONA# change +3VL34
HDMI can't detect 35 DDC _EN must enable 、TMDS_B_HPD# inverse 11/07
11/12
11/17
01/03
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-1
SI-2
SI-2
SI-2
SI-2
LVDS power on timing 19 C238 change to 0.047u to meet TI timing
01/03
01/03
01/03
Prevent WWAN nosie 21 Add 12p on HDA_SDOUT and HDA_SDOUT
Power leakage 21、31 Change HDCP ROM to +3VS power plane
Prevent WLAN leakage 26 Add Diode prevent WLAN leakage
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
PIR 2
45 46S aturday, January 05, 2008
2007/08/28 2006/07/26Compal Electronics, Inc.
Item (Reason for change)Fixed Issue PAGE Modify List Date
29 01/03New card PTH connector GNDNew card PTH connector GND 26
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Phase
Change Cardreader LED control 27 Change Cardreader LED control
Change SPDIF to SPDIF1 Change to SPDIF1
Shut down pop noise 29 Change C293 to 1U
Change BT power to +3VS 30 Change BT power to +3VS
EMI Request 31 SPI_FSEL#、SPI_CLK_R、SPI_FWR# reserver RC
Reserver 0 ohm co lay with common choke 35 Reserver 0 ohm co lay with common choke
Sparate+5VS and +3VS power timing 36 Sparate+5VS and +3VS power timing
Keyboard backlight reserve a 0805 size resistor 33 Keyboard backlight reserve a 0805 size resistor
Change Lid switch connector type 33 Change Lid switch connector type
SI-2
SI-2
SI-2
SI-2
SI-2
SI-2
SI-2
SI-2
SI-2
SI-2
01/03
01/03
01/03
01/03
01/03
01/03
01/03
01/03
28
01/03
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number R e v
Da te: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Montevina Blade UMA LA4101P 0.3
Power Changed-List History-1Cus tom
46 46S aturday, January 05, 2008
2007/08/02 2008/08/02Compal Electronics, Inc.
Version Change List ( P. I. R. List ) for Power CircuitPage# Title Rev.Issue DescriptionItem Request
OwnerDate Solution Description
1 37Add PD4 & PC12
2
3
4
5
7
11/06DC Connector /CPU_OTP
for Layout
Compal
6
8
9
10
11
12
13
14
3.3VALWP/5VALWP Compal
Add PD4 & PC12
11/0639Change PQ301 cancel PQ303
38
43
Charger 11/06 Compal EMI solution
+CPU_CORE 11/06 Compal EMI solution
Add pc128
Add PC240
39 3.3VALWP/5VALWP 11/14 Compal for Layout Change PL303 and PC310
38 Charger 12/31 Compal EMI solution Add PC129, PC130, PC131, PC132, PC133
+CPU_CORE43 12/31 Compal EMI solution Add PC242
39 3.3VALWP/5VALWP 12/31 Compal PWR request Add PU302, control signal changed to ACOFF