comparative evaluation of buck and hybrid buck dc-dc converters for automotive applications

8/10/2019 Comparative Evaluation of Buck and Hybrid Buck DC-DC Converters for Automotive Applications

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Comparative Evaluation of Buck and Hybrid

Buck DC-DC Converters for Automotive

ApplicationsN. Muntean, O. Cornea, O. Pelan, C. Lascu

1University Politehnica of Timisoara, Department of Electrical Engineering, 300223 Timisoara, Romania

Abstract Many applications require a high step-down

ratio in DC-DC converters. Hybrid structures, using

switched-capacitors and/or switched-inductors, have been

reported as an alternative to high frequency transformer

converters. The object of this paper is a comparative study

of a switched-capacitor hybrid buck DC-DC converter

(HBDC) and a classical buck DC-DC converter (BDC) for

automotive applications. The hybrid converter uses a bank

of switched capacitors in order to halve the input voltage

available to the regular buck converter. Analytical aspects

and digital simulations, validated through experimental

results obtained from a full scale, 1kW rated power

prototype, are presented for this purpose.

Keywords DC-DC power converters, automotiveapplications, circuit topology.

I. INTRODUCTION

Dual voltage (14/42V) automotive power systems havethe possibility to convert the energy from the 42V to 14V

batteries/busses. When the power flow is unidirectional aDC-DC buck converter structure is used [1]. Fig. 1 showsthe typical topology of a dual power system with a buckconverter between the two busses.

A large number of converter topologies with highervoltage conversion ratios obtained from classical dc-dcconverters by adding additional components have been

presented in the literature [2-8]. Reference [2] presentsseveral modified uk converter topologies whichincorporate additional capacitors or inductors. Each new

passive component raises the input-to-output voltage ratiobut requires at least one additional diode and a transistor,which increases the complexity of the circuit and the cost.

Several configurations of quadratic converters obtainedby applying a systematic synthesis procedure arepresented in [3]. They can be used in applications whereextremely large range of voltage conversion ratios arenecessary and have the advantage of using only oneadditional transistor over two buck converters in cascade.

New step-down converter topologies have beenobtained by inserting simple circuits such as inductor-switching and capacitor-switching blocks in the structureof the classical DC-DC converters [4]. Figure 2 shows thetopology of a hybrid buck converter with switchingcapacitors. The capacitor-switching block contains twocapacitors and three diodes as can be seen in Fig. 2.awhere it is connected between node 1 and node 2.

New step-up converter configurations obtained byinserting a step-up C-switching block in uk, Zeta andSepic converters are presented in [5].

Fig. 1. Dual voltage automotive power system.

Fig. 2. Switched-Capacitor Hybrid Buck DC-DC Converter:

a) Converter schematic; b) ton switching topology;c) toff switching topology.

In a classical buck converter a low duty cycle (around

30%) is necessary, with relative high currents levels inthe active and passive components. High step-up andstep-down conversion ratios have been obtained by

15th International Power Electronics and Motion Control Conference, EPE-PEMC 2012 ECCE Europe, Novi Sad, Serbia

978-1-4673-1972-0/12/$31.00 2012 IEEE DS2b.3-1


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inserting a coupled-inductor cell formed by a coupledinductor and a diode, in buck, boost, buck-boost, uk,Zeta and Sepic converters reported in [6] and [7].

A unified method for developing step-up and step-down hybrid converter topologies with high voltageconversion ratio is described in [8]. The paper shows howeach hybrid converter can be derived from a main DC-DC converter by inserting an L-switching or a C-switching block in its structure. A comparison withclassical and quadratic DC-DC converters shows that inhybrid topologies the energy stored in the magnetic fieldof the inductors is somewhat higher than in classicalconverters and much lower than in quadratic converters.

This paper presents a comparison between theswitching-capacitor hybrid buck DC-DC converter(HBDC) described in [8] and the conventionaltransformerless buck DC-DC converter (BDC). Section IIdiscusses the theoretical aspects of the comparison, inanalytical and synthetic form, for the main current andvoltage waveforms, in continuous conduction (CCM) and

in boundary condition mode (BCM), which represent themain contributions of this paper. Section III is dedicatedto digital simulations and experimental results, andfinally the Conclusion section will synthesize the results.

II. ANALYTICAL DESCRIPTION OF HBDC

Figure 2.a shows the topology of the hybrid switched-capacitor buck DC-DC converter. Subfigures 2.b and 2.c

present the switching topologies of the HBDC during tonand toff time intervals. During one switching period thecapacitors are charged in series from the input voltageduring toff switching time, and discharged in parallelduring ton switching time as shown in Figs. 2.b, 2.c [7].Capacitors C1and C2have the same capacitance and the

input inductor Lin is added to reduce the input currentripple. A regular buck converter is connected followingthe switching capacitors. The HBDC in Fig. 2 iscompared with a conventional DC-DC buck convertershown in Fig. 3.

The steady-state analysis of the switched-capacitorHBDC converter, as in eqs. (1) and (2), determines itsinput to output voltage ratio. The volt-second balanceequations for Linand Loutcan be written as:

( ) ( ) ( )[ ] 021 =+ CinCin VVDVVD (1)

( ) ( ) ( )[ ] 01 =+ outCout VVDVD (2)

where: Vinis the input voltage; Voutis the output voltage;VCis the voltage drop across the capacitors C1and C2;Dis the duty cycle.

The input-output relation between Voutand Vinin (3) isobtained from (1) and (2).

inout VD

DV

=

2 (3)

The voltage stress TV of the HBDC transistor is given

by (4).

inT VV = 2 (4)

The approximate value of the transistor RMS current isgiven in (5) for BDC and HBDC (Ioutis the load (output)current).

outrmsT IDI =, (5)

HBDC boundary operation (between CCM and

Fig. 3. Conventional Buck DC-DC Converter:

discontinuous conduction mode) is provided by thefollowing equations, expressing the average values of thelimit currents through the input and output inductances:

)2(

)1(

2lim,

D

DD

fL

VI

s

inL

= (6)

when Vinis kept constant, and:

)1(2

lim, DfL

VI

s

outL

= (7)

when Voutis kept constant.Equations (6) and (7) are valid for both inductors,

thereforeIL,lim= ILin,limif L = Lin, orIL,lim= ILout,limif L =Lout. The maximum value of inductor current (6) and (7)is obtained forD=0.586, andD0, respectively:

s

inL fL

VI

=

66.11maxlim,, (8)

s

outL fL

VI

=

2maxlim,, (9)

From the equation of the output peak inductor current

Lout (10) and (11) we can write the per unit (p.u.)equation (12) for BDC [8, 9]. The p.u. equation forHBDC (14) can be obtained using (10) and (13).

outsout

outLout ID

fL

VI +

= )1(2

(10)

in

out

V

VD = 1)1( (11)

+=

in

out

Lout

out

Lout

Lout

V

V

I

I

I

I1

max,lim,max,lim,

(12)

+

=

+

=

in

out

in

out

outin

out

V

VV

V

VVVD

1

121)1(

(13)

+

+=

in

out

in

out

Lout

out

Lout

Lout

V

VV

V

I

I

I

I

1

1

max,lim,max,lim,

(14)

whereIoutis the average output current.From equations (3) to (14), a synthetic comparative

form of the main characteristics of both converters ispresented in Table I. The Table gives the analytical

equations for the converter transfer ratio, transistorvoltage and current, peak and average input currents, and

peak and average inductor currents.

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vout/Vin

IT,rms/Iout

BDC

HBDC

TABLEI.SYNTHETIC COMPARISON BETWEEN BUCK AND SWITCHED-CAPACITOR HYBRID BUCK CONVERTER

Converter

Function Buck (BDC) Hybrid Buck (HBDC)

inout VV / D DD

2

Transistor Maximum Voltage TV inV inV2

Transistor CurrentrmsTI , outID outID

avgTI , outID outID

ContinuousCurrentMode Peak Input Current

inI

.constVout = outSout

out IDfL

V+

)1(2

D

DID

fL

Vout

Sin

out

+

2)1(

2

.constVin = outSout

in IDDfL

V+

)1(2

D

DI

D

DD

fL

Vout

Sin

in

+

22

1

2

Peak Output Inductorand Transistor

Current

TLout II

=

.constVout = outSout

out IDfL

V+

)1(2

out

Sout

out IDfL

V+

)1(2

.constVin = outSout

in IDDfL

V+

)1(2

outSout

in ID

DD

fL

V+

2

1

2

BoundaryOperationMode

Maximum Average

Input Current

max,lim,LinI

.constVout = Sout

out

fL

V

2

forD0Sin

out

fL

V

2

forD0

.constVin = Sout

in

fL

V

16

forD=0.5Sin

in

fL

V

66.11

forD=0.586

Maximum Average

Output InductorCurrent

max,lim,LoutI

.constVout = Sout

out

fL

V

2

forD0

Sout

out

fL

V

2

forD0

.constVin = Sout

in

fL

V

8

forD=0.5Sout

in

fL

V

66.11

forD=0.586

Fig. 4 shows the duty cycle as a function of the voltageconversion ratio for both converters. For Vout/Vin=0.1HBDC has an almost double D and a correspondinglower maximum value of the peak transistor current.

Fig. 4. BDC and HBDC duty cycles as function of the conversion ratio.

Fig. 5 presents the p.u. approximate value of thetransistor rms currents (relative to the output current), asa function of the voltage conversion ratio for bothconverters. HBDC has the disadvantage of a higher rmstransistor current. For Vout/Vin=0.1 IT,rms of BDC is 25%lower.

Fig. 5. The p.u. t ransistor rms current for BDC and HBDC.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vout/Vin

D

BDC

HBDC

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vout/Vin

Iou

t/ILou

t,lim,m

ax

Vout - constant

BDC

HBDC

0 200 400 600 800 1000 12000.8

0.82

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

Pout

[W]

Efficiency

BDC

HBDC

Figures 6 and 7 summarize graphically the boundaryoperation of the converters at Vin= ct. and at Vout= ct.respectively.

For Vin=ct., if the voltage conversion ratio is smallerthan 0.45, HBDC enters DCM at a higher ratio of

Iout/ILout,lim,max. According to Table I the ratio betweenILout,lim,max values of BDC and HBDC is 11.66/8=1.4575.Considering this, it is clear that the absolute value of Ioutat BCM is smaller for HBDC for any Vout/Vin.

For Vout=ct., the two values of ILout,lim,max are the sameas can be seen in Table I and in this condition Fig. 6shows clearly that HBDC enters DCM at a lower outputcurrent.

Figure 8 presents the comparison between the p.u.values of Lout for Iout=ILout,lim.max, when Vout = constant.HBDC has a lower peak output inductor current for anyVout/Vin, but the difference between the two converters isonly in the range of several percents (the maximumdifference is slightly higher 10 %). For Vout/Vin=0.1 thedifference between the two p.u. peak values is about

0.4%. The same is true for the peak transistor current,which is smaller for HBDC.

Fig. 6. BDC / HBDC at the boundary operating mode, between CCMand DCM, at Vin= constant.

Fig. 7. BDC / HBDC at the boundary operating mode, between CCM

and DCM, at Vout= constant.

Fig. 8. The p.u.Loutfor BDC and HBDC, at Vout = constant.

III.DIGITAL SIMULATIONS AND EXPERIMENTAL RESULTS

In order to validate the theoretical considerations,digital simulations using PSim software were performed,and a 1 [kW] rated power HBDC presented in Fig. 9, was

built.

Fig. 9. HBDC prototype.

The parameters of the HBDC prototype are: Vin = 42[V], Vout= 14 [V],Iout= 100 [A],Lin=8 [H],Lout=4 [H],C1 = C2 = 29.92 [F], Cout=47.6 [F]. The diodes areSTPS200170TV1, 200 [A], 200 [V] and the transistor isIXFN120N20, 120 [A], 200 [V], 17 [m].

Figure 10 presents the comparison between theefficiency curves of BDC and HBDC converters atVin=42 [V] and Vout=14 [V].

Fig. 10. BDC / HBDC efficiencies curve.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

Vout/Vin

Lou

t/ILou

t,lim

,max

BDC

HBDC

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vout/Vin

Iou

t/ILou

t,lim,m

ax

Vin - constant

BDC

HBDC

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-30

-25

-20

-15

-10

-5

0

5

10

15

20

Time [us]

VLin

[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-30

-25

-20

-15

-10

-5

0

5

10

15

20

Time [us]

VLin

[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 220

25

30

35

40

45

50

55

60

65

70

Time [us]

V1

,2[V]

Figures 11 to 15 present the simulated andexperimental waveforms of the HBDC obtained for:Vin=42 [V], Vout=14 [V], Iout=67.75 [A] and a switching

period Ts=10 [s], in CCM.Figure 11 shows the voltage across the input inductor

(Lin), Fig. 12 shows the voltage across the C-switchingblock (V1,2 in Fig. 2), Fig. 13 shows the HBDCstransistor voltage, Fig. 14 shows the voltage of the outputdiode (Dout) and Fig. 15 shows the current (ILout) throughthe output inductor (Lout).

IV. CONCLUSION

In this paper the hybrid buck switched-capacitor DC-DC converter is compared with the classical buckconverter in continuous conduction mode and at the

boundary between CCM and DCM.

In section II and in Table I the equations for average,rms and peak transistor current, transistor voltage stress,

peak and average values of input and output inductorcurrents (which depends whether Vin or Vout is kept

constant) are presented and discussed. The theoreticalequations presented for comparison in this paper wereverified using simulation models with ideal components.

A comparative evaluation of a switched-capacitorHBDC and BDC was presented and validated throughdigital simulations and experimental results.

From Table I, and Fig. 4 to 10, the following mainconclusions can be drawn:

- For the same conversion ratio, HBDC works at ahigher duty cycle, with positive aspects in theconverter control.- HBDC boundary conditions are better. If theconverter has to operate in CCM or at BCM, at the

same output current as BDC a lower outputinductance is needed for the HBDC;- BDC has a smaller RMS transistor current whichgives reduced conduction losses in transistor for thisconverter;- The peak transistor current is lower for HBDCwith positive effects regarding the switching device;

- The output inductor of HBDC can be smaller orfor the same value of the output inductance the peakcurrent is slightly reduced;- The maximum voltage across the transistor (in theworst case) is two times higher for HBDC;- It can be seen that in the range of the output power

between 0 - 400 W in Fig. 10, HBDC efficiency isbetter than that of the BDC. If the output to inputvoltage ratio changes it is possible that theintersection point between the efficiency curves ofBDC and HBDC move to the right, HBDC becomingmore efficient. Further investigations are needed hereto find the range of the voltage ratio for whichHBDC is more efficient for a larger range of the

output power.- HBDC contains a larger number of active and

passive components. This structure affects theconverter efficiency, presented here for thecomparative evaluation. This aspect must be studiedin the future, especially in an implementation withmore efficient power devices.

As a final conclusion HBDC ensures a lower peaktransistor and output inductor currents; the higher dutycycle value ensures a wider converter control domain inthe range of the voltage conversion ratio. Compared to aDCDC converter with transformer, the elimination of thehigh frequency transformer decreases the cost, volumeand looses for this converter.

Fig. 11. The voltage across input inductorLinfor HBDC: simulated (left) and experimental (right) waveforms.

Fig. 12. The voltage across the C-switching block (V1,2in Fig. 2): simulated (left) and experimental (right) waveforms.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 220

25

30

35

40

45

50

55

60

65

70

Time [us]

V1,2

[V]

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-10

0

10

20

30

40

50

60

70

80

Time [us]

VDS

[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-10

0

10

20

30

40

50

60

70

80

Time [us]

VDS

[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-10

-5

0

5

10

15

20

25

30

35

40

Time [us]

V

Dou

t[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.2 1.6 1.8 2-10

-5

0

5

10

15

20

25

30

35

40

Time [us]

V

Dou

t[V]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 255

60

65

70

75

Time [us]

ILou

t[A]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 255

60

65

70

75

Time [us]

ILou

t[A]

Fig. 13. HBDC transistor voltage: simulated (left) and experimental (right) waveforms.

Fig. 14. HBDC output diode voltage: simulated (left column) and experimental (right column) waveforms.

Fig. 15. HBDCILoutcurrent: simulated (left column) and experimental (right column) waveforms.

ACKNOWLEDGEMENT

This work was partially supported by the strategic grant POSDRU107/1.5/S/77265 (2010) of the Ministry of Labor, Family and SocialProtection, Romania, co-financed by the European Social Fund Investing in people.

REFERENCES

[1] Energy Efficient Vehicles for Road Transport EE-VERT,Seventh Framework Programme, grant reference SCS7-GA-2008-

218598, www.ee-vert.net;[2] R. D. Middlebrook, Transformerless DC -to-DC Converters with

Large Conversion Ratios, in IEEE TRANSACTIONS ONPOWER ELECTRONICS, vol. 3. No. 4, October1988, pp. 484-488;

[3] D. Maksimovic, and S. uk, Switching Converters with Wide DCConversion Range, in IEEE TRANSACTIONS ON POWERELECTRONICS, vol. 6, No. 1, January 1991, pp. 151-157;

[4] B. Axelrod, Y. Berkovich, and A. Ioinovici, Switched-Capacitor(SC) Switched-Inductor (SL) Structures for Getting Hybrid Step-

Down Cuk/Zeta/Sepic Converters, in Proc. IEEE Int. Symp.Circuits Syst. (ISCAS), Kos Island, Greece, May 21-24 2006, pp.5063-5066;

[5] B. Axelrod, Y. Berkovich, and A. Ioinovici, Hybrid Switched-Capacitor uk/Zeta/Sepic Converters in Step-Up Mode, in Proc.IEEE Int. Symp. Circuits Syst. (ISCAS), Kobe, Japan, May 23-262005, pp. 1310-1313;

[6] B. Axelrod, Y. Berkovich, and A. Ioinovici, Switched Coupled-Inductor Cell for DC-DC Converters with Very Large ConversionRatio, in IEEE Industrial Electronics (IECON), Paris, France,November 6-10 2006, pp. 2366-2371;

[7] B. Axelrod, Y. Berkovich, S. Tapuchi and A. Ioinovici, SteepConversion Ratio uk, Zeta and Sepic Converters Based on aSwitched Coupled-Inductor Cell, in 39thIEEE Power ElectronicsSpecialists Conference, Island of Rhodes, Greece, June 15-192008, pp. 3009-3014;

[8] B. Axelrod, Y. Berkovich, and A. Ioinovici, Switched-Capacitor/Switched-Inductor Structures for GettingTransformerless Hybrid DC-DC PWM Converters, IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS, vol. 55, No. 2,March 2008, pp. 687-696;

[9] N. Mohan, T. Undeland and W. Robbins, Power Electronics:Converters, Applications and Design, John Wiley, New York,1995;

[10] M. Rashid, Power Electronics: Circuits, Devices andApplications,Prentice Hall, NJ, 1988.

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comparative evaluation of buck and hybrid buck dc-dc converters for automotive applications

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