comparision on low -noise n eural signal amplifiers and design of c urrent mirror ota ... · 2018....

Comparision on Low-Noise Neural Signal

Amplifiers and Design of Current Mirror OTA

for EEG 1Lipika Gupta and

2Amod Kumar

1Chitkara University, India.

2CSIO, Chandigarh.

Abstract In an endless effort for developing new assistive technologies to treat

neural disorders, neural interface technology has seen tremendous

progress. For designing analog front-end in neural interface system, the

Low Noise Amplifier (LNA) design for low frequency neural signals is still

a challenging task. Specific design requirements for neural LNA require a

decent understanding of various topologies used for its implementation.

This paper discusses standard design parameters and their desirable values

for LNA design. A comparison of System-level architecture: Open loop and

Closed-Loop topologies are also presented. A summary of various

strategies is explained based on the improvement in design for low power,

low noise and area. The current mirror OTA with capacitive feedback

topology is simulated using 0.18µm technology node using BSIM3V3 MOS

Transistor Model from Cadence. Using gm/Id methodology for selection

the operating point the transistors, a low noise and low power amplifier

design has been obtained.

Keywords: LNA; Neural amplifier; Input reffered noise; PSRR; NEF;

CMRR; OTA.

International Journal of Pure and Applied MathematicsVolume 119 No. 12 2018, 14769-14784ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

14769

1. Introduction

Low Noise Amplifier (LNA) is the first gain stage of any receiver. While ample

of the research is concentrated on the design of LNA for high frequency

applications, it is much popular for low frequency designs as well. LNA is an

integral part of Neural Recording Microsystem which is used to analyze very

low frequency brain signals [1]. Neurons communicate with each other and

generate neural signals which can be used to analyze the brain activity. The

meticulous monitoring of these signals supported by modern IC technology can

enable persons in locked-in position to use various prosthetic devices effectively.

The most commonly used non-invasive method to record neural activity by

placing electrodes on scalp is Electroencephalography (EEG) (1µV to 100mV)

[2]. Several invasive methods such as electrocorticography (ECoG), intracortical

involve placement of electrically-conductive sharp microelectrodes resting on

the brain tissue are performed inside the body. These electrodes are followed by

the bank of LNAs for signal conditioning and further processing. Fig. 1 shows

the typical components of channel for neural acquisition.

LNABand Pass

FilterVGA BUF ADC

Fig 1: Block diagram neural acquisition channel [3]

Low amplitude Neural signals (5µV to 500µV) are acquired by the probes are

applied at the input of LNA. Pre-amplification is critical as it determines the

overall performance of the acquisition channel. It determines the overall gain,

noise and power performance of the entire system. Consequently, low power

consumption, lesser area and low noise are the desirable characteristics of typical

LNA used in Neural Recording channel. It is also designated as neural amplifier

and terms LNA and neural amplifiers has been used interchangeably. Amplified

neural signals are digitalized or analyzed in the subsequent stages [4]. Band-pass

filter (BPF), variable-gain amplifier (VGA), buffer (BUF), and analog-to-digital

converter (ADC) are the signal processing blocks which further analyze

amplified neural signal for particular application [2].

CMOS technologies and circuit techniques have facilitated the development and

miniaturization of these circuits. Many researchers have contributed to the

development of state of art LNAs for low frequency. The Low-noise and Low-

power amplifier designed by R. Harrison [5] in 2003 is the most important

contribution. Fig. 2 shows the schematic of the LNA with capacitive feedback

and Transconductance amplifier which influence all researchers.

International Journal of Pure and Applied Mathematics Special Issue

14770

Fig 2: Low Noise Amplifier for neural signal amplification [5]

Future demands massive integration of multi-channel recoding systems which

can record 100-1000 neurons simultaneously and can be used for non-clinical

applications such as sports and entertainment [6].

This paper presents various design parameters for LNA design and their

desirable values and tradeoffs in Section II. Circuit topology plays the most

important role to achieve the desired parameter values. Section-III discusses

various circuit-level and system-level topologies for Amplifier design. The

implementation of current mirror OTA is discussed in Section-IV.

2. LNA design parameters

The important design parameters, such as noise performance, power

consumption, CMRR and size of LNA have to be considered while designing a

neural recording microsystem. The key design parameters are discussed as

follows [4, 5, 7]:-

A. Input Reffered Noise

At low frequencies, the two main components of noise are: thermal noise and

flicker noise, collectively known as input-referred noise. MOSFET transistors

suffer from low frequency flicker noise which is inversely proportional to the

transistor area and the operating frequency. Therefore, pMOS transistors which

large channel area are used as the amplifier input transistors. The thermal noise

is caused by recording electrodes and amplifier transistors. The amplifier must

have low input referred noise to avoid debasing of neural signals and resolve the

signals for such small amplitude.


14771

B. Noise Efficiency Factor (NEF)

NEF used to evaluate how efficiently an amplifier uses its bias current to reduce

noise [7].

(1)

where is the input referred noise, k is Boltzmann’s constant (1.38 x 10−23

m2 kg s

−2 K

−1), T is the temperature in Kelvins (body temperature = 310 K), VT

is the thermal voltage (25.9 mV at body temperature), ID is the transistor bias

current, and BW is the -3 dB amplifier bandwidth. Smaller the value of NEF is

desired for more efficient the circuit, low input-referred noise and consuming

small power.

C. Common Mode Rejection Ratio (CMRR)

The CMRR of neural amplifier is measurement of its capability to reject

common-mode signals. It is the ratio between the amplitude of the common-

mode signal to the amplitude of an equivalent differential signal [8]. Power-line

interference from ac sources and other common-mode signals will appear at the

amplifier output if the CMRR of the amplifier is low. Thus high value of

CMRR is desired for neural amplifiers.

D. Power Supply Rejection Ratio (PSRR)

Due to very small amplitude of neural signals, the supply voltage variations and

fluctuations have to be rejected for proper amplification. These variations are

significantly larger than the neural signal. High PSRR of the amplifier will

amplify the input neural signal rather than the power supply variations.

In addition to above design parameters, Dynamic range, input impedance,

bandwidth and area are other important parameters for LNA design. Table-1

summarizes standard values of these design parameters [4, 6].

3. Design of Neural Amplifiers

Neural amplifier which can achieve the above mentioned characteristics can

be designed using wide variety of techniques. However design tradeoffs of

microelectronic systems obstruct the simultaneous improvement of all the

parameters. Nevertheless the objective is to develop efficient neural interfaces

for examining brain activity in an improved manner. The designs can be

categorized broadly in two ways: Circuit-level architecture and System-level

architecture [9]. In Fig. 1, the design of transconductance amplifier deals with

circuit-level architecture and the use of this circuit-topology for implementation


14772

of front-end amplifier as Open-Loop or Closed-loop amplifiers is the System-

level architecture.

Table-1: Standard values of Design parameters

Design

Factor

Typical

Range Comments

1 -

5µVrms

Sufficiently low to

resolve signals of

smaller magnitude

Dynamic

Range

40-120

dB

Sufficient

dynamic range to

convey signals of

1-2mV

Input

impedance

100MΩ-

10TΩ

Higher than the

electrode tissue

interface

Bandwidth 0.1-

10kHz

Amplification of

low frequency

bio-signals

Area 0.1-10

cm2

Minimum Area

CMRR

60-120

dB

High to minimize

the interference

from 50/60Hz

power line

PSRR 40-80

dB

High to reject

noise form power

supply

NEF 2-6 Lower the NEF

better is the design

E. Circuit-level architecture:

For Implementing Low Noise and Low power Operational Transconductance

Amplifier (OTA) topologies are used. OTA is a voltage input and current output

amplifier. The transconductance gm is proportional to the iDS drain current and

increases the current efficiency of the amplifier [5]. Fig. 3 shows the schematic

of current mirror OTA used in neural amplifier in Fig.2 as introduced by R.

Harrison. The same has been used for implementation in 180nm technology

node described in Section IV. In this the sub-threshold operation of the input

pMOS transistors is preferred where gm is proportional to the square root of the

drain current, resulting low power and low-bandwidth characteristics which are

well suited for biomedical applications.


14773

The Drain current iDS, transconductance gm, and Unity –gain frequency ft in

weak inversion region are as follows:

Researchers have exploited different types of OTAs such as two stage Millar

OTA, Current mirror OTA, Folded cascode OTA and telescopic OTAs for

improvement in the design parameters. For low noise design current mirror

OTA [10-13] and two stage opamp [11-13] are most widely used. For low

power design folded cascode, telescopic cascode, fully differential self-biased

OTAs are most widely used.

Fig 3: Current mirror OTA for Neural amplifier [5]

F. System-level Arhitecture:

The above stated circuit topologies for can be used for implementation of neural

amplifier for enhancing the design parameters. Different system-level

topologies such as open-loop, capacitive feedback, active feedback, adaptive

feedback topologies ruminate in the change of the characteristics of neural

amplifiers for low frequency input signal. A typical three-opamp

Instrumentation amplifier is suitable for achieving large input impedance, large

CMRR and sufficient gain [6]. However, it consumes large power and area.

Similarly open loop neural amplifiers achieve better noise performance at the

cost of linearity and reduced PSRR. Thus a clear insight of these architectures is

imperative in order to design neural amplifier for a particular application. Open-


14774

loop and closed-loop (capacitive feedback) topologies are discussed below and

a brief comparison is provided for various designs available till date.

Open-Loop Topology:

Nonexistence of feedback loop leads to lesser number of circuit components in

Open-loop topology. Thus low power consumption is the integral property. At

the same time, open loop topology suffers from inaccuracy in gain due to

process-voltage-temperature (PVT) [14]. According to [14] open loop also

introduces larger offset than closed loop amplifiers. However, proper

compensation and design strategy can overcome these disadvantages. The

design purposed is shown in Fig. 4.

The fully differential OTA using Gm - Gm architecture was designed on 130nm

1P8M CMOS technology and show more promising results when compared

with [5]. In addition, [15] used the circuit shown in Fig. 5. The strategy to

reuse current and restrict the number of current braches reduced power and

noise in the circuit. Excellent power efficiency is received at the expense of

linearity and gain accuracy.

Fig 4: Open-loop LNA [14]

Fig. 5: Schematic of Neural amplifier in Open-loop topology [15]


14775

Following table compares the standard parameters of the [14], [15] and [5]. This

is apparent that the open-loop topology used in [14] is most promising in terms

of NEF, PSRR and gain.

Table 2: Comparison of Design parameters of Open-loop topologies

Design

Factor [14]

[15] [5]

Technology 0.13µm 0.5µm 1.5µm

VDD (in V) 1.5 1-5 2.5

Gain (in

dB) 37

36.1 40

(µVrms) 5.5

3.6 2.2

Dynamic

Range -

- 69 dB

Bandwidth 5 Hz -

7kHz

0.3Hz -

4.7k Hz

.025

Hz-

7.2kHz

Area - 0.46mm2 .16mm

2

NEF 2.58 1.8 4.0

PSRR 67dB 5.5 dB 85 dB

1) Capacitive-Feedback Tolpology:

As shown in Fig. 2, Capacitive feedback topology is most extensively

borrowed model from last two decades. In the original model, diode-connected

PMOS (Pseudo-Resistor) Ma, Mb, Mc and Md and small capacitor C1 and C2 craft

low pass response for neural amplifiers. The researchers have been making effort

to design more energy efficient neural amplifiers so that thousands of such

amplifiers can be used in muti-electrode systems. [16] is an important

contribution for micropower design. The design uses the same circuit as in Fig. 1

followed by Band-pass filter stage to shape the passband of the amplifier. With

the addition of this BPF the amplifier can record neural signals of < 1Hz-1kHz

frequencies which includes spikes as well. For achieving low power, instead of

using current mirror OTA, modified folded cascode circuit topology has been

used [16]. Current in each branch is scaled by different W/L ratio of transistor in

each branch. This technique leads to the significant reduction in power of the

circuit refer Fig 6.


14776

Fig. 6: Schematic of Low power Folded Cascode OTA [16]

In another approach to reduce power and area for muti-electrode neural

amplifiers, partial OTA sharing is used [17]. The array of n neural amplifiers,

same as in Fig.2, is used with minor modifications. The vref voltage and C1 is

shared with all n-amplifiers in array, hence leading to lower area and power as

compared to array n individual amplifiers design. However, this design reports

cross talk between channels which is required to be addressed properly. An ultra-

low power Bio-potential amplifier reported in [18] compares three amplifiers

based on different circuit-level topologies of OTAs and single ended and

differential output of the amplifier. A closed-loop fully complementary-input

differential amplifier is designed with improved power-noise performance. The

design parameters are also compared with [5] and are highlighted in Table 3 as

well. The further improvement in design of neural amplifiers has also been

reported in terms of change in on-chip pseudo-resistance implementations [6, 22]

Fig. 7 (a) and modifications feedback capacitor (C2) network [19] Fig. 7 (b).

These modifications lead to low area and low noise design of neural amplifier.

(a)

(b)

Fig 7: (a) Pseudo-resistor outward and inward connected gates, balanced

tunable with wider linear range [6], (b) T-type single ended capacitive

coupled amplifier [19]


14777

Most recent trend is towards designing amplifiers which not only amplify neural

signals, but can be reconfigured for amplification of other Bio-signals signals as

well. Floating gate transistors have ability to be programmed have been used in

[20, 21] to make bio-sensing amplifier that meets the stringent requirements in

neural recording applications. A standard fully differential capacitive feedback

topology is adopted for reconfigurable design [20] and gate balanced

reconfigurable pseudo-resistors are used [21]. Fig. 8 shows the schematic used

for reconfigurable design. The detailed comparison of this configuration with

others is given in Table 3.

Fig. 8: Floating-gate OTA employed in reconfigurable Bio-potential amplifier [20,21]

Table 3: Comparison of Design parameters of Capacitive-feedback topologies


14778

4. Implementation of Current Mirror Ota Using Capacitive Feedback Toplogy

This section shows the employment of capacitive feedback topology on Current

Mirror OTA (Fig.2 & Fig.3) [5]. The circuit has been simulated using 0.18µm

technology node using BSIM3V3 MOS Transistor Model from Cadence. The

design suitable for amplification of very low amplitude and frequency signals

such as EEG and neural spikes. The values of C1, C2 and CL were set at 20pF,

200fF and 5opF to obtain the gain of 40dB. C1 and C2 set the midband gain

AM=C1/C2, the bandwidth was approximated by gm/(AMCL) to 10kHz. The

schematic of Current mirror is same as Fig.2. The bias current is kept 100nA to

accommodate lower bandwidth and hence low value of gm. The drain current of

50nA flows through the devices M1- M8. Using gm/Id method [23] and

mentioned value of drain current, the W/L ratio of each transistor is calculated

for the desired operating point. For low noise operation the W/L ratio of input

pmos transistors was kept high and thus operates in sub-threshold region.

Fig.8 shows the gm/Id plot for pmos transistor for different values of Inversion

coefficient (IC) and the operating region for the device. The Inversion

Coefficient (IC) [5] for all devices expressed as:

(5)

where ID is the drain current and Is is moderate inversion current given by:

(6)

where VT is the thermal voltage (25.9 mV at body temperature), κ is the sub-

threshold gate coupling coefficient having a typical value of 0.7 [4,5].

Fig.8: gm/Id Vs Inversion coefficient plot for pmos transistor

1.00

10.00

0.00001 0.001 0.1 10

Tra

nsc

on

du

cta

ceE

ffic

ien

cy, g

m/I

D

Inversion Coefficient, IC=ID/IS

gm/Id

Weak

Inversion

Strong

Inversion


14779

The calculated W/L values are further optimized for low power and low noise to

obtain the desired gain as close as possible considering the tradeoffs. Table 4

shows the operating conditions and W/L ratios of all the transistors in the circuit.

Table 4: Operating points of OTA transistors Device W/L(µm) ID (nA) IC gm/ID (V-1) Operating region

M1, M2 74/0.36 50.0 0.07 25.3 Sub-threshold

M3, M4, M5, M6 0.42/8.9 50.0 2.27 12.9 Moderate

M7, M8 0.24/1.8 50.0 3 11.7 Moderate

M9, M10 0.24/0.36 100.0 0.21 22.8 Moderate

McasN 0.42/2.7 50.0 0.68 27.87 Sub-threshold

McasP 0.24/.45 50.0 0.17 23.42 Sub-threshold

The simulated value of the gain of the amplifier is shown Fig. 9. The maximum

gain obtained is 38.02dB and the obtained bandwidth is from 0.1Hz to 5.01 kHz.

Fig.9: gm/Id Vs Inversion coefficient plot for pmos transistor

The standard design parameters of the circuit is compared with [5] and [22] in

Table 5. The results show the improvement in terms of gain and noise. The total

power consumed by the circuit is 593.5nW.

Table 4: Comparison of Simulated design parameters with similar OTAs Design

Factor [5] [22] [This work]

Technology 1.5µm 0.18µm 0.18µm

VDD (in V) 2.5 0.8 1.8

Gain (in dB) 40 31.7 38.04

(µVrms) 2.2 5.62 5.01

Bandwidth .025Hz-

7.2kHz 3-164Hz

0.1Hz-5.01

kHz

NEF 4.0 6.33 4.22

CMRR 88 dB Not

mentioned 70dB

PSRR 85 dB 54 dB 55dB

1

20

0.10 1.00 10.00 100.00 1,000.00 10,000.00

Ga

in (

dB

)

Frequency (Hz)


14780

5. Discussion

The future neural prosthetic devices demand better reliability, long life and

perfect biocompatibility. Thus non-invasive methods of neural signal

acquisition require better amplifiers. For designing of improved amplifiers

particularly for non-invasive methods like EEG, better understanding of the

various existing neural amplifiers is required. The purpose of doing this

comparison is to understand various design parameters involved for designing

neural amplifiers and the desirable values. From these specifications, circuit-

level topologies are discussed in brief. Open-loop and capacitive-feedback type

system-level architecture is discussed in more details. Open-loop circuits

provide better noise performance whereas capacitive feed is most popular

topology. Recent research is focused on capacitive feedback topology using

reconfigurable floating gate OTA based design. It is evident that the complexity

of neural recording microsystems is increasing while its effective size is

decreasing. Hence low power and low noise design is a challenging task.

6. Conclusion

This paper described that design of LNA is most significant task of Neural

recording microsystem. We presented various design parameters and their

desirable values for Neural signal amplification. Some main OTA designs for

circuit-level architecture are highlighted; the most common one is the current-

mirror OTA. System-level architecture is described for Open-loop and

capacitive feedback topologies. Some main techniques for low-power, low-

noise designs are: implementation of Pseudo-resistors, modification in the

feedback network capacitor, use of partial OTA in n-array implementation,

using floating gate transistors for reconfigurable designs. In an effort to make

low noise and low power neural amplifier, Current Mirror OTA is simulated

using 0.18µm technology node using BSIM3V3 MOS Transistor Model from

Cadence. The W/L ratios are optimized to for improved gain of 38.04dB,

NEF=4.22 and input referred noise of 5.01 µVrms. Thus it can be concluded the

design is suitable for amplification of low amplitude and low frequency

biomedical signals. Improvements in Integrated Circuit technology and design

optimization will continue to enhance the design of LNA for better clinical and

non-clinical applications.

References

[1] Ruiz-Amaya, J., “A Review of Low-Noise Amplifiers for Neural Applications”, In Proceedings of the 2nd Circuits and Systems for Medical and Environmental Applications, Merida, Mexico, pp. 13–15 December 2010.

[2] R. Harrison, “A versatile Integrated circuit for Acquisition of Biopotential signals,” In Proceedings of IEEE Custom Integrated circuits conference, pp. 115-122, 2007


14781

[3] K. Wise and J. Angell. “A microprobe with integrated amplifiers for neurophysiology”. In proceedings Solid-State Circuits Conference, Digest of Technical Papers, 1971 IEEE I nternational, vol. 14, pp 100-101, Feb. 1971.

[4] R. Harrison, “The design of Integrated Circuits to Observe Brain Activity”, In Proceedings of IEEE, vol.96, pp. 1203-1216, July 2008.

[5] R. Harrison, C. Charles, “ A Low-power Low-Noise CMOS Amplifier for Neural Recodring Appliations,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 958-964, June 2003.

[6] H. Sohmyung, Chul Kim, Yu M. Chi, Abraham A., Christoph M., Akinori U., Gert C., “Inegrated Circuits and Electrode interfaces for Non-invasive Physiological Monitoring”, IEEE Transactions on Biomedical Engineering, vol. 61, no. 5, pp. 1522-1537, May 2014.

[7] Ferrari G., Gozzini F., Molari A., Sampietro M., “Transimpedance amplifier for high sensitivity current measurements on nanodevices” IEEE Journal of Solid State Circuits, vol. 44, pp. 1609–1616, 2009.

[8] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2000.

[9] E. Bharucha, H. Sepehrian, B. Gosselin,”A Survey of Neural Front End amplifiers and their requirements toward practical Neural Interfaces”, Journal od Low Power Electronic Applications, Vol. 4, pp. 268-291, 2014.

[10] Johnson B., Molnar A., “An orthogonal current-reuse amplifier for multi-channel sensing”, IEEE Journal of Solid Stare Circuits, vol.48, pp. 1487–1496, 2013

[11] Mollazadeh M., Murari K., Cauwenberghs G., Thakor N.V., “ Wireless micropower instrumentation for multimodal acquisition of electrical and chemical neural activity” IEEE Transactions on Biomedical Circuits Systems, vol. 3, pp. 388–397, 2009.

[12] Kazerouni I.A., Dehrizi H.G. Isfahani, S.M.M. Zhuo, Z. Baghaei-Nejad, M.; Li-Rong, Z., “A 77 nW Bioamplifier with a Tunable Bandwidth for Neural Recording Systems” In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur,Malaysia, pp. 36–39, December 2010

[13] Kim J., Chae M.S. Liu, W., “A 220 nW Neural Amplifier for Multi-Channel Neural Recording Systems”, In Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1257–1260, Taipei, Taiwan, 24–27 May 2009.


14782

[14] Vikram Chaturvedi, Bharadwaj Amrutur, “An Area-Efficient Noise-Adaptive Neural Amplifier in 130nm CMOS Technology”, IEEE J Circuits and Systems, 2011, Vol. 1, No. 4, 536-545.

[15] J. Holleman, B. Otis, “A sub-microwatt Low noise Amplifier for Neural Recording”, In Proceedings of 29th Annual International Conference of IEEE EMBS, Lyon, France, pp. 3930-3933, Aug 2007.

[16] Wattanapanitch W., Fee M., Sarpeshkar R., “An energy-efficient micropower neural recording amplifier”, IEEE Transactions on Biomedical Circuits Systems,vol.1, pp 136-147, 2007.

[17] Majidzadeh, V., Schmid, A., Leblebici, Y. “Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor”, IEEE Transctions on Biomedical Circuits Systems, vol. 5, pp. 262-271, 2011.

[18] Zhang F., Holleman J., Otis B.P., “Design of ultra-low power biopotential amplifiers for biosignal acquisition applications,” IEEE Transactions on Biomedical Circuits Systems, vol. 6, pp. 344-355, 2012.

[19] K.A. Ng, Yong Ping Xu, “A Compact, Low input capacitance Neural recording amplifier”, IEEE Transactions on Biomedical Circuits Systems,vol.7, pp 610-620, Oct. 2013.

[20] T. Yun, Min-Rui Lai, Christopher M. Twigg, S.Y. Peng, “A Fully Reconfigurable Low-noise Biopotential Sensing Amplifier with 1.96 Noise Efficiency Factor”, IEEE Transactions on Biomedical Circuits Systems,vol.8, pp 411-422, June 2014.

[21] T. Yun, Li-Han Liu, S.Y. Peng, “A Power Efficient Highly Linear Reconfigurable Biopotential Sensing Amplifier using Gate-balanced Pseudo-resistors”, IEEE Transactions on Circuits & Systems,vol.62, No. 2, pp 199-203, Feb 2014.

[22] S. Dwivedi, A.K. Gogoi, “Local Field Potential Measurement with Low-Power Area Efficient Neural Recording Amplifier”, In proceedings of IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), pp. 1-5, 19-21 Feb 2015.

[23] F. Silerira, D. Flandre, P.G.A. Jespers, “A gm/Id based methodology for design of CMOS analog circuits and its application to synthesis of a Silicon-in-Insulator Micropwer OTA”, IEEE Transactions on Solid State Circuits,vol.31, No. 9, pp 1314-1319, Sept 1996.


14783

comparision on low -noise n eural signal amplifiers and design of c urrent mirror ota ... · 2018....

Documents