complex combinational circuits binary adders key to enterprise: addition table also a truth table s...

Complex Combinational Circuits

Binary AddersKey to enterprise: Addition table also a truth table

Si = Ci'AiBi' + Ci'Ai'Bi + CiAi'Bi'+ CiAiBi

Ci+1 = CiBi + AiBi + CiAi

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

Inputs Outputs Ci Ai Bi Si Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

A iB i

C i0 0 0 1 1 1 1 0

0

1

1 1

1 1

AA iB i

C i0 0 0 1 1 1 1 0

0

1

1

11 1

B


Binary AddersAlternative representationSi = (Ci XOR (Ai XOR Bi)) Ci+1 = AiBi + Ci(Ai XOR Bi)

Notes: i) Full adder (shown) composed of 2 half adders (dotted boxes)ii) Example of minimization for multiple outputs (XOR reused)

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

A iB i

C i

S i

C i+ 1


Binary AddersRipple-carry adder (for multiple column additions)

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4


Binary AddersCarry-look-ahead

Ci+1 = AiBi + Ci(Ai XOR Bi)Ci+1 = Gi + PiCi (recursion relation)

where Gi = AiBi and Pi = Ai XOR Bi

example of recursion calculation Ci+2 = Gi+1 + Pi+1Ci+1

= Gi+1 + Pi+1(Gi + PiCi) = Gi+1 + Pi+1Gi + Pi+1PiCi

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

G i+ 1

P i+ 1

G i

P i+ 1P iC i

C i+ 2


Binary AddersTwo’s complement addition

Notes:i) M indicates subtraction (flips Bi’s, and adds 1)ii) detects overflow when carry in does not match carry out for last column

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

F A

A 0

B 0

F A

A 1

B 1

F A

A 2

F A

A 3

S 0 S 1 S 2 S 3

C 0 C 1 C 2 C 3 C 4

M

B 2 B 0

O F


Decodersn-bit code to m-bit code, where m > nBinary decoders

only active output line corresponds to binary quantity at inputExample (2-to-4 binary decoder)

Note: Enable turns circuit on.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

INPUTS OUTPUTS

EN I1 I0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0 1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0


DecodersBinary decoders

Example (2-to-4 binary decoder)

circuit symbol

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

ENI 0

I 1

Y 0

Y 1

Y 2

Y 3

I 0

I 1

E N

Y0

Y1

Y2

Y3

d eco d er


DecodersActive high and active low

Abstraction from 0’s and 1’sA circuit always does the same thing from the point of view of activity; however, input and outputs can change

Example (active low enable; active low output)

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

INPUTS OUTPUTS EN I1 I0 Y3 Y2 Y1 Y0 1 x x 1 1 1 1 0 0 0 1 1 1 0

0 0 1 1 1 0 1

0 1 0 1 0 1 1

0 1 1 0 1 1 1

I0

I1

EN

Y0

Y1

Y2

Y3

d eco d er


DecodersCascading decoders

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

I0

I1

E N

Y0

Y1

Y2

Y3

d eco d er

I 0

I 1

E N

Y0

Y1

Y2

Y3

d eco der

N0

N1

N2

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

INPUTS OUTPUTS N2 N1 N0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 1

0 1 0 1 1 1 1 1 0 1 1

0 1 1 1 1 1 1 0 1 1 1

1 0 0 1 1 1 0 1 1 1 1

1 0 1 1 1 0 1 1 1 1 1

1 1 0 1 0 1 1 1 1 1 1

1 1 1 0 1 1 1 1 1 1 1


DecodersApplications

Realizing an SOP

PQ + QR ≡ PQR(3,6,7)

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

I 0

I 1

EN

Y0

Y1Y2

Y3

d eco d er

Y4Y5

Y6Y7

3 -t o -8

I 2


DecodersApplications

Driving a LED display

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

Y0Y1Y2Y3Y4Y5Y6Y7Y8Y9

I0

I1

I2

I3

top s e gm e n t

bottom l e fts e gm e n t


Encodersn-bit code to m-bit code, where n > m

Binary encoderscreates binary representation of active input

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

INPUTS OUTPUTS I7 I6 I5 I4 I3 I2 I1 I0 N2 N1 N0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1


EncodersProblem: What if more than 1 input line is active?

Solution: Use priority encoding

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

INPUTS OUTPUTS I3 I2 I1 I0 N1 N0 GS 0 0 0 0 0 0 0 0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

I3I2

I1

N 1

N 0

G SI0


Multiplexers and Demultiplexers

Multiplexers select from among multiple inputsDemultiplexers select from among multiple outputs

Note: sources and destinations can be arbitrarily wide.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

m u ltip lex e r( M UX )

d em u litp lex e r(D E M UX )

s ou rce 0

s ou rce 1

s ou rce 2

s ou rce 3

des t in at ion 2

des t in at ion 1

des t in at ion 0

des t in at ion 3

s ou rces elect 0

s ou rces elect 1

d es t .s elect 0

des t .s elect 1

B US


Multiplexers

Example (4-input 1-bit multiplexer)

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

EN S1 S0 OUT 0 x x 0 1 0 0 I0

1 0 1 I1

1 1 0 I2

1 1 1 I3

S0

S1

O U T

EN

I0

I1

I2

I3


Multiplexers

More examples 8-input 1-bit 4-input 2-bit

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

EN S2 S1 S0 OUT 0 x x x 0 1 0 0 0 I0

1 0 0 1 I1

1 0 1 0 I2

1 0 1 1 I3

1 1 0 0 I4

1 1 0 1 I5

1 1 1 0 I6

1 1 1 1 I7

EN S1 S0 OUT A OUT B 0 x x 0 0 1 0 0 I0A I0B

1 0 1 I1A I1B

1 1 0 I2A I2B

1 1 1 I3A I3B


Multiplexers

ApplicationsTime Division Multiplexing 1100 01110010 0101

Realizing a function

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

A BC D 0 0 0 1 11 1 0

0 0

0 1

11

1 0

1

1

1

1

1

1

1

4 -in p u t 1 -b itM U X

D

0CD

1

ou t p u t


Demultiplexers

Decoders and demultiplexers identical!

A 2-to-4 decoder recast as a 4-output 1-bit demultiplexer

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

INPUTS OUTPUTS S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 EN 0 1 0 0 EN 0

1 0 0 EN 0 0

1 1 EN 0 0 0


Programmable logic devices (PLD’s)

Compromise between gate-level design and application-specific integrated circuit (ASIC)

1) Programmable Read Only Memory (PROM)

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

0123

I0I1I2I3

4 -t o -1 6d eco d er

...12131415

Y0Y1Y2Y3Y4Y5Y6Y7




2) Programmable Array Logic (PAL®)F1 = ABC + A'D' + B'CD' F2 = ACD' + B'D

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

A A' B B' C C ' D D '

F 1

F 2




3) Programmable Logic Array (PLA)F1 = A'B' + ABC + A'CDF2 = A'B' + C'D' + AC' + CD'F3 = A'CD + AC'

.

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

AA'BB'CC 'DD '

F 1

F 2

F 3

P1 P2 P3 P4 P5 P6


Summary of Topics

AddersFull adderRipple-carry adderCarry-look-aheadTwo’s complementDecodersEncodersMultiplexersDemultiplexerPLD’sPROM’sPAL’sPLA’s

F A

A 0 B 0

F A

A 1 B 1

F A

A 2 B 2

F A

A 3 B 3

S 0 S 1 S 2 S 3

C 0C 1 C 2 C 3 C 4

complex combinational circuits binary adders key to enterprise: addition table also a truth table s...

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