April 5, 2012 Copyright © 2012 Agilent Technologies

Welcome

Hsieh-Hung Hsieh (PhD) Technical Manager / RF Design Program TSMC

George Estep RFIC Application Development Engineer Agilent EEsof

Agenda

• TSMC 60-GHz CMOS RDK • RDK Solution Approach • 60-GHz CMOS Design Opportunities and Applications • 60-GHz Reference Design

• Comprehensive mm-Wave Simulation & Modeling Solutions

• Top-down ESL architecture verification • RFIC circuit simulation & verification • EM analysis & verification • Consideration of off-chip components & parasitics

• Summary and Q&A

2

© 2012 TSMC, Ltd

TSMC Property RDK Solution Approach

A silicon-proven RF reference circuits and methodology packaged into a complete RF reference design kit (RDK):

Reference circuit design with correlated simulation and measurement data.

Methodology for simulation of substrate noise with substrate networks.

Provide RF basic cell (RBC) and RF building block (RBB) modules with

friendly navigator GUI support.

Enable complicated RF analyses including phase noise, substrate noise

analysis, and EM simulation.

Provide TSMC developed PDK superset devices and IP.

Design collaboration with key ecosystem partners.

© 2012 TSMC, Ltd

TSMC Property

• RF Behavior Model Block Spec. Sizing, System KPI definition System Yield Optimization

• Core Feature (60G Wireless design) LNA, VCO and PA

EM Comprehensive Flow • Compliant to TSMC dummy rules • Seamless simulation flow • Auto behavior model generation

Ecosystem Partners

RF RDK Introduction

Differential Pair

Cross Couple Logic Inductor

Scalable VCO

RF Basic Cell

Core Design

60GHz Wireless Design

Cascoder

• Substrate Noise Analysis Analyze substrate noise coupling in RF circuits

© 2012 TSMC, Ltd

TSMC Property

5

60-GHz CMOS Design Opportunities and Applications

WirelessHD Target on wireless

HDMI

Wireless HDMI Uncompressed

HDTV

ECMA TC48 MAC, PHY and

wireless Video

802.15.3c Wireless PC interface

Mobile device HDMI

IEEE 802.11.ac/ad 802.11 serial

Below 6G & 60G

© 2012 TSMC, Ltd

TSMC Property

6

Motivation of 60-GHz Design 60-GHz band:

High atmospheric attenuation

Higher throughput:

Never ending demand of high data rate

Support more and more users or applications

7 GHz of unlicensed spectrum (57-64 GHz)

Flexible use of spectrum resource

Communication in a wide range of frequency bands

Smaller on-chip passives Higher integration Single-chip transceivers

Technology scaling enables low-cost 60-GHz radio SoC in silicon.

Spectrum full within 5G Underused Spectrum 57G-64GHz

© 2012 TSMC, Ltd

TSMC Property

7

Applications of 60-GHz RFIC:

Applications of 60-GHz RFIC

“Emerging technology”, WiGig Alliance Newest Office

© 2012 TSMC, Ltd

TSMC Property

8

60-GHz wireless design: Setup millimeter wave very high throughput design flow

Achieve reliable measurement results

Enable RF top-down design methodology to perform system level simulation with behavior model solution

Extra devices/ transmission line support

RDK 60G 65nm Design Package

Provide RF frontend circuits (LNA, PA, and VCO)

Achieve reliable simulation/measured results

Extra device support

Provide reference design flow and function validation

© 2012 TSMC, Ltd

TSMC Property

9

TSMC 60-GHz RF Frontend Architecture Based on a heterodyne architecture (two-step conversion).

Frequency planning: 60-GHz RF, 48GHz LO1, 12-GHz IF.

RDK circuit scope: LNA, PA, and VCO.

LNA IFA

/4LO2_I

LO2_Q

PA IFA

VCO

LO1

© 2012 TSMC, Ltd

TSMC Property

10

60-GHz Microstrip-Line-Based LNA The proposed 60-GHz LNA is composed of three gain stages.

The transmission lines are realized in microstrip lines.

VB1

RFoutRFin

VDD1

VB2

VDD2

VB3

M1

M2

M3

M4

M5

M6

VDD3

Microstrip Line

© 2012 TSMC, Ltd

TSMC Property

11

60-GHz Microstrip-Line-Based LNA Operate at a supply voltage of 1.0 V.

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

S 21 (

dB)

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

S 11

(dB

)

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

S 22 (

dB)

0

2

4

6

8

10

58 59 60 61 62 63 64 65Frequency (GHz)

NF

(dB

)

SimulationMeasurement

© 2012 TSMC, Ltd

TSMC Property

12

60-GHz Microstrip-Line-Based LNA With 5T model, more accurate silicon correlation can be achieved.

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

Mag

(S21

) (dB

)

SimulationMeasurement

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

S 21 (

dB)

4T model 5T model

© 2012 TSMC, Ltd

TSMC Property

13

Impact of different metal scheme:

Difference of gain between 1P9M and 1P6M at 60 GHz is 3 dB.

Difference of NF between 1P9M and 1P6M at 60 GHz is 0.4 dB.

More metal stack is beneficial to circuit performance.

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

Mag

(S21

) (dB

)

1P6M1P9M

60-GHz Microstrip-Line-Based LNA

© 2012 TSMC, Ltd

TSMC Property

14

60-GHz Slow-Wave-TL-Based LNA Slow-wave-TL-based LNA:

With the use of slow-wave TL, the compact chip area can be obtained.

Due to the decrease of insertion loss, for a targeted gain, the required dc power

can be reduced while noise performance becomes better.

MS-LNA, Area = 1.5 x 1.3 mm2

SW-LNA1, Area = 1.5 x 0.9 mm2

SW-LNA2, Area = 0.8 x 1.1 mm2

Similar Layout Style (31% Reduction in Chip Area)

Take Advantage of GND Sidewall (35% Reduction in Chip Area)

Total 55% Reduction in Chip Area

© 2012 TSMC, Ltd

TSMC Property

15

60-GHz ESD Reference Design 4kV ESD capability is achieved by using combination of short-circuited and open-

circuited stubs.

Difference of gain between LNA w/i and w/o ESD at 60 GHz is 0.2 dB.

Difference of NF between LNA w/i and w/o ESD at 60 GHz is 0.5 dB.

© 2012 TSMC, Ltd

TSMC Property

16

60-GHz Transformer-Based PA Based on a three-stage differential transformer-coupled architecture.

To stabilize the circuit, the gate resistors are employed in three gain stages.

VG

1

V DD

V DD

V DD

RFout

M2

M1

M2

M1

M3

M3

M4

M4

VDD

RFinVDD

VG

2

VG

3

Microstrip Line

© 2012 TSMC, Ltd

TSMC Property

17

The frequency response of each stage is provided in the following figure.

With the increase of coupling capacitor Cc, the cross-coupled pair is formed in the

pseudo-differential common-source stage, leading to possible oscillation.

-12

-9

-6

-3

0

50 55 60 65 70 75 80Frequency (GHz)

Nor

mal

ized

Gai

n (d

B)

Input Matching + TF1 The 1st Gain Stage The 2nd Gain Stage The 3rd Gain Stage

-100

-50

0

50

100

150

200

10 20 30 40 50 60 70 80 90 100Frequency (GHz)

Stab

ility

Fac

tor

C = 0 fF C = 20 fF C = 40 fF C = 60 fF C = 80 fF C = 100 fF

CcCcCcCcCcCc

Ma1 Ma2

Cc

Cc

60-GHz Transformer-Based PA

© 2012 TSMC, Ltd

TSMC Property

18

Operate at a supply voltage of 1.0 V.

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

S 21

(dB

)

Meas Sim

-20

-10

0

10

20

-20 -15 -10 -5 0 5Input Power (dBm)

Out

put P

ower

(dB

m)

60-GHz Transformer-Based PA

© 2012 TSMC, Ltd

TSMC Property

19

The frequency shift is observed (~ 1 GHz) with the EM corner simulation.

The simulation results indicate that the wideband operation of 60-GHz circuit is essential.

PVT EM Corner Simulation

© 2012 TSMC, Ltd

TSMC Property

20

48-GHz Wideband VCO The proposed 48-GHz VCO adopts a thermometer-weighted switched-capacitor array

for wideband operations.

-VO+VO

M1

VDD

M2

B0

VTUNE

B6

VB_VCO

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7B0 0 1 V 1 V 1 V 1 V 1 V 1 V 1 V B0B1 0 0 1 V 1 V 1 V 1 V 1 V 1 V B1B2 0 0 0 1 V 1 V 1 V 1 V 1 V B2B3 0 0 0 0 1 V 1 V 1 V 1 V B3B4 0 0 0 0 0 1 V 1 V 1 V B4B5 0 0 0 0 0 0 1 V 1 V B5B6 0 0 0 0 0 0 0 1 V B6

© 2012 TSMC, Ltd

TSMC Property

21

44

46

48

50

52

54

56

0.0 0.2 0.4 0.6 0.8 1.0Controlled Voltage (V)

Osc

. Fre

quen

cy (G

Hz)

48-GHz Wideband VCO

Meas Sim

44

46

48

50

52

54

56

0.0 0.2 0.4 0.6 0.8 1.0Controlled Voltage (V)

Osc

. Fre

quen

cy (G

Hz)

Operate at a supply voltage of 1.0 V.

© 2012 TSMC, Ltd

TSMC Property

22

Summary on 60-GHz Reference Design

Critical building blocks of 60-GHz RFIC: LNA, PA, and VCO.

Utilize new devices: transmission line for LNA.

Include circuit database, model, and complete design flow.

Circuit-level silicon validation with millimeter-wave models.

Agilent EEsof within the 60-GHz RDK

Focus of 60-GHz RDK summary: • Combination of fundamental circuit blocks, design flows,

documentation and models intended to introduce mm-wave design in TSMC 65GP process technology upgraded for 60-GHz application.

Circuit simulation in the 60-GHz RDK: • RDK bundled PDK elements:

• RF MOS transistor, MOS-Varactor, MOM cap, poly resistor, and inductor models specifically for 60-GHz design

• Transmission line library

• Pad structures

• Design Elements: • 60-GHz LNA, Power Amp and 48-GHz Wideband VCO circuit designs

complete with schematic and layout views plus simulation and verification test benches

• Design and simulation workshop covering: • RF circuit simulation with GoldenGate including advanced Monte Carlo and

corner technologies, advanced convolution and accurate ADS libraries

• EM modeling of interconnects, transformers and inductors with Momentum

• Bottoms up transistor level performance model generation for system level verification with GoldenGate & SystemVue

VG

1

VD

D

VG

2

VD

D

VG

3

VD

D

RFout

M2

M1

M2

M1

M3

M3

M4

M4

RFin

VDDT1

VDDT1

R1R1

R1 R1

R1

R1

VB1

RFoutRFin

VDD

VB2

VDD

VB3

VDD

M1

M2

M3

M4

M5

M6

T1

T2

T3

T4

T5

T6

T7

T8

T9

CB1 CB2 CB3

C1 C2 C3

T10

T11

T12

T13

T14

T15

T16

T17

CB4

T18

T19

R1 R2 R3

VDD

L1

VDD

L2

VDD

L3

M1

LP1 LP1

VDD

M2

Vctrl

B0C C

Msw1

CORE

M3

LP2 LP2

Ibias2

M4

BUF VDD

Ibias1

B6C C

Msw7

Cvar Cvar vout

23

Agilent EEsof 60-GHz RDK contributions

Inputs from System-level

Schematic Entry

Circuit Simulation

Layout

DRC/LVS

Parasitic Extraction

GDSII or SOC integration

24

Agilent EEsof 60-GHz RDK contributions

Inputs from System-level

Schematic Entry

Circuit Simulation GoldenGate

Layout

DRC/LVS

Parasitic Extraction

GDSII or SOC integration

Inductor & Passive Component Design

Package & Bond wire modeling

RF-ESL Analysis & Design support

25

GoldenGate – RFIC Design and Verification

SystemVue Verification

GoldenGate FCE

Momentum Simulator

Broadband SPICE Model

Generator

S-parameter

Component Options

QFN Designer

Agilent EEsof 60-GHz RDK contributions

• Top-down ESL architecture verification • Verify at every level vs. consistent 802.11ad TX/RX references

• RFIC circuit simulation & verification • Full characterization of complete RF transceiver prior to tape-out

• EM analysis & verification • Enable EM analysis early and often through integrated solvers

• Add off-chip effects & components in overall verification • Addressing integration issues early in the design cycle

26

Agilent EEsof 60-GHz RDK contributions

• Top-down ESL architecture verification • Verify at every level vs. consistent 802.11ad TX/RX references

• RFIC circuit simulation & verification • Full characterization of complete RF transceiver prior to tape-out

• EM analysis & verification • Enable EM analysis early and often through integrated solvers

• Add off-chip effects & components in overall verification • Addressing integration issues early in the design cycle

27

Top-down ESL architecture verification Verify at every level vs. consistent 802.11ad TX/RX baseband references

Initial downconverter system architecture (RF chain used directly in system- level performance study)

1 3

PRE-COMPLIANCE BB/RF Test Device

Fast Circuit Envelope verification (PA model exported from GoldenGate extracted view, includes freq response, nonlinearity, memory effects)

2

Download to T&M (use the same test vectors for hardware verification, - 12-Gsa/sec AWG, - 32-GHz oscilloscope, - same PHY measurement algorithms)

28

Initial 60GHz Transceiver Architecture

• Initial architecture selection and block spec refinement with SpectraSys

• Architecture and block spec validation vs. consistent 802.11ad TX/RX baseband references in SystemVue

1

29

0- to 200-GHz Spectrums & Noise at RX nodes

30

802.11ad PHY simulated results with RFIC CMOS PA, multipath fading, noise: EVM=2.5%

31

2

Agilent EEsof 60-GHz RDK contributions

• Top-down ESL architecture verification • Verify at every level vs. consistent 802.11ad TX/RX references

• RFIC circuit simulation & verification • Full characterization of complete RF transceiver prior to tape-out

• EM analysis & verification • Enable EM analysis early and often through integrated solvers

• Add off-chip effects & components in overall verification • Addressing integration issues early in the design cycle

32

TSMC 60-GHz CMOS mm-Wave RDK Circuit Example: Transformer coupled Power Amp

Schematic Layout

Circuit simulation: DC, S-Parameters, Pout vs Pin, IP3, Noise Figure, ACPR, PAE, Load Pull, Corners, Monte Carlo

VG

1

V DD

VG

2

V DD

VG

3

V DD

RFout

M2

M1

M2

M1

M3

M3

M4

M4

RFin

VDDT1

VDDT1

R1R1

R1 R1

R1

R1

EM simulation: • Component level: Input/output GSG pads, Transformers, Transmission lines. • Block level: Passives + interconnects

33

GoldenGate overview and 60-GHz RDK usage Best-in-class RF circuit simulator: • Full characterization of complete RF transceivers prior to tape-out • Supports all large and small signal RF and transient analyses including large

signal stability and newly added X-parameter simulation support

Advanced analysis support: • Broad statistical analysis support like for worst-case PVT corners, various

Monte Carlo options and Fast Mismatch & Yield Contributor Analysis • Unique transistor-level PLL Jitter and Noise option

Automation & ease-of use: • Built-in and easy access to multi-dimensional sweeps, Optimization, Monte Carlo

or load-pull analysis along with simulation management capabilities • Automated EVM, ACPR, Gain Compression, IP3, and load-pull

Unique mm-Wave design support: • Provides access to ADS Data Display with dedicated RF templates and

adsLib with over 150 RF distributed element library components • Handling largest S-Parameter blocks with Multi-Threaded Convolution

Wireless standard-compliant verification: • Verify full radio functionality using Agilent’s wireless libraries for LTE, WCDMA,

WiMAX, DTV... • Enables scalable system-level solutions from RF architecture exploration

through end-to-end verification with links to SystemVue

VG

1

VD

D

VG

2

VD

D

VG

3

VD

D

RFout

M2

M1

M2

M1

M3

M3

M4

M4

RFin

VDDT1

VDDT1

R1R1

R1 R1

R1

R1

VB1

RFoutRFin

VDD

VB2

VDD

VB3

VDD

M1

M2

M3

M4

M5

M6

T1

T2

T3

T4

T5

T6

T7

T8

T9

CB1 CB2 CB3

C1 C2 C3

T10

T11

T12

T13

T14

T15

T16

T17

CB4

T18

T19

R1 R2 R3

VDD

L1

VDD

L2

VDD

L3

M1

LP1 LP1

VDD

M2

Vctrl

B0C C

Msw1

CORE

M3

LP2 LP2

Ibias2

M4

BUF VDD

Ibias1

B6C C

Msw7

Cvar Cvar vout

34

TSMC 60-GHz CMOS mm-Wave RDK Power Amp characterization in GoldenGate

Full characterization of performance metrics: NF, Pout vs Pin, IP3, Load Pull, PAE, ACPR, …

VG

1

V DD

VG

2

V DD

VG

3

V DD

RFout

M2

M1

M2

M1

M3

M3

M4

M4

RFin

VDDT1

VDDT1

R1R1

R1 R1

R1

R1

35

-30

-20

-10

0

10

20

30

40 45 50 55 60 65 70 75 80Frequency (GHz)

Mag

(S21

) (dB

)

SimulationMeasurement

Gain vs. Frequency

Agilent EEsof 60-GHz RDK contributions

• Top-down ESL architecture verification • Verify at every level vs. consistent 802.11ad TX/RX references

• RFIC circuit simulation & verification • Full characterization of complete RF transceiver prior to tape-out

• EM analysis & verification • Enable EM analysis early and often through integrated solvers

• Add off-chip effects & components in overall verification • Addressing integration issues early in the design cycle

36

Momentum in the 60-GHz RDK

37

VG

1

VD

D

VG

2

VD

D

VG

3

VD

D

RFout

M2

M1

M2

M1

M3

M3

M4

M4

RFin

VDDT1

VDDT1

R1R1

R1 R1

R1

R1

VB1

RFoutRFin

VDD

VB2

VDD

VB3

VDD

M1

M2

M3

M4

M5

M6

T1

T2

T3

T4

T5

T6

T7

T8

T9

CB1 CB2 CB3

C1 C2 C3

T10

T11

T12

T13

T14

T15

T16

T17

CB4

T18

T19

R1 R2 R3

VDD

L1

VDD

L2

VDD

L3

M1

LP1 LP1

VDD

M2

Vctrl

B0C C

Msw1

CORE

M3

LP2 LP2

Ibias2

M4

BUF VDD

Ibias1

B6C C

Msw7

Cvar Cvar vout

Most popular 3D planar electromagnetic simulator: • Advanced NlogN and multi-threading solver algorithms for optimal speed,

accuracy and capacity • Arbitrary polygonal meshing with mesh reduction • Thick metal analysis of side wall currents and efficient via modeling, accounting for

skin and proximity effects

Silicon-accurate nanometer RFIC process support: • Automated layout pre-processing like via array merging • Dummy metal fill and process scaling support • Boolean layer operation for native MIM capacitor support

Cadence Virtuoso integration: • Seamlessly integrated into the Cadence® Virtuoso® 5.1.41 and 6.1.x platforms • Automated stack-up file creation from Cadence technology files • 3D Viewer with embedded visualization of surface currents or radiated fields

provides insight on problem areas in layout • Broad-band Spice Model generation for efficient use in time-domain simulations

Going beyond 3D planar applications: • Fast, direct bond wire support • Through Silicon Via (TSV) modeling support • Virtuoso link to EMPro for full 3D EM simulations

Momentum support in TSMC PDKs

38

Momentum officially qualified for TSMC’s 90-, 65- and 40-nm processes:

• Momentum has passed TSMC extensive qualification tests against measurements up to 30 GHz for different configurations

• +20 inductors on average validated with different metal stacks for symmetric, un-symmetric and center-tapped inductors configurations

Corresponding stack-up files can be downloaded at TSMC online:

Additional Momentum Modules and ADS PDKs available: • +50 Momentum Modules are available for TSMC processes down to 28 nm • ~20 ADS front-end PDKs are available for TSMC processes • Full front-to-back ADS for TSMC Integrated Passive Device (IPD) process

For further details go to:

http://www.agilent.com/find/eesof-partners-tsmc

Sample results for 40 nm:

Momentum Qualification up to 110 GHz Passive building blocks (Transformers, Transmission lines)

Momentum Measurement

S11

S22

dB(S21)

phase(S21)

Cs Rs

Cg1+Cg2 Rg1//Rg2

39

Agilent EEsof 60-GHz RDK contributions

• Top-down ESL architecture verification • Verify at every level vs. consistent 802.11ad TX/RX references

• RFIC circuit simulation & verification • Full characterization of complete RF transceiver prior to tape-out

• EM analysis & verification • Enable EM analysis early and often through integrated solvers

• Add off-chip effects & components in overall verification • Addressing integration issues early in the design cycle

40

Performance w/ & w/o package

Accurately predict real performance

ADS – QFN Designer Predict Packaged Performance in Minutes

Quickly synthesize complex package, combine with IC & PCB data

Configure QFN package

41

Summary

• 60-GHz RDK Introduction • A silicon-proven MS/RF reference circuit and methodology packaged into a

complete RF reference design kit (RDK) • Provides RF top-down design and bottom-up verification methodologies

from system-level simulation through tape-out • Enables design collaboration with key ecosystem partners to meet

customer needs

• Complete RFIC design solutions with dedicated mm-Wave support • Scalable system-level solutions from algorithm development through RF

architecture exploration • Advanced RF design, analysis and simulation support • Silicon-accurate EM verification support • Broad modeling solutions across integration boundaries

• Visit us at DAC and IMS for a demo!

42

Dingqing LuTechnical Sr. Application Specialist, Agilent EEsof EDA

April 5, 2012 Copyright © 2012 Agilent Technologies

You are Invited:

You can find more webcasts www.agilent.com/find/eesof-innovations-in-eda www.agilent.com/find/eesof-webcasts-recorded

Daren McClearnon – ESL Product Planning Manager Agilent EEsof EDA