Computer Access

• Sun workstations may be accessed remotely

in the open computing lab (JD1622C) via p p g ( )

Hummingbird.

• Directions are available from computerDirections are available from computer

support (JD 1109 or 1112) and will be

available on the course web siteavailable on the course web site.

1

Turn ‘em OFF!

It seriously annoys your instructor not a Good Thing

2

It seriously annoys your instructor, not a Good Thing.

EDA : Electronic Design g

Automation

The process of using computer-based software systems to design very large-scale integrated (VLSI) circuits.(VLSI) circuits.

All modern integrated circuits are designed with lEDA tools.

This course uses Verilog for hardwareThis course uses Verilog for hardware description and the NC Verilog simulator from Cadence for simulation.

3

WHAT IS A HARDWARE DESCRIPTION

COMPUTER BASED LANGUAGE

WHAT IS A HARDWARE DESCRIPTION

LANGUAGE (HDL) ?

•COMPUTER-BASED LANGUAGE

•Syntactically similar to programming languages

•MODEL, REPRESENT, AND SIMULATE DIGITAL HARDWARE

•HARDWARE CONCURRENCY

•PARALLEL ACTIVITY FLOW

•SEMANTICS FOR SIGNAL VALUE AND TIME

•SPECIAL CONSTRUCTS AND SEMANTICS

EXAMPLES

HILO2, HARDWARE C, AHDL (U of A 1970), ISPS (CMU, 1971)

EXAMPLES

VERILOG

4

VERILOG,

VHDL (Very High Speed Integrated Circuit Hardware Description Langauge)

Current HDL Usage

• All current digital IC development is done

with either VHDL or Verilog.g

• Other scripting languages (perl, make,

Tk/tcl) may be used to supplement themTk/tcl) may be used to supplement them.

• All FPGA, ASIC and 3rd party tool vendors

(Synopsys Cadence Mentor Graphics etc )(Synopsys, Cadence, Mentor Graphics, etc.)

support both Verilog and VHDL.

5

Wh U HDL ?Why Use an HDL ?

• As the complexity of systems increases, it becomes more

diffi l d i di l h ddifficult to design directly on hardware.

• Exploring different design options is easier and cheaper p g g p p

because you only need to change the HDL description. It

is much easier to change the description than to

reconfigure the prototypereconfigure the prototype.

• You can try different design options quickly and easily. y g p q y y

The time to fix a design problem is reduced and so is the

cost.

6

Test Early and Often

7

Finding defects early is way cheaper than finding them after

they are out in the field. Image © Texas Instruments.

Transistor Density

• First microprocessor (circa 1971) had 2,300

transistors.

• It was done by a team of four in about four

monthsmonths.

• That’s less than 150 transistors per engineer

per monthper month.

8

Density Increase

• Current state of the art in processors is approaching a billion transistors.

• At 150 transistors per engineer per month, something like 6 million man-months.

• Design at the gate level: about 10 transistors/gate.

• A team of 100 could then get a processor done in a mere 5,000 years.

9

Area vs. Operating FrequencyArea vs. Operating Frequency

One HDL encoding can produce many designs through

logic synthesis.

10

Image © John Cooley “The Great ESDA Shootout”

http://www.eedesign.com/editorial/1996/coverstory9604.html

i

Design

Specification

HDL Design

Flow HDL CodingFlow

Simulation HDL

Vectors Simulation

NoSimulation

Passed?

Yes

assed?

11Logic

Synthesis

Popularity of Verilog HDL

• It is a general purpose hardware description language that• It is a general-purpose hardware description language that

is easy to learn and use.

• It is similar to the C programming language.p g g g g

• It allows for different levels of abstraction to be mixed in

the same model.

• Most popular logic synthesis tools support Verilog HDL.

• All fabrication vendors provide Verilog HDL libraries for

post logic synthesis simulationpost logic synthesis simulation.

• The Programming Language Interface (PLI) allows the

user to write custom C code to interact with the internal

12

data structures of Verilog.

Typical Design Flow

h b h i l d i i i ll d• The behavioral description is manually converted to a

Register Transfer Level (RTL) description in an HDL.

• Designer has to describe the data flow that implements the• Designer has to describe the data flow that implements the

desired digital circuit.

• Logic synthesis tools convert the RTL description to a

gate-level netlist ( a description of the circuit in terms of

gates and connections between them).

• The gate level netlist is input to an Automatic Place and• The gate-level netlist is input to an Automatic Place and

Route tool to create a layout.

• The layout is verified then fabricated on chip.

13

y p

Concept & Static Timing p

Market Researchg

Analysis

Design Specification Timing

OK?No

RTL Coding &

Simulation Floorplanning, CT

Yes

Logic Synthesis

p g,

Insertion,

Global P&R

Logic Synthesis

Static Timing

A l i

14Scan Insertion

Analysis

Go to P&R

Detailed RoutingP d?

Back to

Salt MinegPassed?

Yes

Salt Mine

Post-layout STA

Tapeout

Timing

OK? C ll

Back to

Salt Mine

OK? Collect Bonus,

VacationYes

Design Rule Check

15

Terms and DefinitionsTerms and Definitions

Hard ware description A programming language that can describe the

f i li d i i f h d i ilanguage (HDL)

Simulator

functionality and timing of hardware circuits.

Software which reads the HDL and emulates

h h d d ib d b h

Bottom-Up design flow

the hardware described by the HDL.

A design methodology in which you build the low-

level components first and then connect them to

Top-down design flow

p

make large systems.

A design methodology in which you define the

system at a very high level of abstraction and

refine it at the lower levels of abstraction by

partitioning the design into logical, functional, or

h i l it

16

physical units.

Key Features of HDL’sKey Features of HDL s

• Typically an HDL contains some high level programming language constructs

along with constructs to describe the connectivity of hardware design.along with constructs to describe the connectivity of hardware design.

• An HDL allows you to describe the design at various levels of abstraction using

structural or behavioral constructs.

• An HDL allows you to describe the functionality of hardware along with its

timing constraints.

• Concurrency is the ability to perform multiple tasks at the same time. Typically,

programming languages are not concurrent, but in hardware, a number of

operations happen at the same time. Thus, an HDL must be concurrent.p pp ,

• Typically, programming languages have no concept of time. In hardware there

are delays associated with going from an input to an output. An HDL allows you

t d l th d l b it h t f ti

17

to model these delays because it has a concept of time.

Simulation Algorithmsg• Time Driven

Each circuit element is evaluated at each time point producing a new circuit— Each circuit element is evaluated at each time point, producing a new circuit

state at that point.

— Inefficient, because at any time only 2 to 10 percent of elements in a circuit

need to be evaluated.

A

B

C

X

Y

A

W

18

— The change of the value of any of the variable will result in the calculation

of the logical value at all points

• Event driven

Simulation Algorithms

Event driven

— Changes in circuit state are recorded. Only those elements that might cause a

change in circuit state, during time, are simulated. The simulation propagates

values forward, through the circuit, in response to input pin events.

— Most practical and widely used simulation algorithm.

— Efficient, because it “evaluates when necessary.”C

A

B

X

Y

A

W

A th t t ti “t T” A 1 B 0 d C 1 N if t ti “t T+1” l

19

— Assume that at time “t = T”: A=1, B=0 and C = 1, Now if at time “t=T+1” only

A changed to “0” this will require the calculation of only the output of this gate.

Simulation Algorithms

• Demand driven

— Further refines “evaluates when necessary.”

— Evaluates nets and gates only when their values are needed to provide simulation

output.

— Propagates requests for simulation values, backwards through circuit and time.

B

C

A

X

Y

A

W

A th t t ti “t T” W 1 N if t ti “t T+1” W d t h

20

— Assume that at time “t = T”: W= 1. Now, if at time “t=T+1” W does not change

then the changed of any of the other variable will not require any calculation.

Simulation Algorithms

• Cycle-based

C ll ll l i b t i tCollapse all logic between registers.

Only calculated final values.

Intermediate timing and delay data are lost.

Fastest, but not suitable for all simulations.

21

Cycle Based AlgorithmCycle Based Algorithm

S31Q2

Q1S1 S2

S31Q

CLK

Q1Q1

S1

S2

S3

22Q2

Cycle Based Algorithm

S1 S2S3

Q1S1

S1 = Q1 & 1

S2 = S1 | 0Only calculate final value

at clock edge not all intermediate|

S3 = S2 ^ 0

! S3 = Q1

at clock edge, not all intermediate

values at the time at which they

transition. Timing may be verified

23

! S3 = Q1with a static timing analyzer.

Combined AlgorithmsCombined Algorithms

• Perfectly synchronous circuits may bePerfectly synchronous circuits may be effectively simulated with cycle-based simulation combined with STA.

• Real designs tend not to be totally synchronous (though ECE526 designs will y ( g gbe).

• Sophisticated simulators combine palgorithms: parts that are suitable for cycle-based use cycle-based, parts that are not use

d i24

event-driven.

Time Wheel in Event-Driven Simulation

• When the simulator compiles its data structures, it creates the initial queues (time=0) for the time wheel based on the HDLwheel based on the HDL.

• The simulation starts when the current simulation time is 0.time is 0.

• When all the events scheduled at time 0 are executed, the simulation time advances to the next time step.

• Events at each time step can append new events to t t l t ti

25

event queues at a later time.

Time Wheel in Event-Driven SimulationTime Wheel in Event-Driven SimulationEvent queues at each

time stamp t

t+1

t+2

t+3

ECurent Simulation Time

t+4An event at time t+2

schedules another

event at time t+4

• The time wheel can only go forward.y g

• Time advances only when every event scheduled at that time is executed.

26

Verilog Event QueuesVerilog Event Queues

27

http://csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf

Different Levels of Abstraction

• Architectural/AlgorithmicArchitectural/Algorithmic

• Register Transfer level (RTL)

• Gate

• Switch

28

Different Levels of AbstractionDifferent Levels of Abstraction• Architectural/Algorithmic

The system is described in the terms of the– The system is described in the terms of the

algorithms it performs.

The aim is to study the data flow of the system– The aim is to study the data flow of the system

and potential bottlenecks.

• Register Transfer Level (RTL)• Register Transfer Level (RTL)

– Describes the flow of data and control signals

within and between functional blockswithin and between functional blocks.

– Schedules assignments at clock edges.

29

Different Levels of Abstraction

– The Register Transfer Level, (RTL), is a design level of abstraction. RTL refers to coding that uses a subset of the HDL language.the HDL language.

– RTL is the level of abstraction below behavioral and b t t l E t d fi d i t f l kabove structural. Events are defined in terms of clocks

and certain behavioral constructs are not used.

– A RTL description implies that the data in the registers you are describing "transfers" in the manner specified by your clocks. RTL synthesis must preserve the

30

y y y ptransfer of data between registers as specified by your clocks.

Different Levels of Abstraction

• Gate

– Interconnection of logic elements (or gates) to check functionality, performance, or the timing of design.

S it h• Switch

– Describes logic behavior of transistor circuits.

E l t fli t d b bidi ti l– Evaluates conflicts caused by bidirectional pass transistors, signal strengths of multiple elements driving a net, and so on.

31

g ,

Design Methodologies

• Bottom-up design flow

– Start with small functionsStart with small functions

– Build up a hierarchy, eventually creating the

top level design.p g

• Top-down design flow

– Start with an overall design specification– Start with an overall design specification.

– Add detailed functions to make it work.

32

Verilog is Flexible

• There are many ways to code a Verilog

project.p j

• Standards have developed over the years.

Examples presented here frequently showExamples presented here frequently show

variations on what CAN be done and do not

always correspond to best industrialalways correspond to best industrial

practices.

33

Always Use Synchronous Design

Q0 Q1 Q3Q2

CLK

34

NEVER do anything like this!

Synchronous Count

CLK

Q0Q0

Q1

Q2

0 1 2 3 4 5 6

35

Ripple Clock Behavior

CLK

Q0Q0

Q1

Q2

0 1 2 3 4 5 60 02 4

36

Synchronous Designs

• Synchronous designs are more robust.

• Synchronous designs are testableSynchronous designs are testable.

• Synchronous designs are portable.

S h d i h b i• Synchronous designs have better noise

immunity.

• http://www.elecdesign.com/Articles/Index.c

fm?AD=1&ArticleID=7596

37

Th V il Si l tThe Verilog Simulator

• It is a logic level simulator that you can use to:• It is a logic-level simulator that you can use to:

-Determine feasibility of new design ideas.

Try out more than one approach to a design problem-Try out more than one approach to a design problem.

-Verify functionality.

-Identify design errors.y g

• Verilog started out as a verification tool. Hardware

design and synthesis came later.g y

• NC Verilog simulator now supports all Verilog

2001 enhancements.

38

Invoking the Simulator

• Starting in Fall 2007, all Verilog-based courses will use NC Verilog.

il fil– ncverilog filename.v

• The obsolete Cadence simulator Verilog XL is still running on the workstationsstill running on the workstations.

• It is invoked by– verilog finename.vg

• Make sure you always use NC Verilog and not Verilog XL

39

Designing with Primitives

• First labs use Verilog built-in primitives for

design.g

• This is not an improvement over schematic

capturecapture.

• While it is useful for learning the

functioning of tools it is NOT the wayfunctioning of tools, it is NOT the way

Verilog is used for circuit design.

40

Verilog Primitives

• Just like drawing schematics, circuits of any arbitrary size can be made with primitive components.components.

• Primitive logic operators are– AND

– OR

– XOR

– NOT

• And the inverses of these four– NAND, NOR, XNOR, BUF

41

Instantiating Primitives

nand (out, in1, in2, in3, in4);

nand: primitive type Verilog keywordnand: primitive type. Verilog keyword.

out: gate output is always the first port

i 1 il f biin1, etc.: Verilog supports gates of arbitrary

width. Gate instances do not need to correlate 1:1

to physical gates.p y g

If not otherwise declared, variables (in1, in2, etc.

default to single-bit wires.

42

Multi-bit wires

Not needed for Lab 1, but will be needed shortly.

wire andbus;

wire [1:0] bus;

and gate_1(andbus, bus[0], bus[1]);

//gate_1 is the NAME of one particular and gate. Gate

//names are optional but generally advisable.

43

Lab 1 Circuit Header

//Carefully note SYNTAX, especially on first line

`timescale 1 ns / 1 ns //first character is backtick, not apostrophe

module MUX2_1 (out, a, b, sel);

//Port declarations

output out;

input a b sel;input a, b, sel;

wire a, b, sel, sel_, out; //note sel_ is left out of manual

44

Lab 1 Netlist

//The netlist

not (sel_, sel);

and (a1, a, sel_);

and (b1, b, sel);

or (out, a1, b1);

endmodule

45

Warning

• Verilog IS case sensitive.

• All Verilog keywords are lower caseAll Verilog keywords are lower case.

46

Case Sensitivity

• Keywords are always lower case

– Wire A, B;//ILLEGALWire A, B;//ILLEGAL

– WIRE A, B;//ILLEGAL

– wire A a;//Legal but bad techniquewire A, a;//Legal but bad technique

– wire A, B;//The advised way

wire a b;//OK but may be confusing– wire a, b;//OK but may be confusing

47

Case Sensitivity

• Verilog is case sensitive

– reg [3:0] count;

– reg [15:0] COUNT;

– reg [31:0] Count;

• Logic synthesizer and other downstream tools are not.

• Above would simulate correctly, fail in synthesis.

48

Lab 1 Netlist

//The netlist

not (sel_, sel);

and (a1, a, sel_);

and (b1, b, sel);

or (out, a1, b1);

endmodule

49

Lab 1 Schematic

B

OUTSEL

A

50

How Would This Change theHow Would This Change the

Netlist?

B

OUTSEL

A

51

Modified Netlist

//The netlist

not (sel_, sel);

and (a1, a, sel_);

and (b1, b, sel);

and (ab, a, b);

or (out, a1, b1, ab);

endmodule

52

endmodule

Test Bench

• Lab 1, like all labs, has a Verilog circuit description and a Verilog test program.

• Circuit description may contain ONLY synthesizable constructs. Many Verilog constructs are not synthesizable.

• Test fixtures (test benches, same thing) are not so limited. All of Verilog is legal for test programs.

53

Managing Files

• It is generally good practice to

– Have exactly one UNIX file per VerilogHave exactly one UNIX file per Verilog

module.

– Have the Verilog module name be the same as g

the UNIX file name.

– Give the UNIX file a .v extension.

– Have one directory per lab.

54

Directory Organization

Design Root

Source Code Synthesis Simulation

55

Scripts Logs, Reports Netlists

Lab 1 Test Bench

i l /`timescale 1 ns / 1 ns

module test_mux;

reg a, b;

wire out;

reg sel;

MUX2 1 m1(out, a, b, sel);MUX2_1 m1(out, a, b, sel);

initial

$monitorb( “%d out %b a %b b %b sel %b”

56

$monitorb( “%d out=%b a=%b b=%b sel=%b”,

$time, out, a. b. sel);

Lab 1 Test Stimulus

i i i l b iinitial begin

#10 a=0; b=1; sel=0;

#20 sel=1;

#20 a=1; b=1;

#10 sel=0;

#20 $stop;#20 $stop;

#1 $finish;

end

57

end

endmodule

More Stimulus

• The stimulus shown is a start but is not complete.

• For this lab, ALL possible combinations must be tested.

• This means all logic values (000 ! 111)

• It also means all legal Verilog values.g g

• What are the other values an input can have?

58

Design Errors and Faults

• Lab manual does not entirely correspond to

industry-standard nomenclature (testing and y ( g

verification, pg. 12).

• Faults are manufacturing defects “FactoryFaults are manufacturing defects. Factory

test vectors” are written to enable them to

be detected once the design is suitablybe detected once the design is suitably

modified for test.

59

Verification

• In ECE 526, we are concerned with logic verification, NOT fault detection.

• These are two distinct procedures.

• You will write test fixtures to determine the logical functioning of your designs. You will not write test vectors to enable the foundry to sort out the good chips from the bad.

60

Lab Report

• Lab manual page 10 has an example of

good technique and bad technique.g q q

• Both have a 2:1 mux.

• Do they work identically? Answer this• Do they work identically? Answer this

question in your lab report.

61

Lab 1

• Tools change as time goes on.

• Not all commands/procedures in the labNot all commands/procedures in the lab

manual will work exactly as written.

• Lab printer generally won’t work Do not• Lab printer generally won t work. Do not

depend on it.

62

Bottom-Up Design Flow

REGISTER REGISTER

4 Design timing, performance,

And testability are analyzed

p g

ALU

STATE

PC

RAM3 The complete design is

modeled and tested

DFF DFF...

modeled and tested

2 Intermediate level components2 Intermediate level components

Are modeled at the gate level

And tested

DFF1 Lowest level components

are modeled at gate level

63

g

and tested

Bottom-Up Design FlowSince bottom-up design closely follows the steps involved in breadboarding and building a system using hardware onlybreadboarding and building a system using hardware only, bottom-up design is the traditional method.

•The advantages of bottom-up design are:– Many designers already have the software and hardware required to

design this way.

– Designers are traditionally trained to work this way.

– Less time is needed to implement individual pieces of the circuit.

•The disadvantages of bottom-up design are:– Typically, there is a poor functional view of the entire system.yp y p y

– You need more time to implement the entire system, because you must complete individual pieces first. In other words, concurrent engineering is more difficult with bottom-up design methods.

64

Top Down Design FlowTop-Down Design Flow1. The top-level system is modeled

for functionality and performance CPUInputs Outputs

for functionality and performance

using a high-level behavioral

description.

h j i d l d

CPU

2. Each major component is modeled

at the behavioral level and the

design is simulated again for

functionality and performance

Registers Registers

ALU PC

Counter RAMfunctionality and performance.

3. Each major component is modeled at

the gate level and the design is

simulated again for timing,

functionality and performance.

Registers Registers

ALU PC

Counter RAM

G i l i

65

Gate implementation

Top-Down Design FlowTop-Down Design Flow• Top-down design begins with a Verilog functional model of

the top level system As the individual partitions are modeledthe top-level system. As the individual partitions are modeled

in more details, they are plugged back into this top-level

function description.

• The advantages of top-down design are:

– System analysis is done at the beginning of the design cycle.

Therefore, quality and performance trade-off decisions can be made atTherefore, quality and performance trade off decisions can be made at

the earliest stage.

– Concurrent engineering is facilitated. In other word, a number of

engineers can work on different parts of the design at the same time.engineers can work on different parts of the design at the same time.

– Typically, fewer design iterations are required; so time to market is

reduced.

Increasingly large designs are easier to handle

66

– Increasingly large designs are easier to handle.

Top-Down Design Flow

• The disadvantages of top-down design are:

– There is a learning curve involved, because it isThere is a learning curve involved, because it is

not as traditional as bottom-up design.

– It requires software and hardware capable of q p

performing mixed-level simulations.

67

Verilog HDL and NC Verilog• Verilog HDLVerilog HDL

- Hardware description language that allows you to describe circuits at different levels of abstraction and to mix any level of abstraction in the design.

- Verilog can be applied to all aspects of electronic design, including testing and verification. Therefore, only one g g , ylanguage needs to be learned.

NC V il S ft• NC Verilog Software

High speed simulator that reads Verilog HDL and simulates

the description to emulate the behavior of real hardware

68

the description to emulate the behavior of real hardware.

Key Language FeaturesVerilog Module

• Modules are the basic building blocks in the hierarchy.

• Verilog descriptions or models are placed inside• Verilog descriptions or models are placed inside modules.

• Modules may represent:

-A physical block like an IC or ASIC cell.

-A logical block like the ALU portion of a CPU design.

-Smaller design components-Smaller design components.

-The complete system.

69

Verilog Module

module SN74LS74 module DFF module ALU

endmodule endmodule endmodule

70

Module Ports

• Module ports are equivalent to the pins in hardware.

• Modules communicate with the outside world through ports.

Y li t d l ' t i th ft th• You list a module's ports in parentheses after the module name.

• You declare ports to be input output or inout• You declare ports to be input, output or inout(bidirectional) in the module description.

71

Module Ports

module DFF (D, CLK, PRE, CLR,

Q, QB);

input D, CLK, PRE, CLR;

CLR

output Q, QB;

DFF

CLK

D

Q

D QB

endmodule

PRE

72

endmodule

Things to NoteThings to Note

• Verilog keywords (module endmodule• Verilog keywords (module, endmodule, input, output) are all lower case.

• There is no defined order for ports• There is no defined order for ports.

• Input and output statement order does not need to correspond to port orderneed to correspond to port order.

• Ports declared together must be all the same type: all single bit in the exampletype: all single bit in the example.

• Continuation character not needed (module declaration line)

73

declaration line).

Modifying a Module

How would the previous module change for

a JK flipflop?p p

74

JK Flipflop Ports

module JKFF(J, K, CLK, PRE, CLR, Q, QB);

input J, K, CLK, PRE, CLR;input J, K, CLK, PRE, CLR;

output Q, QB;

….

….

….

endmodule

75

Module Instances• You can create a larger system or component by listing instances of

other modules and connecting those instances by their ports.

• In the following example, REG4 contains four instances of the module g p ,

DFF. Note that each module has its own instance name (d0, d1, d2 and

d3). The instance name gives a unique name to every object, and is

used so that the internals of the instance can be examined.

• Notice that the order of the ports in the instance follows the order in the

module definition.

• Instantiating a module is not the same as calling a routine; each instance

is a complete independent and concurrently active copy of the module

76

is a complete, independent, and concurrently active copy of the module.

Module Instancesmodule REG4(d,clk,clr,q,qb);REG4 qqb ( q q )

output [3:0] q, qb;

input [3:0] d;

input clk, clr;DFF

d0

DFF

d1

DFF

d2

DFF

d3

REG4 qqb

DFF d0(d[0], clk, clr, q[0], qb[0]);

DFF dl(d[l], clk, clr, q[l], qb[1]);

DFF d2(d[2] lk l [2] b[2])

d0d1d2d3

dclk clr DFF d2(d[2], clk, clr, q[2], qb[2]);

DFF d3(d[3], clk, clr, q[3], qb[3]);

endmodule

DFF

clk clr

endmodule

Design Name Instance Namemodule DFF(d, clk,

clr, q, qb);

77

…

endmodule

Simpler DFF

D Q module DFFS(CLK, D, Q);

DFFS

Q

input CLK, D;

output Q;

CLKoutput Q;

…..

…..

endmoduleRegisters used in data flow

paths rarely include RST or

78

paths rarely include RST or

QB ports.

Hooking Up Instances

D I D t O tDFFSDFFS

Clock

Data In Data OutDFFS DFFS

79

Shift Register

module shift4(Clock, Data_In, Data_Out);

input Clock, Data_In;

output Data_Out;

wire Delay1, Delay2, Delay3;

DFF D0 (Clock, Data_In, Delay1);

DFF D1 (Clock, Delay1, Delay2);

DFF D2 (Clock, Delay2, Delay3);

DFF D3 (Cl k D l 3 D t O t)

80

DFF D3 (Clock, Delay3, Data_Out);

endmodule

VerifyVerifymodule tb_shift4;

lk d ireg clk, data_in;

wire data_out;

shift4 uut(clk data in data out);shift4 uut(clk, data_in, data_out);

initial clk = 1’b0;

always #10 clk = ~clk;always #10 clk clk;

initial begin

#5 data in = 1’b1;_ ;

forever #20 data_in = ~data_in;

end

81

endmodule

Basic Verilog Constructs

• White space (blank, tab, new line) is

ignored.g

• Comments follow “C” conventions:

/*Multi line comments can be done with star– / Multi line comments can be done with star-

slash.*/

– //Single line comments are double slashes//Single line comments are double slashes.

– /*This does not work./*Why would you want to

do it,*/ anyhow?*/

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do it, / anyhow? /

System Tasks for Simulation

• $display

• $write$write

• $monitor

$ b• $strobe

• $time

• $stop

• $finish

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$finish

$display

• Displays the value of signals or variables in

a design or test fixture.g

• Usage: $display(s1, s2, s3,….sn);

• s1 s2 etc are signals in the uut or variables• s1, s2, etc. are signals in the uut or variables

in a test fixture.

U i f i i il C• Uses string formatting similar to C.

• Includes new line character by default.

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$display string formatting

• %d display a variable in decimal

• %b display a variable in binary%b display a variable in binary

• %s display a string

% di l ASCII h• %c display an ASCII character

• %h display a variable in hex

• %g display a real number in scientific

notation or decimal, whichever is shorter.

85

,

$display Examples

• $display(“I want a cookie.”);– I want a cookie.

• $display(“Count = %d”, count);– Count = 6

• $display(“Count %b” count);• $display(“Count = %b”, count);– Count = 0110

• $display($time “ count = %b state = %h” count$display($time, count %b, state %h , count, state);– 80 count = 0110, state = fa

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$time

• $time calls out the simulation time.

• It has nothing to do with the time of day.g y

• Internally, it is represented by a 64-bit number, so

it can keep track of a long simulation.

• Example: $display($time);

– 80

• 80 time units have passed since the simulation

started.

87

$write

• $write is exactly the same as $display except that it does not implicitly include a new line character.

• Example:

– $write(“I want a cookie. ”);

– $write(“I want a cookie! \n”);

• Output:

– I want a cookie. I want a cookie!

88

$monitor

• Monitors a signal when its value changes.

• Usage: $monitor(p1 p2 p3 pn);Usage: $monitor(p1,p2,p3…pn);

• p1, p2, etc. are signals in the uut or

variables in a test fixturevariables in a test fixture.

• $monitor displays the values of all objects

i i li h f hin its list whenever any one of them

changes.

89

Using $monitor

• Same formatting as $display

• Only ONE $monitor can be active at a timeOnly ONE $monitor can be active at a time.

Thus

$monitor(“clock = %b reset = %b” clk rst);– $monitor( clock = %b reset = %b , clk, rst);

– $monitor(“state = %h”, state);

ill lt i l “ t t ” b i it d• will result in only “state” being monitored.

90

Difference Between $monitor andDifference Between $monitor and

$display

• $monitor is continuous.

• $display only runs once$display only runs once.

• Possible usage: display header, monitor

changing data:changing data:

– $display(“time\tstate\tcount”);

$ i (“$ i %h \ %h” )– $monitor(“$time,%h \t%h”, state, count);

91

$strobe

• Very similar to $display.

• The difference is that $strobe is always theThe difference is that $strobe is always the

last task to be executed at any time

specification whereas $display may not bespecification whereas $display may not be.

92

$strobe and $display Example$strobe and $display Example

always @(posedge clk) begin

a = b;

d They COULDc = d;

end

They COULD,

but probably

won’t, give

always @(posedge clk) begin

$display(“a = %b c = %b” a c);

, g

different results.

$display( a = %b, c = %b , a, c);

$strobe(“a = %b, c = %b”, a, c);

93end

Scope of Variables

• All system task examples so far have not

had any scope operator.y p p

• They would all operate on variables in the

test fixturetest fixture.

• Internal variables can also be displayed,

monitored etc by scoping down to wheremonitored, etc. by scoping down to where

they are.

94

Monitoring an Internal Variable

• Change scope by stringing together hierarchical names with periods.

• Example: UUT is instance of design DESNAME

– DESNAME UUT(CLK, X, Y, Z);

– $display (“a = %b, X = %b”, UUT.a, X);

• The value of the variable “a” that is in the uut will be shown, as will the variable X in h fi

95

the test fixture.

Looking Inside the UUT

Monitor this pointA

C

Monitor this point

OUTSEL D E

BF

96

$monitor(“AND1 Output = %b”, UUT.C);

Unlimited Scoping

• Big designs can have many levels of

hierarchy.y

• Each instance of a sub design will have an

instance nameinstance name.

• So you can monitor signals at any level of

hierarchy by using the scoping operator andhierarchy by using the scoping operator and

hierarchical names.

$ it (TOP CONTROLLER SM STATE)$monitor(TOP.CONTROLLER.SM.STATE);97

$stop and $finish

• $stop halts simulation and puts the

simulator into interactive mode. Resume

simulation by typing “.” at the prompt.

• $finish ends the simulation$finish ends the simulation.

98

When to use $stop and $finish

• $stop is used to get into interactive mode.

• This makes it good for debugging in the lab.g gg g

• $finish ends the session.

• Larger projects are typically simulated inLarger projects are typically simulated in “Batch Mode.” Then they need to be terminated with a $finish. Leaving $stop in g pthe test bench would not allow the simulator process to terminate.

99

Verilog Primitives

• Verilog provides basic logical functions as predefined• Verilog provides basic logical functions as predefined primitives. You do not have to define this basic functionality.y

• Most ASIC libraries are developed using primitives.

• They form an integral part of the bottom-up design methodology but are not used in behavioral code.

• Verilog simulates the predefined primitives with built in algorithmsbuilt-in algorithms.

• Behavioral simulation is far faster than gate-level simulation.

100

simulation.

Verilog Primitives

Primitive Name Functionality

d L i l ANDand Logical AND

or Logical OR

not Inverter

buf Buffer

xor Logical Exclusive OR

d i l A dnand Logical AND Inverted

nor Logical OR Inverted

xnor Logical Exclusive OR Inverted

101

xnor Logical Exclusive OR Inverted

Primitive Pins Are Expandable• The number of pins for a primitive gate is defined p p g

by the number of nets connected to it. Therefore, you do not need to redefine a new logical function

hene er the n mber of inp ts or o tp ts to thatwhenever the number of inputs or outputs to that function change.

• All gates except not and buf can have a variable number of inputs, but only one output.

• The not and buf gates can have a variable number

102

of outputs, but only one input.

Verilog Primitives

nand (out, in1, in2);outin1

in2

nand (out, in1, in2, in3);out

in2

in1in2 ( , , , );

nand (out in1 in2 in3 in4);out

in3

in1in2in3 nand (out, in1, in2, in3, in4);outin3in4

103

Multiple-input Primitives

Input 2

• AND

• OR 0 1 X ZInput 1

• XOR

• NOR0 0 1 X X

• XNOR 1 1 1 1 1

X X 1 X X

Z X 1 X X104

Z X 1 X X

More Primitives

Input 2

• AND

• ORAND 0 1 X ZInput 1

• XOR

• NOR0 0 0 0 0

• XNOR 1 0 1 X X

X 0 X X X

Z 0 X X X

Note that gates are NOT

limited to two inputs.

105

Z 0 X X Xlimited to two inputs.

Another Multiple-input Primitive

Input 2

• AND

• ORXOR 0 1 X ZInput 1

• XOR

• NOR0 0 1 X X

• XNOR 1 1 0 X X

X X X X X

Z X X X X

Any XOR/XNOR will

output an X (unknown) if

i t i k Hi

106

Z X X X Xany input is unknown or Hi

Z.

Single-input Primitives

• Buf In Out

0 1

1 0• Not

1 0

X X

Z X

107

Primitives with Control Inputs

• Bufif1

• Bufif0In Out

Bufif0

• Notif1

N if0 Ct l• Notif0 Ctrl

Output is Z (high impedance) if control is notOutput is Z (high impedance) if control is not

asserted.

O i X if l IS d d i i108

Output is X if control IS asserted and input is

X or Z.

Netlists of Primitives

and #gate delay ANDGATE1 (out in1 in2 in3);and #gate_delay ANDGATE1 (out, in1, in2, in3);

Gate

Type

Lumped

Intrinsic

Gate

Name

Port list, output

always firstType Intrinsic

and

Fanout

Delay

109

Delay

Time Delays

• Gates can have an associated delay– and #gate_delay ANDGATE1 (out, in1, in2, in3);

• The simulator can be instructed to wait before executing a line of code

#10 in1 <= 1’b1;– #10 in1 <= 1 b1;

• Note the syntactical difference. In the first case, there is a delay associated with the gate instance. y gIn the second, the simulator is instructed to wait before proceeding.

110

Time Delays

• Time delays are specified using #n, where n

is the amount of time in units as specified in p

a timescale directive. This will default to

nanoseconds.

• Example: #10 rst <= 1’b1;

• Wait for 10 ns then set signal rst to logic 1• Wait for 10 ns, then set signal rst to logic 1.

111

Setting bits

• Lab manual is sloppy on this syntax. Don’t

be that way in your code.y y

• Proper syntax includes the number of bits

and the radixand the radix.

• Example: rst <= 1’b0;

i i d bi l f l i 0• rst is assigned a one-bit value of logic 0.

112

More on Setting Bits

• As shown in the lab manual, bit variables can be set to logic 0 or logic 1 without proper formatting:

– Example: control = 0;

• This is poor practice and DOES NOT WORK with x and z values.

• The right way:

– control = 1’b0;

113

– tribit = 1’bz;

Assignment Operators

• Both = and <= have been used in these

examples.p

• They are not identical in function. The

difference will be covered laterdifference will be covered later.

• Rule of thumb: use = with combinational

code <= with sequentialcode, <= with sequential.

– Sequential is code that infers flopflops.

114

What’s This?

115