science

Computer Architecture Lecture 1Give qualifications of instructors:

DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC and RAIDMember of NAEReview of CS 161What is a von-Neumann computer? => The Stored Program Concept Sequential Execution of a program instructions in binary for storing in memoryDesign of an Instruction Set - RISC Vs. CISC, ExamplesDesign of CPU DatapathCPU Control Design (Hardwire vs. Microprogramming)Memory Design (Main memory, Cache Memory, Virtual memory)Input-OutputMIPS ISA1. all MIPS instructions are same lengthsimplifies fetch and decode (steps 1,2)Intel 80x86 and IBM 360/370 instructions are variable length, 1-17 bytes2. few instruction formats in MIPSsource register fields are same place in all instructionscan read two registers and decode instruction in the same cycleExplicit Load/Store instructions for memory-register operations Review of CPU Datapath DesignInstruction operation consists of 5 parts, namely, Fetch (IF), Decode (ID), Execute (EX), Memory (DM), and Write-back (WB) stagesSingle Cycle Design Big Cycle CPI = 1 Problems: (1) Low frequency meaning less number of instructions executed per cycle (2) All instns take same one big cycle Multicycle Design Small Cycle CPI < 5 Break the datapath to several stages, each taking one cycle. Frequency is increased and some instns can finish earlier. Problems: Need extra registers to separate the stages and control must ensure that right control signals must be applied to right stage at the right time => complex control design, but still manageable in hardware.

Review: Datapath for MIPSDataMemory(Dmem)PCRegistersALUInstructionMemory(Imem)Stage 1Stage 2Stage 3 Stage 4Stage 5IFtchDcdExecMemWBUse datapath figure to represent stagesALU IMReg DMRegPipelined Execution IPC= 1To simplify pipeline, every instruction takes same number of steps, called stagesOne clock cycle per stageIFtchDcdExecMemWBIFtchDcdExecMemWBIFtchDcdExecMemWBIFtchDcdExecMemWBIFtchDcdExecMemWBProgram FlowTimeALU IMReg DMReg IMGraphical Pipeline RepresentationInstr.

OrderTime (clock cycles)LoadAddStoreSubOrALU IMReg DMRegALU IMReg DMRegALUReg DMRegALU IMReg DMReg(right half highlighted means read, left half write)Example: Single-cycle vs. PipelinedALU IMReg DMRegALU IMReg DMRegALU IMReg DMRegALU IMReg DMReg2 4 6 8 10 12 14 16 18 20 timeALU IMReg DMRegALU IMReg1

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3Advanced Architectural ConceptsCan we achieve CPI < 1? (i.e., can we have IPC > 1?) State-of-the-Art MicroprocessorSuperscalar execution or Instruction Level Parallelism (ILP)Deeper Pipeline => Dynamic Branch Prediction => Speculation => Recovery Out-of-order Execution => Instruction Window and Prefetch => Reorder BuffersVLIW Ex: Intel/HP Titanium

Instruction Level Parallelism (ILP) IPC > 1IFtchDcdExecMemWBMemDcdExecMemWBIFtchDcdExecMemWBIFtchDcdExecMemWBIFtchDcdExecMemWBProgram Flow ILP = 2TimeIFtchDcdExecWBIFetchEX: Pentium, SPARC, MIPS 10000, IBM Power PCVery Large Instruction Word (VLIW) IPC > 1IFtchDcdExecMemWBExecIFtchDcdExecMemWBExecIFtchDcdExecMemWBProgram Flow EX: ItaniumTimeExec