computer architecture: a constructive approach sequential circuits arvind
DESCRIPTION
Computer Architecture: A Constructive Approach Sequential Circuits Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology. OpSelect - Add, Sub, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero,. Sel. Sel. lg(n). lg(n). O 0 O 1 O n-1. - PowerPoint PPT PresentationTRANSCRIPT
Computer Architecture: A Constructive Approach
Sequential Circuits
ArvindComputer Science & Artificial Intelligence Lab.Massachusetts Institute of Technology
January 9, 2012 http://csg.csail.mit.edu/SNU L2-1
Combinational circuits
OpSelect - Add, Sub, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero, ...
Result
Comp?
A
B
ALU
Sel
OA0
A1
An-1
Mux...
lg(n)Sel
O0
O1
On-1
A
Dem
ux ...
lg(n)
A
Deco
der
...
O0
O1
On-1
lg(n)
Such circuits have no cycles (feedback) or state
A simple synchronous state element
ff QD
C
C
D
Q
Metastability
Data is sampled at the rising edge of the clock
Edge-Triggered Flip-flop
Flip-flops with Write Enables
ff QD
C
EN
C
D
Q
EN
ff QDC
EN
01
ff QD
CEN
dangerous!
Data is captured only if EN is on
Registers
Register: A group of flip-flops with a common clock and enable
Register file: A group of registers with a common clock, input and output port(s)
ff
D
ff
D
ff
D
ff
D
ff
D
ff
D
ff
D
ff
QQQQQQQQ
D
C
En
Register Files
ReadData1ReadSel1
ReadSel2
WriteSel
Register file
2R + 1W
ReadData2
WriteData
WEClock
No timing issues in reading a selected register
register 1
WSel C
register 0
WData
WE RSel2
RData2
RSel1
RData1
Register Files and Ports
Ports were expensive multiplex a port for read & write
ReadData1ReadSel1
ReadSel2
WriteSel
Register file
2R + 1W
ReadData2
WriteData
WE
ReadDataReadSel
R/WSel Register file
1R + 1R/W
R/WData
WE
We can build useful and compact circuits using registers
Example: Multiplication by repeated addition
January 9, 2012 L2-8http://csg.csail.mit.edu/SNU
Multiplication by repeated addition
January 9, 2012 L2-9http://csg.csail.mit.edu/SNU
1101 (13)1011 (11)1101
+ 1101 + 0000 + 1101 10001111 (143)
b Multiplicanda Muliplier *
add4
add4
add4
a0
a1
a2
a3
m0
m1
m2
m3
0
mi = (a[i]==0)? 0 : b;
Combinational 32-bit multiplyfunction Bit#(64) mul32(Bit#(32) a, Bit#(32) b);
Bit#(32) prod = 0; Bit#(32) tp = 0;
for(Integer i = 0; i < 32; i = i+1) begin Bit#(32) m = (a[i]==0)? 0 : b; Bit#(33) sum = add32(m,tp,0); prod[i] = sum[0]; tp = truncateLSB(sum); end return {tp,prod};endfunction
January 9, 2012 L2-10http://csg.csail.mit.edu/SNU
Combinational n-bit multiplyfunction Bit#(w+w) mulN(Bit#(w) a, Bit#(w) b);
Bit#(w) prod = 0; Bit#(w) tp = 0;
for(Integer i = 0; i < w; i = i+1) begin Bit#(w) m = (a[i]==0)? 0 : b; Bit#(w+1) sum = addN(m,tp,0); prod[i] = sum[0]; tp = truncateLSB(sum); end return {tp,prod};endfunction
January 9, 2012 L2-11http://csg.csail.mit.edu/SNU
What is wrong with this code?
Combinational n-bit multiplyfunction Bit#(Tadd#(w,w)) mulN(Bit#(w) a, Bit#(w) b);
Bit#(w) prod = 0; Bit#(w) tp = 0;
for(Integer i = 0; i < valueOf(w); i = i+1) begin Bit#(w) m = (a[i]==0)? 0 : b; Bit#(Tadd#(w,1)) sum = addN(m,tp,0); prod[i] = sum[0]; tp = truncateLSB(sum); end return {tp,prod};endfunction
January 9, 2012 L2-12http://csg.csail.mit.edu/SNU
Design issues with combinational multiply
Lot of hardware 32-bit multiply uses 31 addN circuits
Long chains of gates 32-bit ripple carry adder has a 31 long chain
of gates 32-bit multiply has 31 ripple carry adders in
sequence!
January 9, 2012 L2-13http://csg.csail.mit.edu/SNU
The speed of a combinational circuit is determined by its longest input-to-output path
Sequential Multiply
January 9, 2012 L2-14http://csg.csail.mit.edu/SNU
mul_en
ba
result (low)
y
x prod
<<
add0
&
tp
<<
result (high)
== 32
i
0
done
Sequential multiply Reg#(Bit#(32)) a <- mkRegU(); Reg#(Bit#(32)) b <- mkRegU();
Reg#(Bit#(32)) prod <-mkRegU();Reg#(Bit#(32)) tp <- mkRegU();Reg#(Bit#(6)) i <- mkReg(32);
rule mulStep if (i < 32); Bit#(32) m = (a[i]==0)? 0 : b; Bit#(33) sum = add32(m,tp,0); prod[i] <= sum[0]; tp <= truncateLSB(sum); i <= i+1; endrule
January 9, 2012 L2-15http://csg.csail.mit.edu/SNU
state elements
a rule to describe dynamic behavior
rdyenabInt#(32)
Int#(64)
rdy
start
resu
lt Mult
iply
module
Int#(32)
implicit conditions
interface Multiply; method Action start (Int#(32) a, Int#(32) b); method Int#(64) result();endinterface
A Multiply Modulet
#(Numeric type t)
t
t
t tTadd#(t,t)
t could beInt#(32),Int#(13), ...
The module can easily be made polymorphic
Many different implementations can provide the same interface: module mkMultiply (Multiply)
February 7, 2011 http://csg.csail.mit.edu/6.375 L02-16
Multiply Modulemodule mkMultiply32 (Multiply32); … Reg#(Bit#(32)) prod <-mkRegU();
Reg#(Bit#(32)) tp <- mkRegU();
rule mulStep if (i < 32); … prod[i]<= sum[0]; tp<= truncateLSB(sum); endrule
method Action start(Bit#(32) aIn, Bit#(32) bIn) if (i == 32);
a <= aIn; b <= bIn; tp <= 0; prod <= 0; i <= 0; endmethod
method Bit#(64) result() if (i == 32); return {tp,prod}; endmethodendmoduleJanuary 9, 2012 L2-17http://csg.csail.mit.edu/SNU
Internalbehavior
Externalinterface
State
Sequential 32-bit multiplymodule mkMultiply32 (Multiply32); Reg#(Bit#(32)) a <- mkRegU(); Reg#(Bit#(32)) b <- mkRegU();
Reg#(Bit#(32)) prod <-mkRegU();Reg#(Bit#(32)) tp <- mkRegU();Reg#(Bit#(6)) i <- mkReg(32);
rule mulStep if (i < 32); Bit#(32) m = (a[i]==0)? 0 : b; Bit#(33) sum = add32(m,tp,0); prod[i] <= sum[0]; tp <= truncateLSB(sum); i <= i+1; endrule method Action start(Bit#(32) aIn, Bit#(32) bIn) if (i == 32); a <= aIn; b <= bIn; tp <= 0; prod <= 0; i <= 0; endmethod method Bit#(64) result() if (i == 32); return {tp,prod}; endmethodendmoduleJanuary 9, 2012 L2-18http://csg.csail.mit.edu/SNU
Sequential n-bit multiplymodule mkMultiplyN (MultiplyN); Reg#(Bit#(w)) a <- mkRegU(); Reg#(Bit#(w)) b <- mkRegU();
Reg#(Bit#(w)) prod <-mkRegU();Reg#(Bit#(w)) tp <- mkRegU();Reg#(Bit#(Add#(Tlog(w),1)) i <- mkReg(w);
rule mulStep if (i < valueOf(w)); Bit#(w) m = (a[i]==0)? 0 : b; Bit#(Tadd#(w,1)) sum = addN(m,tp,0); prod[i] <= sum[0]; tp <= truncateLSB(sum); i <= i+1; endrule method Action start(Bit#(w) aIn, Bit#(w) bIn) if (i == valueOf(w)); a <= aIn; b <= bIn; tp <= 0; prod <= 0; i <= 0; endmethod method Bit#(Tadd#(w,w)) result() if (i == valueOf(w)); return {tp,prod}; endmethodendmoduleJanuary 9, 2012 L2-19http://csg.csail.mit.edu/SNU
Module: Method Interface
x_en y_enx y
> !(=0)
swap? subtract?
sub
xy
enrdy
xrdy
start
resu
ltstart_en start_en
February 7, 2011 http://csg.csail.mit.edu/6.375 L02-20
Not complete(taken from the GCD example)
Sequential Multiply Module
January 9, 2012 L2-21http://csg.csail.mit.edu/SNU
start_enba
result (low)
y
x prod
<<
add0
&
tp
<<
result (high)
!= 32
i
0
result_rdy
start_rdy
-1
Not complete
00
0
Pipelined Barrel Shifter
By inserting a register we can shorten the combinational critical path
January 9, 2012 L1-22http://csg.csail.mit.edu/SNU
00
0
Lab exercise 2