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Computer Architecture and

Organization: L06: Instruction Cycle

By: A. H. Abdul Hafez

[email protected], [email protected]

November 4, 2016 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

Outlines

November 4, 2016 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU 2

1. Fetch and decode

2. Determine the Type of Instruction

3. Instruction set in details

4. End

Instruction Cycle


A program residing in the memory unit of the computer

consists of a sequence of instructions.

The program is executed in the computer by going

through a cycle for each instruction.

Each instruction cycle in turn is subdivided into a

sequence of subcycles or phases: 1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if indirect

4. Execute the instruction

Fetch and Decode


Initially PC is loaded with the address of the first instruction in the program

SC is cleared to 0, providing T0 timing signal.

The microoperations for the fetch and decode phases are:

T0 : AR PC

T1 : IR M[AR], PC PC +1

T2 : D0, ...,D7 decode IR(12-14), ARIR(0-11), IIR(15) Since only AR is connected to the address inputs of memory, it is necessary to

transfer the address from PC to AR during the clock transition associated with T0.

The instruction read from memory is then placed in the IR with the clock transition of T1

At the same time PC is incremented by one to prepare it for the address of the next instruction of the program. At T2, the Opcode in IR is decoded, I bit is transferred to Flip Flop I, and IR part (0-11) is transferred into AR.

Fetch and Decode T0 : AR PC


To provide the data path for the transfer of PC to AR, we must

apply timing signal T0 to achieve the following connection:

1. Place the content of PC onto the bus by making the bus selection inputs

S2S1S0 equal to 010

2. Transfer the content of the bus to AR by enabling the LD input of AR

The next clock transition initiates the transfer from PC to AR since

T0=1. (See Mano figure 5.8)

Fetch and Decode T1 : IR M[AR], PC PC +1


For the second statemet, it is necessary to use timing

signal T1 to provide the following conditions in the bus

system Enable the read input of memory

Place the content of memory onto the bus by making S2S1S0= 111

Transfer the content of the bus to IR by enabling the LD input of IR

Increment PC by enabling the INR input of PC

The next clock transition initiates the read and increment

operations since T2=1 (See Mano Fig 5.8)

7

Memory Unit

AR

PC

IR

BUS

S2

S1

S0

T1

T0

7

1

2

3

Address

Clock LD

LD

INR

Read

Common Bus

T0: AR←PC

T1: IR←M[AR], PC←PC+1

Sequence Counter

Decoder

T0 T1 ………… T15

Clock

0

1

1 0 0 ……………0 0 1 0 ……………0

0 0 0 0 0 0 0 1

1

0

0

1

0

1

1

1

1

1

1

1

0 0 1 0

0 0 1 ……………0

0

0

T2: D7….D0←Decode IR(12-14), AR←IR(0-11), IIR(15)

Determine the Type of Instruction


The timing signal that is active after decoding is T3.

During time T3, the control unit determines the type of instruction

that was just read from memory.

See flowchart (at Mano Fig. 5.9) next slide.

9

Instruction Types

The basic computer has three instruction code formats :

opcode address

15 14 12 11 0

I (a) Memory reference instruction format

(Opcode = 000 through 110)

1 1 1 Register operation

15 14 12 11 0

0 (b) Register reference instruction format

(Opcode = 111)

1 1 1 I/O operation

15 14 12 11 0

1 (c) Input-output instruction format

(Opcode = 111)

10

Start

SC 0

AR PC

IR M[AR], PC PC+1

Decode operation code in IR (12-14)

AR IR(0-11), I IR(15)

D7

I I

AR M[AR] Nothing Execute

Register-refernce

Instruction

SC 0

Execute

input-output

Instruction

SC 0 Execute

Memory-reference Instruction

SC 0

T0

T1

T2

=0 (Memory-reference) (Register or I/O) =1

( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct )

T3 T3 T3 T3

Flowchart for instruction cycle (initial configuration)

D7 I T3 D7 I T3 D7 I T3 D7 I T3

11

Register-Reference Instructions

Register ref instructions are identified when D7=1 and I=0

Execution is started with timing signal T3 and takes one clock cycle.

Register ref instruction is specified by bits (0-11) of IR which also transfer to AR during

time T2. D7 I T3 = r (common for all register-refernce instructions)

IR( I ) = Bi [bit in IR (0-11) that specifies the operation]

r: SC ← 0 Clear SC

CLA rB11: AC ← 0 Clear AC

CLE rB10: E ← 0 Clear E

CMA rB9: AC ← AC Complement AC

CME rB8: E ← E Complement E

CIR rB7: AC ← shr AC, AC(15) ← E, E← AC (0) Circulate right

CIL rB6: AC ← shl AC, AC(0) ← E, E← AC (15) Circulate left

INC rB5: AC ← AC+1 Increment AC

SPA rB4: If (AC (15)=0) then (PC← PC+1) Skip if positive

SNA rB3: If (AC (15)=1) then (PC← PC+1) Skip if negative

SZA rB2: If (AC =0) then (PC← PC+1) Skip if AC zero

SZE rB1: If (E=0) then (PC← PC+1) Skip if E zero

HLT rB0: S← 0 (S is a start-stop flip-flop) Halt computer

HLT instruction clears a start-

stop flip-flop S and stops the

SC from counting. To restore

the operation of the computer,

the start-stop flip-flop must be

set manually.

12

Start

SC 0

AR PC

IR M[AR], PC PC+1


AR IR(0-11), I IR(15)

D7

I I


Register-refernce

Instruction

SC 0

Execute

input-output

Instruction

SC 0 Execute


SC 0

T0

T1

T2



T3 T3 T3 T3


D7 I T3 D7 I T3 D7 I T3 D7 I T3

Memory-Reference Instructions


Memory ref instructions are identified when D7=0.

The effective address of the instruction is in AR and was placed there during

timing signal T2 for direct instruction and during T3 for the indirect instruction.

The execution of all Memory instructions starts from timing signal T4.

Symbol Operation

decoder

Symbolic description

AND D0 AC← AC ^ M[AR]

ADD D1 AC← AC + M[AR], E ← Cout

LDA D2 AC← M[AR]

STA D3 M[AR]← AC

BUN D4 PC← AR

BSA D5 M[AR] ← PC, PC ← AR+1

ISZ D6 M[AR] ← M[AR]+1,

if M[AR]+1=0 then PC ← PC + 1

Memory-Reference Instructions


AND to AC

D0T4: DR ← M[AR] read operand from memory and store it in DR

D0T5: AC← AC ^ DR, SC ← 0 And AC with DR and save the result in AC

ADD to AC


D1T5: AC← AC + DR, E ← Cout, SC ← 0 add AC with DR and save the result in AC.

LDA: Load to AC


D2T5: AC ← DR, SC ← 0 transferee DR to AC.

STA: Store AC

D3T4: M[AR] ← AC , SC ← 0 save content of AC in memory.


BUN: Branch Unconditionally This instruction transfers the program to the

instruction specified by the effective address in AR.

D4T4: PC ← AR, SC ← 0 transfer the address of the next instruction from AR

to PC.

Note: remember that PC holds the address of the next instruction.

address instruction

100 BUN 135

101 SPA

…….

……..

……..

135 CLA


BSA: Branch &save Address This instruction is useful for branching to a portion of

the program called subroutine. When the subroutine is

finished, the computer returns back to the next instruction

after BSA instruction..

D5T4: M[AR] ← PC, AR←AR+1

D5T5: PC ← AR, SC ← 0

17

0 BSA 135 Next instruction

…..

…..

Subroutine

1 BUN 135

020

021

135

PC=136

0 BSA 135 Next instruction

…..

…..

Subroutine

1 BUN 135

020

PC=021

AR=135

136

(a) Memory, PC, and AR

at time T4

(b) Memory, PC, and AR

after execution.

Memory Memory

Example of BSA instruction execution

Indirect

branch

Save the next

instruction

address

021

Jump

Ret

urn


ISZ: Increment and skip if Zero This instruction increments the word specified by the

effective address, and if the incremented value is zero,

PC is incremented by 1 in order to skip the next

instruction. Since it is not possible to increment a word

inside the memory, it is necessary to read the word into

DR, increment DR, and store the word back into

memory. D5T4: M[AR] ← PC, AR←AR+1

D6T4: DR ← M[AR]

D6T5: DR ← DR+1

D6T6: M[AR] ← DR, if (DR=0) then (PC ← PC+1), SC ← 0.

19

Flowchart for memory-reference instructions

DR M[AR] DR M[AR] DR M[AR]

AC AC ∧ DR

SC 0

AC AC + DR

E Cout

SC 0

AC DR

SC 0

AND ADD LAD

D0 T4 D1 T4 D2 T4

D0 T5 D1 T5 D2 T5

Flowchart for memory-reference instructions


M[AR] AC

SC 0

PC AR

SC 0

M[AR] PC

AR AR+1

DR M[AR]

DR DR+1 PC AR

SC 0

M[AR] DR

IF (DR=0)

Then

(PC←PC+1)

SC 0

STA BUN BSA ISZ

D3 T4 D4 T4 D5 T4 D6 T4

D5 T5 D6 T5

D6 T6

21

Start

SC 0

AR PC

IR M[AR], PC PC+1


AR IR(0-11), I IR(15)

D7

I I


Register-refernce

Instruction

SC 0

Execute

input-output

Instruction

SC 0 Execute


SC 0

T0

T1

T2



T3 T3 T3 T3


D7 I T3 D7 I T3 D7 I T3 D7 I T3

November 4, 2016 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

22

Input-Output Configuration

• The terminal devices send and receive serial information.

• The INPR and OUTR communicate serially with terminals and

in parallel with the AC.

• FGI and FGO are two single bit flip-flops needed to

synchronize the timing rate difference between the terminals

and the computer.

23

Printer

Keyboard

Receiver

interface

Transmitter

interface

OUTR

INPR

AC

FGI

FGO

Input operation

00110110

0

01110111

1

Initially, FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit code

is shifted into INPR and the input flag FGI IS SET TO 1. As long as the flag

FGI=1, the content of INPR cannot be changed with a new code. The computer

checks the FGI flag, if it is 1, the information in INPR is transferred into AC in

parallel and the FGI is cleared to 0. Once the flag is cleared, new information

code can be shifted into INPR by striking another key.

24

Printer

Keyboard

Receiver

interface

Transmitter

interface

OUTR

INPR

AC

FGI

FGO

00110110

0

Output operation

1 0

Initially, FGO is set to 1. The computer checks the flag bit, if it is 1, the

information from AC is transferred in parallel into OUTR and FGO is cleared to 0.

The output device accepts the coded information, prints the corresponding

character, and when the operation is completed, it sets FGO to 1. As long as the

flag FGO is cleared, the computer does not load a new character code into OUTR.

November 4, 2016 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

25

Input-Output Instructions

D7 I T3 =p (common for all input-output instructions)

IR( I ) = Bi [bit in IR (6-11) that specifies the instructions]

p: SC ← 0 Clear SC

INP pB11: AC(0-7) ←INPR, FGI ← 0 Input character

OUT pB10: OUTR ←AC (0-7), FGO ← 0 Output character

SKI pB9: if (FGI=1) then (PC ←PC + 1) Skip on input flag

SKO pB8: if (FGO=1) then (PC ←PC + 1) Skip on output flag

ION pB7: IEN ← 1 Interrupt enable ON

IOF pB6: IEN ←0 Interrupt enable OFF

• Input-output instructions are needed for transferring information to and from

AC register, for checking the input and output flags and for controlling the

interrupt facility.

• Input-output instructions have op-code 1111 and are recognized when D7=1

and I=1.

• The execution of all input-output instructions is done during timing signal T3.

The end of the Lecture


Thanks for your time

Questions are welcome

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