DEPARTMENT OF ELECTRONICS AND

COMMUNICATION

MODEL EXAM

Degree & Branch : ME VLSI

Date : 23.12.2013

Subject : computer architecture and parallel processing

Semester : I

Max. Marks : 100

PART-A (10x2=20)

1. Distinguish uniform and non-uniform memory access systems.

2. Write down the Cache-memory coherence policies.

6. Define miss penalty

7. Write the formula for misses/instruction

5. Why MIPS cannot be used as a performance measure always?.

6. Mention any two difference between multi-vector track and SIMD

track

7. State Amdahl’s law.

8. What is address mapping?

9. State any two difference between synchronous message passing

and asynchronous message passing.

10. What is micro tasking?

PART-B(5x16=80)

11. (a) Discuss the shared memory multiprocessor with neat diagram.

(or)

(b) Explain PRAM and VLSI models with a neat diagram for

each

12. (a) Discuss the grain packing and scheduling

(or)

(b) (i) Write and explain any two applications of parallel

processing .

(ii) Discuss the scalability analysis and its approaches briefly.

13.(a) Explain the various advanced processor technology

(or)

(b) (i) Discuss about backplane bus system in detail

(ii)Explain the sequential and weak consistency models

briefly

14.(a) Write and explain the principles of of multithreading.

(or)

(b) Draw and explain the modular construction of butterfly

switch networks with 8X8 crossbar switches.

15.(a) Discuss the loop parallelization and pipelining with an

example

(or)

(b) Differentiate between SMT and CMP in terms of architectural

view, performance, TLP and ILP.