Computer Architecture

Cache Model

John MorrisElectrical & Computer Enginering/Computer Science, The University of Auckland

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Cache Model

• Cache size: 64 kbytes = 216 bytes• Word size: 4 = 22 bytes = 32 bits• Direct mapped cache• Number of lines = 216/22 = 214 = 16384• 2 bits: byte within a word• 14 bits: address of line• 32-14-2 = 16 bits: tag

32

216 14

Cache Model

• Cache size: 64 kbytes = 216 bytes• Word size: 4 bytes = 32 bits• Line size: 32 = 25 bytes• Set associative cache

• Number of ways = 8• Number of lines = 216/25 = 211 = 2048• Number of sets = 211/23 = 28 = 256• 5 bits: byte within a line• 8 bits: address of set• 32-8-5 = 19 bits: tag

32

519 8

Cache - Conflicts

• Conflicts• Two addresses

separated by 2k+m

will hit the same cache location

p-k-m mk

p bits

tag cache address byte address

Addresses in which these k bitsare the same will map to the same

cache line

Cache Model

• Cache size: 64 kbytes = 216 bytes• Word size: 4 bytes = 32 bits• Line size: 32 = 25 bytes• Set associative cache

• Number of ways = 8• Number of lines = 216/25 = 211 = 2048• Number of sets = 211/23 = 28 = 256• 5 bits: byte within a line• 8 bits: address of set• 32-8-5 = 19 bits: tag

32

519 8

Step size for conflicts28+5 = 8192 bytes

Cache Model – Performance pitfalls

• n-way set associative cachetolerates n conflicts at steps of 2k+m bytes through memory

• Avoid data structures with elements of this sizeeg matrices with rows of 2k+m bytes

Example: matrices with float (4 byte) elements

28+5 / 4 = 2048 elements 2048 element arrays may show poor

performance and are best avoided

Similarly 1024 element arrays of doubles (8 bytes) may process slowly

Using cache onprevious slide:Step size for conflicts28+5 = 8192 bytes