computer architecture lecture 10 mips control unit ralph grishman oct. 2015 nyu

Computer ArchitectureLecture 10

MIPS Control Unit

Ralph GrishmanOct. 2015

NYU

Computer Architecture lecture 8 2

Full core MIPS data path

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Control Logic

• What’s left: setting the proper control lines for each instruction

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instruction Control signals

4Copyright © 2014 Elsevier Inc. All rights reserved.

FIGURE 4.14 The three instruction classes (R-type, load and store, and branch) use two different instruction formats. The jump instructions use another format, which we will discuss shortly. (a) Instruction format for R-format instructions, which all have an opcode of 0. These instructions have three register operands: rs, rt, and rd. Fields rs and rt are sources, and rd is the destination. The ALU function is in the funct field and is decoded by the ALU control design in the previous section. The R-type instructions that we implement are add, sub, AND, OR, and slt. The shamt field is used only for shifts; we will ignore it in this chapter. (b) Instruction format for load (opcode = 35ten) and store (opcode = 43ten) instructions. The register rs is the base register that is added to the 16-bit address field to form the memory address. For loads, rt is the destination register for the loaded value. For stores, rt is the source register whose value should be stored into memory. (c) Instruction format for branch equal (opcode =4). The registers rs and rt are the source registers that are compared for equality. The 16-bit address field is sign-extended, shifted, and added to the PC + 4 to compute the branch target address.

Instruction Formats


Control Logic

• In general, operation depends on both opcode and funct

• Requires a large combinatorial circuit

• We will do this in two steps• ALU function for each instruction• other control lines for each instruction

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Two control units

Divide into two control units:one for ALU, one for other control lines

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Main control

unit

ALU control

opcode

funct ALU

OtherContrpllines


ALU Control InputsALU function A invert Binvert Operation

and 0 0 00

or 0 0 01

add 0 0 10

subtract 0 1 10

set less than 0 1 11

nor 1 1 00

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ALU functions requiredInstruction ALU function

load word add

store word add

and and

or or

add add

subtract subtract

set less than set less than

branch on equal subtract

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Control linesInstruction

RegDst

ALUsrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOp0

R-format

1 0 0 1 0 0 0 1 0

lw 0 1 1 1 1 0 0 0 0

sw X 1 X 0 0 1 0 0 0

beq X 0 X 0 0 0 1 0 1

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Single-cycle control

• Everything happens in one clock cycle:• Fetch instruction• Fetch registers• Do ALU operation• Load from memory + store into register

orStore into memoryorStore into register

• Very slow• Must allow for slowest instruction• Most instructions involve an add or subtract

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Faster adder?

• Ripple-carry adder is very slow (64 gate delays for 32 bits) …can we make a faster adder?

• Approach: incorporate more parallelism into adder

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Carries

Analyze each bit position in terms of its effect on carries:• 1 + 1: generates a carry

• there is always a carry out of this bit position

• 1 + 0: propagates a carry• there is a carry out of this bit position only if there is a carry

in

• 0 + 0: does neither• there is never a carry out of this bit position

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Groups

• We can classify 4-bit groups in the same way:for example:

0 0 0 1+ 1 1 1 1

is a generate group: a carry always comes out (from the high bit)while

0 0 0 0+ 1 1 1 1

is a propagate group: a carry comes out (from the high bit)only if a carry came in (to the low bit)

[see lecture notes for formulas and analysis]

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Carry Look-Ahead

• What is the benefit of using P and G?– they can be computed in parallel for all bits and

groups much faster addition

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Computer Architecture lecture 8 159/30/15

16-bit CLA Adder

computer architecture lecture 10 mips control unit ralph grishman oct. 2015 nyu

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