computer architecture mehran rezaei [email protected]
TRANSCRIPT
2
Welcome
3
Text book
Computer Organization & Design: The Hardware/Software InterfaceDavid A. Patterson and John
E. Hennessy
4th Edition, Morgan Kaufmann
http://books.elsevier.com/companions/1558606041/
4
Overview
• Intro to Computer Architecture
• Administrative Matters
• Course Style, Philosophy and Structure
• High Level, Assembly, and Machine Language
5
What is “Computer Architecture”
Computer Architecture = ?
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What is “Computer Architecture”
Computer Architecture =
Instruction Set Architecture +
Machine Organization
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Instruction Set Architecture
... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964
SOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures: Encodings & Representations-- Instruction Set -- Instruction Formats-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional Conditions
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The Instruction Set: a Critical Interface
instruction set
software
hardware
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MIPS R3000 Instruction Set Architecture
• Instruction Categories– Load/Store– Computational– Jump and Branch– Floating Point
• coprocessor– Memory Management– Special
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
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Organization
• Capabilities & Performance Characteristics of Principal Functional Units(e.g., Registers, ALU, Shifters, Logic Units, ...)
• Ways in which these components are interconnected
• Information flows between componentsData path
• Logic and means by which such information flow is controlled.Control unit
• Choreography of FUs to realize the ISA
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What is “Computer Architecture”?
Coordination of many levels of abstraction
Under a rapidly changing set of forces
Design, Measurement, and Evaluation
I/O systemInstr. Set Proc.
Compiler
OperatingSystem
Application
Digital DesignCircuit Design
Instruction Set Architecture
Firmware
Datapath & Control
Layout
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Forces on Computer Architecture
ComputerArchitectur
e
Technology ProgrammingLanguages
OperatingSystems
History
Applications
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Administrative Stuff
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Course Style (overview handout)
• Grade breakdown– Midterm Exam: 20%– Final Exam: 30%– Project:
30% – Homework Assignments: 20%
• No late homework
• Passing Grade– Project + Homework : necessary requirements– Reasonable grades on exams (50% above)
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Course Problems
• Can’t make midterm– Tell me early and we will schedule alternate time
• Forgot to turn in homework or any other problem– Zero for that assignment
• What is cheating?– Studying together in groups is encouraged– Work must be your own– Common examples of cheating:
• running out of time on a assignment and then pick up output, take homework from box and copy, person asks to borrow solution “just to take a look”, copying an exam question, ...
– Better off to skip assignment
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Reading Assignments
• For the first half of the course, every week, you will have reading assignments. – Every lecture, 5 minutes, about the
reading assignment– Time to time, break out from the text book
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Course Materials (Systematically)
• Instruction Set Architecture
• Computer Arithmetic, ALU
• Measuring the performance of computer system
• CPU design, single cycle and pipelined CPU
• Memory Systems
• I/Os
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Where are we?
• Intro to Computer Architecture
• Administrative Matters
• Course Style, Philosophy and Structure
• High Level, Assembly, Machine Language
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High Level Language Program
Assembly Language Program
Machine Language Program
Control Signal Specification
Compiler
Assembler
Machine Interpretation
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
°°
ALUOP[0:3] <= InstReg[9:11] & MASK
High Level, Assembly, Machine language, and control signals
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw$15, 0($2)lw$16, 4($2)sw$16, 0($2)sw$15, 4($2)
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Levels of Organization (computer Anatomy)
SPARCstation 20
Processor
Computer
Control
Datapath
Memory Devices
Input
Output
Workstation Design Target:25% of cost on Processor25% of cost on Memory(minimum memory size)Rest on I/O devices,power supplies, box
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Execution Cycle
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
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A Prediction by Gordon Moore
0
2
4
6
8
10
12
14
16
18
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
year
Lo
g2
of
Nu
mb
er o
f C
om
po
nen
ts
per
In
teg
rate
d F
un
ctio
n
Courtesy of the graph – Cramming more componentsonto integrated circuits, Electronics, 38(8), April 1965
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The Growth in CPU Speed (lately)
Sources: J. S. Emer. “Simultaneous Multithreading: Multiplying Alpha's Performance”, 12 th Microprocessor Forum, October 1999.
R. E. Kessler. “The Alpha 21264 Microprocessor”, IEEE Micro, 19(2), pp. 24 36, March/April 1999. V. A. Klauser. “Trends in High Performance Microprocessor Design”, Telematik, 7(1), pp. 12 21, April 2001.
Chip's name 21064 - EV4 21164 - EV5 21264 - EV6 21364 - EV7 21464 - EV8
Introduced 1992 1995 1998 X X
Technology 0.75 - 0.5 mm 0.5 - 0.35 mm 0.35 mm 0.18 mm 0.125 mm
Transistors 1.68 M 9 M 15 M 152 M 250 M
Frequency 150 - 275 MHz 300 - 600 MHz 0.6 - 1 GHz 1.2 - 1.4 GHz 1.2 - 2 GHz
Architecture 2-Way In-Order 4-Way In-Order 4-Way Out-Of-Order 4-Way Out-Of-Order 8-Way Out-Of-Order
System on a Chip 4-Way SMT, SoC
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Pace In Memory SpeedColumn Access
Strobe (CAS)/
Year of Slowest Fastest data transfer Cycle
Introduction Chip Size DRAM (ns) DRAM (ns) time (ns) time (ns)
1980 64K bit 180 150 75 250
1983 256K bit 150 120 50 220
1986 1M bit 120 100 25 190
1989 4M bit 100 80 20 165
1992 16M bit 80 60 15 120
1996 64M bit 70 50 12 110
1998 128M bit 70 50 10 100
2000 256M bit 65 45 7 90
2002 512M bit 60 40 5 80
Row Access Strobe (RAS)
Courtesy of the table:J. L. Hennessy and D. A. Patterson. ``Computer Architecture A Quantitative Approach'', Morgan Kaufmann Publishers, Third
Edition 2003.
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CPU-Memory Speed Gap
1
10
100
1000
10000
100000
1980
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
2002
2004
Year
Per
form
ance
Memory CPU
Courtesy of the Graph:J. L. Hennessy and D. A. Patterson. ``Computer Architecture A Quantitative Approach'', Morgan Kaufmann Publishers, Third
Edition 2003.
Ever-increasingCPU-Mem S-Gap