computer architecure 2 marks question bank...

S.SAKTHI, AP/IT, CCET, KARUR

COMPUTER ARCHITECURE

2 MARKS QUESTION BANK

THIRD YEAR EEE- 6TH

SEMESTER


UNIT-1

DATA REPRESENTATION, MICRO-OPERATIONS, ORGANIZATION AND DESIGN

1. What is Registers?

Registers contain either data or control information

Data are numbers and other binary-coded information

Control information is a bit or a group of bits used to specify the sequence of command

signals

2. List out the Data types found in the registers of digital computers

Numbers used in arithmetic computations

Letters of the alphabet used in data processing

Other discrete symbols used for specific purpose

3. Binary-to-Decimal Conversions

1011.1012 = (1 x 23) + (0 x 2

2)+ (1 x 2

1) + (1 x 2

o) + (1 x 2

-1) + (0 x 2

-2) + (1 x 2

-3)

= 810+ 0 + 210 + 110 + 0.510 + 0 + 0.12510

= 11.62510

4. Decimal-to-Binary Conversions

37 / 2 = 18 remainder 1 (binary number will end with 1) : LSB

18 / 2 = 9 remainder 0




1 / 2 = 0 remainder 1 (binary number will start with 1) : MSB

Read the result upward to give an answer of 3710 = 1001012

5. Hex-to-Decimal Conversion

2AF16 = (2 x 162) + (10 x 16

1) + (15 x 16

o)

= 51210 + 16010 + 1510

= 68710

6. Decimal-to-Hex Conversion

42310 / 16 = 26 remainder 7 (Hex number will end with 7) : LSB

2610 / 16 = 1 remainder 10

110 / 16 = 0 remainder 1 (Hex number will start with 1) : MSB

Read the result upward to give an answer of 42310 = 1A716


7 .Hex-to-Binary Conversion

9F216 = 9 F 2

= 1001 1111 0010

= 1001111100102

8 .Binary-to-Hexes Conversion

1 1 1 0 1 0 0 1 1 02 = 0 0 1 1 1 0 1 0 0 1 1 0

3 A 6

= 3A616

9 .Binary-Coded-Decimal Code

Each digit of a decimal number is represented by its binary equivalent

8 7 4 (Decimal)

1000 0111 0100 (BCD)

Only the four bit binary numbers from 0000 through 1001 are used

Comparison of BCD and Binary

13710 = 100010012 (Binary) - require only 8 bits

13710 = 0001 0011 0111BCD (BCD) - require 12 bits

10 .Define Complements

Complements are used in digital computers for simplifying the subtraction

operation and for logical manipulation

There are two types of complements for base r system

r‘s complement 2) (r-1)‘s complement

Binary number : 2‘s or 1‘s complement

Decimal number : 10‘s or 9‘s complement

(r-1)‘s Complement

(r-1)‘s Complement of N = (rn-1)-N

» 9‘s complement of N=546700

(106-1)-546700= (1000000-1)-546700= 999999-546700

= 453299

» 1‘s complement of N=101101

(26-1)-101101= (1000000-1)-101101= 111111-101101

= 010010

r‘s Complement

l r‘s Complement of N = rn-N

» 10‘s complement of 2389= 7610+1= 7611

» 2‘s complement of 1101100= 0010011+1= 0010100


11. Decimal Example (+375) + (-240)

375 + (10‘s comp of 240) = 375 + 760

0 375 (0000 0011 0111 0101)

+9 760 (1001 0111 0110 0000)

0 135 (0000 0001 0011 0101)

12. Define Weighted Code : 2421 code

The bits are multiplied by the weights, and the sum of the weighted bits gives the decimal digit

13. Define Parity Bit

An extra bit included with a binary message to make the total number of 1‘s either odd or even

14. Define Even-parity method

The value of the parity bit is chosen so that the total number of 1s (including the parity bit) is an

even number

15. Define Odd-parity method

Exactly the same way except that the total number of 1s is an odd number

16. Define Register transfer:

Register Transfer is defined as copying the content of one register to another.


17. Define Arithmetic Micro operation

A micro operation is an elementary operation performed with data stored in register. They are

classified into:

Register transfer micro operation

Arithmetic micro operation

Logic micro operation

Shift micro operation

18. List out the Basic arithmetic micro operations.

Basic arithmetic micro operations are:

Addition

Subtraction

Increment

Decrement

Arithmetic Shift

19. Draw Binary Adder:

20. Draw Binary Adder-Subtractor:


21. Draw Binary Incrementor:

22. Define Logic Micro operation

Logic micro operation specify binary operations on the strings of bits in registers.

Logic micro operations are bit-wise operations, i.e., they work on the individual bits of data.

23. Define Shift Micro operations

Shift micro-operations are used for serial transfer of data beside they are used in

conjunction with arithmetic, logic, and other data processing operations. There are 3 types of shift

micro operations. What differentiates them is the information that goes into the serial input:

Logical shift

Circular shift

Arithmetic shift

24. Define Logical Shift:

Logical shift is one that transfers 0 through the serial input. In a Register Transfer

Language, the following notation is used

shl for a logical shift left

shr for a logical shift right

25 . Define Circular Shift:

The circular shift rotates of the register around the two ends without loss of information.

This is accomplished by connecting the two ends of the shift register to each other. the following

notation is used

cil for a circular shift left

cir for a circular shift right

26 . Define Arithmetic Shift:

Arithmetic shift is a micro-operation that shifts a signed binary number to the left or right.

Arithmetic shift must leave sign bit unchanged.

Note that the arithmetic shift right is considered divide by 2 and left shift is considered

multiply by 2. The next two figures show the arithmetic shift right and left respectively.


27. List out the 3 instruction code formats for basic computer.

The Basic Computer has 3 instruction code formats. Each format has 16 bits.

The op-code of the instruction contains 3 bits and the meaning of the remaining 13 bits

depends on the operation code encountered.

Memory reference instruction uses 12 bits to specify the operand address and one bit for

indirect address.

The register reference instruction are recognized by op-code 111 with 0 in left most bit

(Bit 15) of the instruction. The 12 bits are used in to specify the operation done with AC

register.

Input-Output instruction is recognized by op-code 111 and with 1 in bit 15. The

remaining 12 bits are used to specify type of Input-Output instruction type.

28. List out the instruction types.

Instruction Types will be:

Functional Instructions includes

o Arithmetic, logic, and shift instructions

o ADD, CMA, INC, CIR, CIL, AND, CLA

Transfer Instructions

o Data transfers between the main memory and the processor registers

o LDA, STA

Control Instructions

o Program sequencing and control

o BUN, BSA, ISZ

Input-Output Instructions

o Input and output

o INP, OUT


29 .Give the implementations of control units.

Control units are implemented in one of two ways:

Hardwired Control

o CU is made up of sequential and combinational circuits to generate the control

signals

Micro-programmed Control

o A control memory on the processor contains micro-programs that activate the

necessary control signals

30.Define Instruction Cycle

In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address

4. Execute the instruction

After an instruction is executed, the cycle starts again at step 1, for the next instruction

31. List of all memory reference Instructions:


32. Draw the design of Accumulator Logic


UNIT-2

CONTROL AND CENTRAL PROCESSING UNIT

1. Define Microprogram

1. Program stored in memory that generates all the control signals required to execute the

instruction set correctly

2. Consists of microinstructions

2. Define Microinstruction

Contains a control word and a sequencing word

3. Define Control Word -All the control information required for one clock cycle

4. Define Sequencing Word -Information needed to decide the next microinstruction address

Vocabulary to write a microprogram

5. Define Control Memory(Control Storage: CS)

Storage in the microprogrammed control unit to store the microprogram

6. Define Writeable Control Memory(Writeable Control Storage:WCS)

1. CS whose contents can be modified

2. Allows the microprogram can be changed

3. Instruction set can be changed or modified

7. Define Dynamic Microprogramming

Computer system whose control unit is implemented with a microprogram in WCS

Microprogram can be changed by a systems programmer or a user

8. Define Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines the Microinstruction Address to be executed

in the next clock cycle

1. In-line Sequencing

2. Branch

3. Conditional Branch

4. Subroutine

5. Loop

6. Instruction OP-code mapping

9. Give machine instruction format.


10. Give the two types of control units:

―Hardwired control unit‖ is implemented using conventional logic design techniques.

―Microprogramming‖ is another implementation for building control units.

11. Define Control word

It is a series of 0‘s and 1‘s that can be programmed to perform different operations on

components of the system

12. Define Microprogram

Program stored in memory that generates all the control signals required to execute the

instruction set correctly

Consists of microinstructions

13. Define Microinstruction

Contains a control word and a sequencing word

Control Word -All the control information required for one clock cycle

Sequencing Word -Information needed to decide the next microinstruction address

14. Define Control Address Register

Specifies address of microinstructions, and control data register holds microinstruction

Microinstruction contains control word that specifies one or more microoperations

Once these operations are executed, control must determines next address

Microinstructions contain bits for initiating microoperations and bits that determines the

address sequence for the control memory

15. List out the Address sequence capability required in control memory.

Address sequence capability required in control memory are:

o Incrementing CAR

o Unconditional-Conditional branching depending on status bits

o Mapping from bits of instruction to address in control memory

o Subroutine call-return facility

16. Give Mapping format:


17. Define Microinstruction Format Microinstruction format of control memory is shown in next Figure. It shows 20 bit of

microinstruction divided to:

o F1, F2, F3 that specify 3 microoperations executed in same clock cycle

o CD field for specifying branch status bit condition

o BR field that determines type of branch.

o AD which is 7-bit address field that can a location of 128 different addresses

18. Define Symbolic Microinstructions

Each line of assembly line Microprogram defines a symbolic microinstruction. Each

symbolic microinstruction is divided into 5 fields:

o Label: empty or may specify symbolic address and ends with semicolon

o CD: one of (U, S, I, Z) status bits will be tested for branch decision

o BR: one of next operations (JMP, CALL, RET, MAP)

o AD: Address field on of next selections (Address, NEXT, or EMPTY)

19. Give the parts of CPU.

The CPU is made of 3 parts:

1. Registers: stores intermediate data generated during execution

2. ALU: performs required micro operations

3. Control Unit: controls transfer of data among registers and instruct ALU to perform

correct operation

20. Define CONTROL WORD

There are 14 selection inputs in the unit and their combined value specifies control word.

21. ALU provides:

Arithmetic operations (ADD, SUB, INCA, DECA)

Logic operations (AND, OR, XOR, COMA)

Shift operations (SHLA SHRA).

And Transfer operation (TSFA)


22. Derive a control word (CW) that executes the next statement: Field SELA SELB SELD OPR

Symbol R2 R3 R1 SUB

CW 010 011 001 00101

23. Define Stack Organization.

Stack is a storage device that stores information in a way that the item is stored last is the

first to be retrieved (LIFO).

Stack in computers is actually a memory unit with address register (stack pointer SP) that

can count only. SP value always points at top item in stack.

24. List out the two operations done on stack.

The two operations done on stack are

PUSH (Push Down), operation of insertion of items into stack

POP (Pop Up), operation of deletion item from stack

Those operation are simulated by INC and DEC stack register (SP).

25. Define Register stack .

A stand alone unit that consists of collection of finite number of registers.

26. Write down the Procedures for pushing stack.

Initially, SP = 0, EMPTY = 1, FULL =0

Procedures for pushing stack

SP -> SP + 1

M[SP] -> DR

IF (SP = 0) THEN (FULL = 1)

EMTY -> 0


27. Write down the Procedures for popping stack.

DR -> M[SP]

SP -> SP – 1

IF (SP = 0) THEN (EMTY = 1)

FULL -> 0

28.List out the 3 notations to evaluate expressions.

The 3 notations to evaluate expressions

1. A + B Infix notation

2. +AB Prefix notation (Polish notation)

3. AB+ Postfix notation (reverse Polish notation)

29. Define Reverse Polish Notation

It is in a form suitable for stack manipulation. Starts by scanning expression from left to

right. When operator is found then perform operation with 2 operands in left of operator and

replace result place of 2 operands and operator.

30. Convert infix notation expression (A + B)*(C * (D + E) + F) to RPN?

AB+ DE+ C * F+ *.

31. List out the three most common CPU organizations:

1. Single accumulator organization:

ADDX /* AC -> AC + M[X] */

2. General register organization:

ADD R1, R2, R3 /* R1 -> R2 + R3 */

ADD R1, R2 /* R1 -> R1 + R2 */

MOVR1, R2 /* R1 -> R2 */

ADD R1, X /* R1 -> R1 + M[X] */

3. Stack organization:

PUSHX /* TOS -> M[X] */

ADD


32. Define Three-Address Instructions

Program to evaluate X = (A + B) * (C + D):

ADD R1, A, B /* R1 -> M [A] + M[B]*/

ADD R2, C, D /* R2 -> M[C] + M[D]*/

MUL X, R1, R2 /* M[X--] -> R1 * R2*/

o Results in short programs

o Instruction becomes long (many bits)

33. Define Two-Address Instructions


MOV R1, A /* R1 -> M[A] */

ADD R1, B /* R1 -> R1 + M[A] */

MOV R2, C /* R2 -> M[C] */

ADD R2, D /* R2 -> R2 + M[D] */

MUL R1, R2 /* R1 -> R1 * R2 */

MOV X, R1 /* M[X] -> R1 */

34. Define One-Address Instructions

Use an implied AC register for all data manipulation


LOAD A /* AC -> M[A] */

ADD B /* AC -> AC + M[B] */

STORE T /* M[T] -> AC */

LOAD C /* AC -> M[C] */

ADD D /* AC -> AC + M[D]*/

MUL T /* AC -> AC * M[T]*/

STORE X /* M[X] -> AC */

35. Define Zero-Address Instructions

Can be found in a stack-organized computer


PUSHA /* TOS -> A*/

PUSHB /* TOS -> B*/

ADD /* TOS -> (A + B)*/

PUSHC /* TOS -> C*/

PUSHD /* TOS -> D*/

ADD /* TOS -> (C + D)*/

MUL /* TOS -> (C + D) * (A + B) */

POPX /* M[X] ->TOS*/

36. What are addressing modes?

The different ways in which the location of an operand is specified in an instruction are

referred to as addressing modes.

37. Define Implied mode:

o The operands are specified implicitly in the definition of the instruction.


o No need to specify address in the instruction

o All register reference instruction in Basic Computer that uses accumulator is from

this type. Since registers holding operand(s) are implied in op code of the operation

itself.

o Zero address instructions in stack-organized computers are implied mode

instruction since operands are implied always at top of stack.

Examples from Basic Computer:

CLA, CME, INP

38. Define immediate mode:

Instead of specifying the address of the operand, operand itself is specified with the

instruction.

o No need to specify address in the instruction

o However, operand itself needs to be specified

o Sometimes, require more bits than the address

o Fast to acquire an operand

o Useful mode to initialize registers to constant values (initial).

39. Define Register mode

Address specified in the instruction is the register address that resides within CPU.

o Designated operand need to be in a register

o Shorter address than the memory address

o Saving address field in the instruction

o Faster to acquire an operand than the memory addressing-

o EA = IR(R) (IR(R): Register field of IR)

40. List out the 3 different Relative Addressing Modes depending on R.

o PC Relative Addressing Mode(R = PC)

+ 24 = 850.

o Indexed Addressing Mode(R = IX, where IX: Index Register)

o Base Register Addressing Mode(R = BAR, where BAR: Base Address Register)

41. Define Indexed Addressing mode

The content of index register is added to address part of instruction to obtain Effective Address

(EA).

42. Define register addressing mode.

In register addressing mode, the operand is the contents of a processor register. The name

(address) of the register is given in the instruction.


43. Define absolute addressing mode.

In absolute addressing mode, the operand is in a memory location. The address of this

location is given explicitly in the instruction. This is also called as direct addressing mode.

44. Define indirect addressing mode.

The effective address of the operand is the contents of a register or memory location whose

address appears in the instruction. This is called as indirect addressing mode.

45. What is indexed addressing mode?

The effective address of the operand is generated by adding a constant value to the contents

of a register. This is called as indexed addressing mode.

46. What is relative addressing mode?

The effective address is determined by the index mode using the program counter in place

of general purpose register. This mode is used to access the data operands.

47. What is auto increment mode?

The effective address of the operand is the contents of a register specified in the instruction.

After accessing the operand, the contents of this register are automatically incremented to point the

next item in a list.

48. What is auto decrement mode?

The contents of a register specified in the instructions are first automatically decremented

and then used as the effective address of the operand.

EXAMPLE:

Below figure shows a two word instruction at address 200 and 201 that ―load to AC‖. The

instruction has an address field occupying second word of value 500.

The first word specifies op code while second word specifies address of operand

o PC= 200

o R1 = 400 ( register)

o XR = 100 (index register)

Mode field can specifies any mode mentioned earlier

1. In direct mode EA=500 and M[500] = 800. So AC = 800

2. In immediate mode EA=201. Second word of instruction is loaded to AC. So AC = 500

3. In Indirect mode M[500] = 800 which is EA. And M[800] = 300 be loaded into AC. So AC =

300.

4. In relative mode EA=500+202=702. M[702] = 325. So operand=325

5. In index mode EA=XR + 500 = 100 + 500 = 600. M[600] = 900. So AC = 900

6. In register mode operand is in R1. So 400 is loaded into AC. AC = 400

7. In register indirect mode EA=400. M[400] = 700. So AC = 700

8. In auto decrement mode AC= M[R1 – 1] = M[399] = 450


49. Define Data transfer instructions

Moves data from one place to another. The most common transfer are between memory

and processor registers, between processor registers and IO, and between processor registers.


Note that

o ADR address

o NBR number

o X index register

o R1 processor register

o AC accumulator

o @ indirect addressing

o $ relative address to PC

o # immediate operand

o ( ) register indirect mode

o + auto increment combined with register indirect

o _ auto decrement combined with register indirect

50. Define Arithmetic Instructions

They will be the 4 basic operations: Add, Subtract, Multiply, and Divide.

Multiplication and Division usually generated using software subroutines.

51. Define Logical and Bit manipulation instructions

Logical instructions perform binary operations on bits stored in registers and maybe in

memory.

Helpful for manipulating single bits or group of bits

Performs on single bits as separated from each other and treated as Boolean variable.

52. Give status bit conditions.

Status Bit Conditions

ALU of any processor is equipped with condition code bits or flags. Next figure

shows 8-bit ALU with 4-bit status flags (C, S, Z, and V). those can be set and

cleared.

In Basic Computer, the processor had several (status) flags –1 bit value that

indicated various information about the processor‘s state –E, FGI, FGO, I, IEN, R

C (Carry): Set to 1 if the carry out of the ALU is 1

S (Sign): The MSB bit of the ALU‟ s output

Z (Zero): Set to 1 if the ALU‟ s output is all 0‟ s

V (Overflow): Set to 1 if there is an overflow if last 2 carries = 1. If output of

ALU > 127 or < - 128.


53. Define RISC Reduced Instruction Set Computers

fewer instructions and addressing modes

54. Define Complex Instruction Set Computers (CISC)

These computers with many instructions and addressing modes came to be known as

Complex Instruction Set Computers (CISC)

55. Give the features of RISC processors.

o Few instructions

o Few addressing modes

o Only load and store instructions access memory

o All other operations are done using on-processor registers

o Fixed length instructions

o Single cycle execution of instructions

o The control unit is hardwired, not microprogrammed

56. List out the major characteristics of CISC architecture.

A large number of instructions– typically from 100 to 250 instructions

Some instructions that perform specialized tasks and are used infrequently

A large variety of addressing modes—typically from 5 to 20 different modes

Variable-length instruction formats

Instructions that manipulate operands in memory

57. Define Overlapped register windows:

Some computers provide multiple-register banks, and each procedure is allocated its own

bank of registers. This eliminates the need for saving and restoring register values.

Some computers use the memory stack to store the parameters that are needed by the

procedure, but this required a memory access every time the stack is accessed.

A characteristics of some RISC processors is their use of overlapped register windows to

provide the passing of parameters and avoid the need for saving and restoring register

values.

58.Give the calculation for Overlapped register windows The number of registers available for each window is calculated as followed:

window size = L + 2C + G

The total number of registers needed in the processor is

register file = (L + C)W + G

59. Define Berkeley RISC I: The Berkeley RISC I is a 32-bit integrated circuit CPU.

It supports 32-bit address and either 8-, 16-, or 32-bit data.

It has a 32-bit instruction format and a total of 31 instructions.

There are three basic addressing modes:

Register addressing, immediate operand, and relative to PC addressing for

branch instructions.

It has a register file of 138 registers

10 global register and 8 windows of 32registers in each


60. Give an example for Instruction set of Berkeley RISC I.

The data manipulation instructions

ADD R22, R21, R23 R23 R22 + R21

ADD R22, #150, R23 R23 R22 + 150

ADD R0, R21, R22 R22 R21 (Move)

ADD R0, #150, R22 R22 150 (Load immediate)

ADD R22, #1, R22 R22 R22 + 1 (Increment)

61. Write down the data transfer instructions in Instruction set of Berkeley RISC I:

Consist of six load instructions, three store instructions, and two instructions

that transfer the program status word PSW.

PSW contains the status of the CPU and includes the program counter, the

status bits from the ALU, pointers used in conjunction with the register

windows, and other info. That determine the state of the CPU.

LDL (R22)#150, R5 R5 M[R22] + 150

LDL (R22)#0, R5 R5 M[R22]

LDL (R0)#500, R5 R5 M[500]

62. List out some Data manipulation instructions.

ADD Rs,S2,Rd Rd Rs + S2 Integer add

ADDC Rs,S2,Rd Rd Rs + S2 + carry Add with carry

SUB Rs,S2,Rd Rd Rs - S2 Integer subtract

SUBC Rs,S2,Rd Rd Rs - S2 - carry Subtract with carry

SUBR Rs,S2,Rd Rd S2 – Rs Subtract reverse

SUBCR Rs,S2,Rd Rd S2 – Rs – carry Subtract with carry

AND Rs,S2,Rd Rd Rs S2 AND

OR Rs,S2,Rd Rd Rs V S2 OR

XOR Rs,S2,Rd Rd Rs S2 Exclusive-OR

SLL Rs,S2,Rd Rd Rs shifted by S2 Shift-left

SRL Rs,S2,Rd Rd Rs shifted by S2 Shift-right logical

SRA Rs,S2,Rd Rd Rs shifted by S2 Shift-right arithmetic

63. List out some Data transfer instructions

LDL (Rs)s2,Rd Rd M[Rs + S2] Load long

LDSU (Rs)s2,Rd Rd M[Rs + S2] Load short unsigned

LDSS (Rs)s2,Rd Rd M[Rs + S2] Load short signed

LDBU (Rs)s2,Rd Rd M[Rs + S2] Load byte unsigned

LDBS (Rs)s2,Rd Rd M[Rs + S2] Load byte signed

LDHI Rd,Y Rd Y Load immediate high

STL Rd,(Rs)S2 M[Rs + S2] Rd Store long

STS Rd,(Rs)S2 M[Rs + S2] Rd Store short

STB Rd,(Rs)S2 M[Rs + S2] Rd Store byte

GETPSW Rd Rd PSW Load status word

PUTPSW Rd PSW Rd Set status word


64. List out some Program control instructions

JMP COND,S2(Rs) PC Rs + S2 Conditional jump

JMPR COND,Y PC PC + Y Jump relative

CALL Rd,S2(Rs) Rd PC Call subroutine

PC Rs + S2 and

CWP CWP –1 change window

CALLR Rd,Y Rd PC Call relative

PC PC + Y and

CWP CWP – 1 change window

RET Rd,S2 PC Rd + S2 Return and

CWP CWP + 1 change window

CALLINT Rd Rd PC Disable interrupts

CWP CWP –1

RETINT Rd,S2 PC Rd + S2 Enable interrupt

CWP CWP + 1

GTLPC Rd Rd PC Get last PC


UNIT-3

COMPUTER ARITHMETIC, PIPELINE AND VECTOR PROCESSING

1. List out the different possibilities of Addition and Subtraction of Signed-Magnitude

Numbers:

2.Define Booth algorithm :

Booth algorithm needs examination of the multiplier bits and shifting of the partial product. Prior

to the shifting, the multiplicand added to the partial product, subtracted from the partial product, or

left unchanged by the following rules:

1. The multiplicand is subtracted from the partial product when we get the first least

significant 1 in a string of 1's in the multiplier.

2. The multiplicand is added to the partial product when we get the first Q (provided

that there was a previous 1) in a string of 0's in the multiplier.

3. The partial product does not change when the multiplier bit is the same as the

previous multiplier bit.

3.Give the algorithm for performing restoring division.

The algorithm for performing restoring division is as follows.

1. Shift A and Q left one binary position.

2. Subtract M from A, and place the answer back in A.

3. If the sign of A is 1, set q0 to 0 and add M back to A;otherwise set q0 to 1.


4.Draw 2-bit by 2-bit array multiplier:

5.Draw 4-bit by 3-bit array multiplier:

6.When divide-overflow occurs?

A divide-overflow occurs if the high-order half bits of the dividend makes a number

greater than or equal to the divisor. Another problem associated with division is the fact that a

division by zero must be avoided. The divide-overflow condition takes care of this condition as

well. This occurs because any dividend will be greater than or equal to a divisor, which is equal to


zero. Overflow condition is usually detected when a special flip-flop is set. We will call it a divide-

overflow flip-flop and label it DVF.

7.List out the consecutive parts of Addition and Subtraction of Floating Point Numbers:

1. Check for zeros.

2. Align the mantissas.

3. Add or subtract the mantissas

4. Normalize the result

8. Draw the block Diagram of BCD Adder

9. Define Parallel processing

A parallel processing system is able to perform concurrent data processing to achieve faster

execution time

10. Write down the goal of parallel processing:

To increase the throughput

11. Define Throughput, instruction stream, and data stream

Throughput – the amount of processing that can be accomplished during a given interval

of time

The sequence of instructions read from memory is the instruction stream

The operations performed on the data in the processor is the data stream

12. Give Flynn’s Computer classification:

o Single instruction stream, single data stream – SISD

o Single instruction stream, multiple data stream – SIMD

o Multiple instruction stream, single data stream – MISD

o Multiple instruction stream, multiple data stream – MIMD

13. Define SISD – Instructions are executed sequentially. Parallel processing may be achieved by

means of multiple functional units or by pipeline processing


14. Define SIMD – Includes multiple processing units with a single control unit. All processors

receive the same instruction, but operate on different data.

15. Define MIMD – A computer system capable of processing several programs at the same time.

16. Define Pipelining is a technique of decomposing a sequential process into suboperations, with

each subprocess being executed in a special dedicated segment that operates concurrently with all

other segments

17.Write down the speedup of a pipeline.

The speedup of a pipeline processing over an equivalent nonpipeline processing is defined by the

ratio S = ntn .

(k + n – 1)tp

18. Define Arithmetic Pipeline

1. Pipeline arithmetic units are usually found in very high speed computers

2. They are used to implement floating-point operations, multiplication of fixed-point

numbers,

3. and similar computations encountered in scientific problems

19. Define Arithmetic Pipeline

Four segments are used to perform the following:

o Compare the exponents

o Align the mantissas

o Add or subtract the mantissas

o Normalize the result

20. Define Instruction Pipeline

1. An instruction pipeline reads consecutive instructions from memory while previous

instructions are being executed in other segments

2. This causes the instruction fetch and execute phases to overlap and perform

simultaneous operations

21. Define Instruction Pipeline

The following steps are needed to process each instruction:

o Fetch the instruction from memory

o Decode the instruction

o Calculate the effective address

o Fetch the operands from memory

o Execute the instruction

o Store the result in the proper place


22. Give the reasons for the pipeline to deviate from its normal operation.

o Resource conflicts caused by access to memory by two segments at the same

time.

o Data dependency conflicts arise when an instruction depends on the result of a

previous instruction, but his result is not yet available

o Branch difficulties arise from program control instructions that may change the

value of PC

23. List out the methods to handle data dependency:

o Hardware interlocks are circuits that detect instructions whose source operands

are destinations of prior instructions. Detection causes the hardware to insert the

required delays without altering the program sequence.

o Operand forwarding uses special hardware to detect a conflict and then avoid it

by routing the data through special paths between pipeline segments. This

requires additional hardware paths through multiplexers as well as the circuit to

detect the conflict.

o Delayed load is a procedure that gives the responsibility for solving data conflicts

to the compiler. The compiler is designed to detect a data conflict and reorder

the instructions as necessary to delay the loading of the conflicting data by

inserting no-operation instructions.

24. List out the methods to handle branch instructions:

o Prefetching the target instruction in addition to the next instruction allows either

instruction to be available.

o A branch target buffer is an associative memory included in the fetch segment

of the branch instruction that stores the target instruction for a previously

executed branch. It also stores the next few instructions after the branch target

instruction. This way, the branch instructions that have occurred previously are

readily available in the pipeline without interruption.

o The loop buffer is a variation of the BTB. It is a small very high speed register

file maintained by the instruction fetch segment of the pipeline. Stores all

branches within a loop segment.

o Branch prediction uses some additional logic to guess the outcome of a

conditional branch instruction before it is executed. The pipeline then begins

prefetching instructions from the predicted path.

o Delayed branch is used in most RISC processors so that the compiler rearranges

the instructions to delay the branch.

25. List out the representative application areas where vector processing is of the utmost

importance.

The following are representative application areas where vector processing is of the

utmost importance:

• Long-range weather forecasting

• Petroleum explorations

• Seismic data analysis

• Medical diagnosis

• Aerodynamics and space flight simulations


Artificial intelligence and expert systems

• Mapping the human genome & Image processing

26.Define Memory Interleaving

Interleaving is an advanced technique used by high-end motherboards/chipsets to improve memory

performance. Memory interleaving increases bandwidth by allowing simultaneous access to more

than one chunk of memory. This improves performance because the processor can transfer more

information to/from memory in the same amount of time, and helps alleviate the processor-

memory bottleneck that is a major limiting factor in overall performance. Interleaving works by

dividing the system memory into multiple blocks. The most common numbers are two or four,

called two-way or four-way interleaving, respectively.

An instruction pipeline may require the fetching of an instruction and an operand at

the same time from two different segments.

An arithmetic pipeline usually requires two or more operands to enter the pipeline

at the same time.

Instead of using two memory buses for simultaneous access, the memory can be

partitioned into a number of modules connected to a common memory address and

data buses.

27.What is Supercomputers?

A supercomputer is a computer system best known for its high computational speed, fast

and large memory systems, and the extensive use of parallel processing.

It is equipped with multiple functional units and each unit has its own pipeline

configuration.

28.Define Flops:

A measure used to evaluate computers in their ability to perform a given number of floating-point

operations per second is referred to as flops

29.Define Array Processors

An array processor is a processor that performs computations on large arrays of data.

The term is used to refer to two different types of processors.

Attached array processor:


Is an auxiliary processor.

It is intended to improve the performance of the host computer in specific

numerical computation tasks.

SIMD array processor:

Has a single-instruction multiple-data organization.

It manipulates vector instructions by means of multiple functional units

responding to a common instruction.

30.List out the two different types of array processors:

Attached array processor

SIMD array processor

31.What is Attached Array Processor?

Its purpose is to enhance the performance of the computer by providing vector processing

for complex scientific applications.

Parallel processing with multiple functional units

32. What is SIMD Array Processor?

An SIMD array processor is a computer with multiple processing units operating in

parallel.

33.Give an example for SIMD Array Processor.

The ILLIAC IV computer developed at the University of Illinois and manufactured by the

Burroughs Corp.

Are highly specialized computers.

They are suited primarily for numerical problems that can be expressed in vector or

matrix form.

34. Compare scalar and vector processor.

Scalar processor:

It processes one data item at a time.

Vector processor:

A single instruction operates simultaneously on multiple data items.

35.Define Superscalar Processors.

A superscalar architecture is one in which several instructions can be initiated

simultaneously and executed independently. Superscalar architectures allow several instructions to

be issued and completed per clock cycle.


UNIT-4

INPUT-OUTPUT ORGANIZATION

1. List out some Peripheral Devices

Video monitors, Printers, Magnetic tapes.

2. What is Input-output interface?

Input-output interface provides a method for transferring information between internal

storage and external I/O devices.

3. Draw the Connection of I/O bus to input-output devices

4. List out the three ways that computer buses can be used to communicate with memory and

I/O:

1. Use two separate buses, one for memory and the other for I/O.

2. Use one common bus for both memory and I/O but have separate control lines for

each.

3. Use one common bus for memory and I/O with common control lines.

5. Compare Isolated versus Memory-Mapped I/O

In the isolated I/O configuration, the CPU has distinct input and output instructions, and

each of these instructions is associated with the address of an interface register.

The isolated I/O method isolates memory and I/O addresses so that memory address values are not

affected by interface address assignment since each has its own address space.


6. Define Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that control signals be

transmitted between the communicating units to indicate the time at which data is being

transmitted. One way of achieving this is by means of a strobe pulse supplied by one of the units to

indicate to the other unit when the transfer has to occur

7. Define Asynchronous communication interface or a universal asynchronous receiver-

transmitter (UART):.

Integrated circuits are available which are specifically designed to provide the interface

between computer and other interactive terminals like keyboard. Such a circuit is called an

asynchronous communication interface or a universal asynchronous receiver-transmitter (UART).

8.Data transfer to and from peripherals may be handled in one of three possible modes:

1. Programmed I/O

2. Interrupt-initiated I/O

3. Direct memory access (DMA)

9. Define Programmed I/O:

Programmed I/O operations are the result of I/O instructions written in the computer

program. Each data item transfer is initiated by an instruction in the program. Usually, the transfer

is to and from a CPU register and peripheral. Other instructions are needed to transfer the data to

and from CPU and memory. Transferring data under program control requires constant monitoring

of the peripheral by the CPU. Once a data transfer is initiated, the CPU is required to monitor the

interface to see when a transfer can again be made. The CPU stays in a program loop until the I/O

unit indicates that it is ready for data transfer. This is a time-consuming process since it keeps the

processor busy needlessly.

10. Define Interrupt-initiated I/O:

It can be avoided by using an interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the data are available from the device. In the

meantime the CPU can proceed to execute another program. The interface meanwhile keeps

monitoring the device. When the interface determines that the device is ready for data transfer, it

generates an interrupt request to the computer.

11. Define Direct memory access (DMA): In direct memory access (DMA), the interface

transfers data into and out of the memory unit through the memory bus.


12. What is Priority Interrupt?

A priority interrupt is a system that establishes a priority over the various sources to

determine which condition is to be serviced first when two or more requests arrive simultaneously.

13. Write notes on Daisy-Chaining Priority.

The daisy-chaining method of establishing priority consists of a serial connection of all

devices that request an interrupt. The device with the highest priority is placed in the first position,

followed by lower-priority devices up to the device with the lowest priority, which is placed last in

the chain. This method of connection between three devices and the CPU is shown in Fig. below.

14. What is Interrupt Cycle?

The interrupt enable flip-flop IEN can be set or cleared by program instructions. When IEN

is cleared, the interrupt request coming from 1ST is neglected by the CPU. The program-controlled

IEN bit allows the programmer to choose whether to use the interrupt facility. If an instruction to

clear IEN has been inserted in the program, it means that the user does not want his program to be

interrupted. An instruction to set IEN indicates that the interrupt facility will be used while the

current program is running.

15. Define bus request.

The bus request (BR) input is used by the DMA controller to request the CPU to release the

control of buses.

16. Define bus grant.

The CPU activates the bus grant (BG) output to inform the external DMA that the buses are free.

17.Define burst transfer

In DMA burst transfer, a block sequence consisting of a number of memory words is transferred

in a continuous burst while the DMA controller is master of the memory buses.


18. Define cycle stealing

An alternative technique called cycle stealing allows the DMA controller to transfer one data word

at a time, after which it must return control of the buses to the CPU.

19.The CPU initializes the DMA by sending the following information through the data bus:

1. The starting address of the memory block where data are available or where data are to

be stored.

2. The word count, which is the number of words in the memory block.

3. Control to specify the mode of transfer such as read or write

4. A control to start the DMA transfer

20. Define Commands:

Instructions that are read from memory by an IOP are sometimes called commands, to

distinguish them from instructions that are read by the CPU. Commands are prepared by

experienced programmers and are stored in memory. The command words constitute the program

for the IOP. The CPU informs the IOP where to find the commands in memory when it is time to

execute the I/O program.

21. Draw IBM 370 I/O word formats.

22.The command field corresponds to an operation code that specifies one of six basic types

of I/O operations:

1. Write. Transfer data from memory to I/O device.

2. Read. Transfer data from I/O device to memory.

3. Read backwards. Read magnetic tape with tape moving backward.

4. Control. Used to initiate an operation not involving transfer of data, such

as rewinding of tape or positioning a disk-access mechanism.

5. Sense. Informs the channel to transfer its channel status word to

memory location 64.

6. Transfer in channel. Used instead of a jump instruction. Here the data address field

specifies the address of the next command word to be executed by the channel.


23. What is Serial Communication?

A data communication processor is an I/O processor that distributes and collects data from

many remote terminals connected through telephone and other communication lines. A

communication network may consist of any of a wide variety of devices, such as printers,

interactive display devices, digital sensors, or a remote computing facility.

Extra Questions:

1. What is memory mapped I/O?

With memory mapped I/O, any machine instruction that can access memory can be used to

transfer data to or from an I/O device.

2. What constitute the device’s interface circuit?

The address decoder, the data and status register and the control circuitry required to co–

ordinate I/O transfers constitute the device‘s interface circuit.

3. What is interrupt service routine?

The routine executed in response to an interrupt request is called as interrupt service

routine. In short, it is called as ISR.

4. Define interrupt latency.

The delay between the time an interrupt request is received and the start of execution of the

interrupt service routine is called interrupt latency.

5. What is the difference between subroutine and interrupt service routine?

Subroutine is the routine which could be called by another subroutine or main routine

under program control. Interrupt Service Routine is called automatically on the occurrence of an

interrupt which is predefined.

6.Give a typical scenario assuming that interrupts are enabled.

The typical scenario is as follows :

1. The device raises an interrupt request.

2. The processor interrupts the program currently being executed.

3. Interrupts are disabled by changing the control bits in the PS.

4. The device is informed that its request has been recognized and in response, it deactivates

the

interrupt request signal.

5. The action requested by the interrupt is performed by the ISR.

6. Interrupts are enabled and execution of the interrupted program is resumed.

7.What are vectored interrupts?

To reduce the time involved in the polling process, a device requesting an interrupt may

identify itself directly to the processor. Then the processor can immediately start executing the

corresponding ISR. The term vectored interrupts refer to all interrupt handling schemes based on

this approach.


8.What is interrupt vector?

Interrupt vector is the starting address of the interrupt service routine stored in the location

pointed by the interrupting device.

9.What are privileged instructions?

Privileged instructions are the instructions which are executed only while the processor is

running in the supervisor mode.

10.What is privilege exception?

An attempt to execute a privileged instruction while in the user mode leads to a special type

of interrupt called a privilege exception.

11.What are exceptions? Give an example.

An except is a term often used to refer to any event that cause an interruption.

Example : I / O interuupts

12.What is a debugger?

A debugger is a program used by system software which helps the programmer finds errors

in a program.

13 What are the two facilities provided by a debugger?

The facilities provided by a debugger are,

1. Trace

2. Break points.

14. When does an exception occur when the processor is in trace mode?

When the processor is operating in the trace mode, an exception occurs after execution of

every instruction, using the debugging program as the exception service routine. The trace

exception is disabled during the execution of debugging program.

15.What are the uses of interrupts in OS?

The Uses of interrupts in OS are,

1. To assign priorities

2. Switch from one user program to another.

3. Implementing security.

4. Protection features.

5. Co–ordinate I/O activities.

16.What is a process?

A program, together with any information that describes its current state of execution, is

regarded by the OS as an entity called a process.

17 Define multitasking.

Multitasking is a mode of operation in which a processor executes several user programs at

the same time.


18.What is time slicing?

Time slicing is a common OS technique that makes multitasking possible. With this

technique, each program runs for a short time period called as a time slice,t, then another program

runs for its time slice and so on. The period t, is determined by continuously running hardware

clock, which generates an interrupt every t seconds.

19.What is a program state?

A program state is state which includes register contents, program counter and the program

status word.

20.What is DMA?

A special control unit that may be provided to allow transfer of a block of data directly

between an external device and the main memory, without continuous intervention by the

processor. This approach is called direct memory access (DMA).

21.What is the purpose of DMA controller?

The DMA controller performs the functions that would normally be carried out by the

processor when accessing the main memory.

22.What is cycle stealing?

Cycle stealing is an interweaving technique used by DMA controller to steal the memory

cycles from the processor.

23.What is a block or burst mode?

The DMA controller may be given exclusive to the main memory to transfer a block of

data without interruption. This is known as block or burst mode.

24.What is a bus master?

The device that is allowed to initiate data transfers on the bus at any given time is called

bus master.

25.What is bus arbitration?

Bus arbitration is the process by which the next device to become the bus master is selected

and bus mastership is transferred to it.

26 Name the two approaches to bus arbitration.

The approaches to bus arbitration are,

1. Centralized arbitration

2. Distributed arbitration

29. What do you mean by distributed arbitration?

Distributed arbitration means that all devices waiting to use the bus have equal

responsibility in carrying out the arbitration process, without using a central arbiter.

30. What is the purpose of a bus protocol?

A bus protocol is the set of rules that governs the behavior of various devices connected to

the bus as to when to place information on the bus, assert control signals and so on.


31. Define master.

Master is a device that initiates data transfer by issuing read or write commands on the bus.

Master is also called as initiator.

32 What is a slave?

The device addressed by the master is called as slave. Slave can also be called as target.

33. What is a synchronous bus?

In synchronous bus, all devices derive timing information from the common clock line.

Equally spaced pulses on this define equal time intervals.

34. What is a asynchronous bus?

In asynchronous bus, controlling data transfer on the bus is based on the use of handshake

between the master and the slave.

35. What is the main advantage of asynchronous bus?

The main advantage of asynchronous bus is that the handshake process eliminates the need

for synchronization of the sender and the receiver blocks, thus simplifying timing design.

36. What is a port?

The side opposite to bus signals in an I/O interface consists of data path with its associated

controls to transfer data between the interface and the I/O device. This side is called a port.

37. What is the difference between serial port and parallel port?

A parallel port transfers data in the form of a number of bits typically 8 or 16

simultaneously to or from the device.A serial port transmits and receives data one bit at a time.

38. What is a bridge?

A bridge is an interconnection circuit between two buses. It translates the signals and

protocols of one bus into those of the other.

39. Define SCSI.

SCSI stands for Small Computer System Interface. It refers to a standard bus defined by

ANSI under designation X3.131.

40. What are the different categories of SCSI bus signals?

SCSI bus signals are classified as,

1. Data signal

2. Phase signal

3. Information signal

4. Handshake

5. Direction of transfer.

41. What are the objectives of USB?

The objectives of USB are as follows:

1. Provide a simple, low cost and easy to use interconnection system.

2. Enhance user convenience through a ‗plug–and-play‘ mode operation.


42. What is an isochronous data stream?

An isochronous data stream means that the successive events are separated by equal

periods of time.

43. What is a hub?

A hub is the intermediate control point between the host and the I/O device.


UNIT-5

MEMORY ORGANIZATION

1. Define Memory Hierarchy.

It is to obtain the highest possible access speed while minimizing the total cost of the

memory system

2. What is Main memory?

The memory unit that communicates with directly with CPU is called main memory.

o Not enough storage space.

3. Define Auxiliary memory

Devices that provide backup storage are called auxiliary memory.

o Most common are magnetic disks and tape drives.

o Used to store system programs, large data files, backup data

o Not urgently needed data are stored here.

4. List out the important characteristics of storage devices.

o Access mode

o Access time

o Transfer rate

o Capacity

o Cost.

5. Define RAM: integrated circuit chips (Static or Dynamic)

o SRAM consists of flip flops as storage media. Stored data remains valid as long as power

is applied to the unit

o DRAM stores data as form of electric charges in small capacitors. Capacitors are

provided by CMOS transistors. Needs refreshing periodically as charges on small capacitor

discharge soon (need electronic control unit for that).

o DRAM compared to SRAM offer reduced power consumption and larger capacity. But

SRAM are faster.

6. Define ROM

ROM is different type of main memories. Used to store programs and data that does not change at

all (programs, tables, etc.)

7. What is a RAM chip?

It consists of a number of address pins, bidirectional data pins, and some control pins.


8. Draw the Typical RAM chip

9. Draw the Typical ROM chip

10. Define ASSOCIATIVE MEMORY:

1. Accessed by the content of the data rather than by an address.

2. Also called Content Addressable Memory (CAM)

11. Define Temporal Locality

The information which will be used in near future is likely to be in use already( e.g. Reuse

of information in loops)

12. Define Spatial Locality

If a word is accessed, adjacent(near) words are likely accessed soon (e.g. Related data

items (arrays) are usually stored together;instructions are executed sequentially)

13. What is Cache?

Cache is a fast small capacity memory that should hold those information which are most

likely to be accessed.

14. Define Access time

o Average time needed to reach storage location and obtain contents.

Access time = seek time + transfer time


15. Define Seek time:

o Transfer time: time required to transfer data to-from device.

16. Define Transfer rate

o The number of characters or words the device can transfer in one second.

17. Write notes on MAGNETIC DISKS.

1. Circular plate constructed of metal or plastic coated with magnetized material.

2. Both sides of disks are used and severatemsl sysl disks may be stacked with read-write

heads available for each surface.

3. All disks rotate together at high speed

4. Bits are stored in tracks which are concentric circles

5. Tracks are divided into sections called sectors

18. Write notes on MAGNETIC TAPES

1. Strip of plastic coated with magnetic recording material.

2. Bits are recorded as magnetic spots along several parallel tracks(7 to 9 tracks to form

character with parity).

3. Read-write heads are positioned on each track.

4. Magnetic tape units can be started stopped, forward moved, or reverse moved or rewound.

5. Data are recorded in records (number of characters) followed by gaps between record for

synchronization.

6. At start and end of each record there is ID bit patterns.

7. Records are identified by reading ID bit patterns.

19. Define Associative Memory

1. Accessed by the content of the data rather than by an address. Also called Content

Addressable Memory (CAM).

2. When word is written to CAM, no address is needed; next available unused storage

location is located. When word is read from CAM, the content of word or part of it is

specified, the memory locates all words which give match and marks them for reading.

3. Associative memories are expensive and used for application where time search is critical.

20. "Cache Memory system Performance"

Hit Ratio : "% of memory accesses satisfied by Cache memory system"

21. "Mapping Function: Associative Mapping"

Any block location in Cache can store any block in memory

o Most flexible

Mapping Table is implemented in an associative memory

o Fast, very Expensive

Mapping Table

o Stores both address and the content of the memory word.


22."Mapping Function: Direct Mapping"

1. Associative memories are expensive compared to RAMs

2. Each memory block has only one place to load in Cache

3. Mapping Table is made of RAM instead of CAM

23. List out the Cache Write policies.

Write Through and Write-Back (Copy-Back)

24. Define Write Through

Memory is always updated

When writing into memory

o If Hit, then both cache and memory is written in parallel

o If Miss, then memory is written

o For a read miss, missing block may be overloaded onto a cache block

Slow as memory is always accessed

25. Define Write-Back (Copy-Back)

When writing into memory

o If Hit, only Cache is written

o If Miss, missing block is brought to cache and write into Cache

26. What is Associative Memory?

The time required to find an item stored in memory can be reduced considerably if stored

data can be identified for access by the content of the data itself rather than by an address.

27. Define Locality of reference Analysis of a large number of typical programs has shown that the references to memory at

any given interval of time tend to be confined within a few localized areas in memory. This

phenomenon is known as the property of locality of reference.

28. Define Hit ratio The performance of cache memory is frequently measured in terms of a quantity called hit ratio.

29. List out the Three types of mapping procedures are of practical interest when considering

the organization of cache memory. 1. Direct mapping

2. Associative mapping

3. Set-associative mapping

30. What is Direct mapping?

Maps each block of main memory into only one possible cache line.

31. Define Associative mapping:

Associative mapping overcomes the disadvantage of direct mapping by permitting each

main memory block to be loaded into any line of the cache


32. Define Set associative mapping:

Set associative mapping is a compromise that exhibits the strengths of both the direct and

associative approaches while reducing their disadvantages.

33. How Cache is initialized?

The cache is initialized when power is applied to the computer or when the main memory

is loaded with a complete set of programs from auxiliary memory. After initialization the cache is

considered to be empty, but in effect it contains some non-valid data. It is customary to valid bit

include with each word in cache a valid bit to indicate whether or not the word contains valid data.

34. List out the Goals of a replacement policy.

The goal of a replacement policy is to try to remove the page least likely to be referenced in

the immediate future. Two of the most common replacement algorithms used is the first-in

first-out (FIFO) and the least recently used (LRU). The FIFO algorithm selects for replacement

the page that has been in memory the longest time. Each time a page is loaded into memory, its

identification number is pushed into a FIFO stack.

35. Give the most commonly used replacement algorithms.

The first-in first-out (FIFO) and the least recently used (LRU).

36. List out the basic components of a memory management unit .

1. A facility for dynamic storage relocation that maps logical memory references into physical

memory addresses

2. A provision for sharing common programs stored in memory by different users

3. Protection of information against unauthorized access between users and preventing users

from changing operating system functions

37. List out the access rights of interest that are used for protecting the programs residing in

memory.

1. Full read and write privileges

2. Read only (write protection)

3. Execute only (program protection)

4. System only (operating system protection)

Full read and write privileges are given to a program when it is executing its own

instructions.

Write protection is useful for sharing system programs such as utility programs and other

library routines. These system programs are stored in an area of memory where they can be

shared by many users. They can be read by all programs, but no writing is allowed. This

protects them from being changed by other programs.

38. What is meant by replacement algorithm?

When the cache is full and memory word that is not in the cache is requested, the cache control

hardware must decide which block should be removed to create space for the new block that

contains the referenced word. The algorithm used for this purpose is called replacement algorithm.


39. Define the term miss penalty.

In case of cache miss, extra time is needed to bring the desired information into a cache is called

the miss penalty.

40. What is meant by page frame?

An area in main memory that can hold one page is called a page frame.

41. What is meant by memory interleaving?

The memory cell array is organized in two banks.

Each bank can be accessed separately.

Consecutive words of a given block are stored in different banks.

Such interleaving of words allows simultaneous access to two words that are transferred.

42. What are pages?

All programs and data are composed of fixed length units called pages, each of which consists of a

block of words that occupies contiguous locations in the main memory.

43. Give the memory hierarchy.

Registers, Cache memory, Main Memory and Secondary Memory.

44. List the features of PROM

The features of PROM are,

They are programmed directly by the user.

It is faster.

Less expensive approach.

More flexible than ROM.

45. What is the disadvantage in EEPROM?

The only disadvantage of EEPROM is that different voltages are needed for erasing, writing and

reading the stored data.

46. Define ROM.

ROM (Read Only Memory) is a non – volatile memory which involves only reading of stored data.

47. Differentiate between static RAM and dynamic RAM.


48. What are the advantages of cache memory?

The advantages of cache memory are,

It reduces the memory access time.

It holds the currently active segments of a program and their data.

49. What is the use of secondary storage? Give examples.

The additional, cheaper, secondary storage is used when large amounts of data and many

programs have to be stored, particularly for information that is accessed in frequently.

Examples: Magnetic disks, Tapes and Optical disks.

50. What are the two registers involved in data transfer between the memory and the

processor?

The registers used to transfer data are,

MAR (Memory Address register)

MDR (Memory Data Register)

51. Define RAM

Memory in which any location can be reached in a short and fixed amount of time after specifying

its address is called as Random Access Memory (RAM).

computer architecure 2 marks question bank...

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