computer engineering 1502 advanced digital design professor donald chiarulli computer science dept....
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Computer Engineering 1502Advanced Digital Design
Professor Donald ChiarulliComputer Science Dept.5427 Sennott [email protected]
Course Assistants and Resources
Jason Bakos – TAOffice – 5426 Sennott [email protected]
Sam Dickerson –TAOffice – 271-I Benedum [email protected]
Web online forum – see Course web page www.cs.pitt.edu/~don/coe1502
Goals of this course
Learn tools and techniques of modern digital design for large scale digital systems
Complement your Computer Architecture Course (CoE 1541) with actual design experience for the processor covered in that course.
PREREQUISITE – CoE 0501 CO-REQUISITE – CoE 1541
Pre/Co requisites are non-negotiable
Things to do today
1. Choose a lab partner (carefully)2. Read carefully, sign and return a copy of the course syllabus 3. Add your name and e-mail address to the electronic class roster
via the course web page.
Next class 1. Set up your account, make sure the tools work properly2. Each student will have a home directory, and your group will have
a shared directory (greek letters). Verify that you have proper access to this directory.
3. Proceed with the tools tutorial, make sure that you do the library
setup part on both accounts.
What’s expected of you
• Most of the work in this class is divided into a series of units that will be
combined into your first processor design
• A unit will begin with a lecture (approx 1 hour) at the beginning of class
• You will have one or two weeks to complete the unit depending on the
complexity
• Units will be checked individually by myself or the TA -- demonstrations are
required to receive credit for a unit
• Units not checked on the due date will be considered late with credit deducted
• Units more than one week late will receive no credit (but you will still have to do
them)
www.cs.pitt.edu/~don/coe1502
Grading
Two projects plus final exam
Project 1 – due at Midterm (approx 33%)• complete multicycle CPU with interrupt controller• graded as average of four units• completed in group of two
Project 2 – due at end of term, usually on day of final (approx 33%)• complete pipeline CPU with primary cache controller• graded as four units (CPU/cache/CPU testbench/cache
testbench)• project group of four students
Final Exam – Practical exam (approx 33%)• Design exam given in class• Must complete small design project in 2 hours• Completed individually
Units in Project 1
• ALU: design, verification and synthesis• CPU: Multi-cycle implementation of base instruction set• Exception handler: 1 external interrupt, 3 internal traps• Memory bus controller: interface to RAM on Wildfire FPGA board• Synthesis: Synthesis and test on Wildfire FPGA board
Project 2
Structured to emulate industrial design experience
• Work as project team of 4 students• Two students assigned as principle designers• Two students responsible of test and verification• Instructor or TA acts as project leader
Final Exam
This is a design class, the final exam will test how effectively you have learned to tools and techniques of digital design
You will be given the specification for a small device that you should be familiar with either from experiences in this or other classes
You will be given two hours to implement this device using the software tools you have used in the course
Grading will be based on completeness, functionality and quality of the design that you produce
Since this is the only individual grade you will receive in this class, it will weigh heavily in the computation of your course grade
Software Tools
HDL Designer Suite - Mentor Graphics IncFGPA Advantage - Design Entry ToolModelSim - Simulator
Xilinx - Design SynthesisFPGA place and Route tools
Design Flow
FPGA Advantage
VHDL
Place and Route
FPGAHardware
ModelSim
Design Entry Verification
XilinxLogic Synthesis
Logic Analyzer
Hardware platform:Field Programmable Gate Arrays
• Xilinx Virtex VP100 FPGA• 99K+ logic cells• 16MB x 64bit Ram• 64 bit channel logic analyzer interface• PCI bus host interface logic
“Wildfire” reconfigurable processing card
FPGA Structure
Target CPU ArchitectureMIPS R2000* organization**
32 x 32bit Registerfile
IntegerALU
Control Unit
DataCache
Inst.Cache
Memory Interface
• 3 address architecture• load/store machine• 32 x 32bit register file• three instruction formats• full version of the processor used in H+P text.• Intruction set reference on class web page
* modified version for this class.
** Floating Point registers and ALU not shown