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Computer Interfacing for Fourth Year Class Medical Control Engineering Branch.

This course is intended to introduce hardware and software design techniques to solve the

issues that surround the operation of digital control and data acquisition systems through

interfacing signals coming from sensing devices to personal computers and

microcontrollers using analogue and digital circuit design techniques, while at the same

time using the same control platform to drive actuators to interact with working

environment by designing drive electronic circuits suitable to the implemented actuators

and using electrical isolation techniques where necessary.

Course Loading:

o 1 lecture each week (two hours lecture).

o 1 tutorial session each week (one hour tutorial session).

o 1 lab demonstration every third week with lab homework.

o 1 Assignment due on the last day of 15 weeks course.

References:

o Kevin James,” PC interfacing and Data Acquisition”, 1st edition, Newnes,

2000, U.K.

o Steven E. Derenz,” Practical Interfacing in the Laboratory” 1st Edition,

Cambridge University Press, 2003, U.K.

o Jan Axelson, “Parallel port complete”, 4th

Edition, Lakeview Reseach inc.,

2000, USA.

University of Technology Control and System Engineering Department

Medical Engineering Branch

Computer Interfacing for Medical Engineering

4th Year Class

1st Semester

2016 / 2017

Lecture 1

2

Computer interfacing

To learn how to connect computers and microcontrollers to various physical sensors

and actuators.

Overall view: a typical data

acquisition and control system

Sensor Signal

conditioning A/D

Computer

D/A Power

Drive

circuit

Mechanical

device

Timer

Sample

&

Hold

Digital control

circuit

Pre-

Amplifier

Signal conditioning circuits

Op Amps and Analog Interfacing

Analog interfacing techniques

op-amps (v.5f) 6

Operational Amplifier choices (op

amp)

• Why use op amp?

• What kinds of inputs/outputs required?

• What frequency responses desired?

• What type of op amp suits the application?

(Bipolar , Bi-FET, MOS/CMOS)

Biasing

• {Biasing in electronics is the method of establishing predetermined voltages or currents at various points of an electronic circuit for the purpose of establishing proper operating conditions in electronic components},

op-amps (v.5f) 7

Direct Current (DC) amplifier

• Example: use power op amp (or transistor) to control

the DC motor operation.

• Need to maintain the output voltage at a certain level

for a long time.

• All DC (biased) levels must be designed accurately .

• Circuit design is more difficult.

op-amps (v.5f) 8

Op-

amp

DC

Sourc

e

Load:

DC

motor

Alternating Current (AC) amplifier • Example: Microphone

amplifier, signal is AC and

is changing at a certain

frequency range. Current

is alternating not stable.

• Use capacitors to connect

different stages, so no

need to consider biasing

problems.

op-amps (v.5f) 9

Op-

amp

AC

Sourc

e

Load

Each stage can have its

owe biasing level. A

capacitor is an isolator, so

the circuit is easier to be

designed.

Biased at

Vcc

Biased at

Vcc/2

Vcc/2=2.5V

Factors for choosing an

amplifier • Source DC or AC ?

– DC(static or slow changing input, without decoupling capacitors)

– AC(for fast changing input, use decoupling capacitors)

• Input range, biased : absolute min, max voltage

• Output range, biased : absolute min, max voltage

• Frequency: range, allowed attenuation in dB

• Noise tolerance

• Power – output current/output impedance.

• DC-direct current amplifier

• AC-alternating current amplifier

Op-

amp

DC

Source

Load

Op-

amp

AC

Source

Load

Input impedance (Rin) and

Output impedance (Rout)

• Why do we prefer High Rin and Low Rout?

• Because it is more efficient.

• To maximize Vin2 (input voltage driving stage 2)

Rout1must be made lower, Rin2 higher.

• Good choice: Rin1M or over, Rin 10

Stage1(sensor)

Vout1

Rout1

Stage

2

Rin2

Rout

1

Vout1 Rin2

Vin2=

Vout1*Rin2/(Rout1+Rin2)

Vin2

Is

equivalent

to

Meaning of power gain in dB

(Decibel)

• Vout=output

• Vin=input

• Voltage gain =Vout/Vin

• Power gain =(Vout)2/ (Vin)2

• Power gain in dB=10*log10(Power gain )

• =20* Log10|(Vout/Vin)|=20*Log10|G|,

• where G= Voltage gain

• When power gain=(Vout/Vin)2=1, voltage_gain=1,

power_gain is 0dB

• When power gain=(Vout/Vin)2=0.5,

voltage_gain=(0.5)1/2=0.707, power_gain is -3dB

Frequency-gain plot When power gain=(Vout/Vin)2=1, voltage_gain=1, power_gain is

0dB

When power gain=(Vout/Vin)2=0.5, voltage_gain=(0.5)1/2=0.707,

power_gain is -3dB

• An amplifier frequency-gain is important to understand

its chartered at different frequencies.

• Horizontal axis is frequency (log scale) in Hz,

• Vertical axis is gain in dB

Log

Frequency

Power

Gain (dB)

0dB

-3dB

Gain is -3dB

Power gain is 0.5 Gain is 0dB

Power gain is 1

Slope:

20

dB/decad

e

drop

One decade = one number is 10 times of the other number

14

Operational amplifiers (op-amps)

– ideal op-amps

– inverting amplifier

– non-inverting amplifier

– voltage follower

– current-to-voltage amplifier

– summing amplifier

– full-wave rectifier

– instrumental amplifier

Ideal Vs. realistic

op-amp

• Ideal Realistic Rin

• A= infinite 105->108

• Zin= infinite 106(bipolar input)

1012(FET input)

output offset exists

V0=A(V+-V-) V-

V+ +

_ 2

3

6 LM741

Inverting amplifier

• Gain(G) = -R2/R1

• For min. output offset, set R3 = R1 // R2

• Rin=R1

• Question:

– If R1=1K, R2=10K, find G and Rin

+

_

R2

R1

R3

V0 V1

Virtual-ground,V2

A Input

Output

Non-inverting amplifier

_ V0

V1

R1

R2

• Voltage Gain(G) 1 + (R2/R1)

• For min. offset output , set R1//R2=Rsource

• High input resistance

• Question:

– If R1=1K, R2=10K, find G and Rin

+

V2

A Input Output

Differential amplifier

• V0=(R2/R1)(V2-V1)

• Minimum output offset R1 //R2 =R3 //R4

_ V0

R2

+

R1 V1

R3 V2

R4

A Input Output

Exercise

• A temperature sensor has an offset of 100mV

(produces an output of 100mV at 0 °C-degrees

Celsius), and the gradient is 10 mV per °C. The

temperature to be measured is ranging from 0 to 50 °C.

• The required ADC input range is 0 to 9Volts.

• Given that the power supply is +/-9V, design a

differential amplifier for this application.

Voltage follower (Unit voltage gain,

high current gain, high input impedance)

• Gain=1,

• Rin=high

• For minimum output offset R=Rsource

_ V0=V1

V1 +

R

A

Current to voltage converter:

Application to photo detector – no loading

effect for the light detector

_ V0

I R

• V0=I R

• I should not be too large otherwise

offset voltage will be too high.

+

A

Photodiode

Light

detector

Summing amplifier

_ V0

R

+

• V0 = -{(V1/R1)+(V2/R2)+(V3/R3)}R

R1

R2

R3

I1

I1+I2+I3

V1

V2

V3

Inputs

Output

Integrator

Differentiator

Op-amp characteristics

• Input and output offset voltages

– It is affected by power supply variations,

temperature, and unequal resistance paths.

– Some op-amps have offset setting inputs.

– Unequal resistance paths and bias currents

on inverting and non-inverting inputs

• Temperature variations

Op-amp dynamic response

• Slew rate -- the maximum rate of output

change (V/us) for a large input step

change.

– A741 slew rate=0.5V/ s. Fast slew rate is

important in video circuits , fast data

acquisition etc.

• Gain bandwidth product

– higher gain --> lower frequency response

– lower gain --> higher frequency response

Common mode gain

• If the two inputs (V+,V-) are connected together

and is given Vc, output is found to be Vo.

– ideal differential amplifier only amplifies the voltage

difference between its two inputs, so Vo should be 0.

• But in practice it is not.

• This deficiency can be measured by the

• Common_mode_gain=Gc=Vo/Vc.

op-amps (v.5f)

Diagram of gain bandwidth product

•

Hz

op-amps (v.5f)

Instrumentaiton amplifier

To make a better DC amplifier from op-amps

Diagram of instrumentation amplifier

Applications: Bridge amplifiers, amplifiers in

medical measurement systems

Instrumentation amplifier • It has all the advantages of an amplifier.

• Gain(G)=V0/(V+-V-)

• =(R4/R3)[1+(2R2/R1)] (typically 10 to 1000)

• Even V+=V-= Vc , there is a slight output

because of the Common Mode

Gain=Gc=V0/Vc

• Therefore, V0= G(V+-V-)+GcVc

• To measure this imperfection, Common Mode

rejection ratio (CMRR)=G/Gc (typically 103 to

107, or 60 to 140 dB)is used , the bigger the

better.

Comparing amplifiers

• Op Inv. Noninv. Diff. Instu.

• Amp Amp Amp Amp Amp

• High Rin Yes No Yes No Yes

• Diff’tial Yes No No Yes Yes

• input

• Defined No Yes Yes Yes Yes

• gain

op-amps (v.5f) 32

Operational amplifier selection

techniques and keywords • National semiconductor is the main manufacturer: See

http://www.national.com/appinfo/milaero/analog/highp.html

• General Purpose: LM741*

• High Slew Rate:50V/ ms --> 2000V/ ms (how fast the output can be changed)

• Follower (high speed):50MHz

• Low Supply Current: 1.5mA --> 20 µA/Amp

• Low offset voltage: 100 µV

• Low Noise

• Low Input Bias Current: 50pA -->10pA

• High Power : 0.2A --> 2A

• Low Drift: 2.5 mV/ _C --> 1.0 mV/ _C

• Dual/Quad

• High Power Bandwidth High Power Bandwidth : 300KHz - 230Mhz

Active filters

using op-amps

• Applications: accept or reject certain

signals with specific frequencies. High-

pass, low-pass, band-pass etc. E.g.

– reject noise

– extract signal after demodulation

– reject unwanted side effect signals

Types

• 1: Low pass

• 2: High pass

• 3: Band pass

• 4: Band stop (notch)

definition of power gain in decibel

(dB)

• Output power is P2, input power is P1

• Power Gain in dB=10 log10 (P2/P1)

• Or, output voltage is V2, input voltage is V1

• Assume load R is the same, power=V2/R

• Power Gain in dB=10 log10 (V22/ V1

2)

• Power Gain in dB=20 log10 |(V1/ V2)|

• =20 log10 |G|, where G=voltage gain

Time domain vs. frequency

domain

• Time domain: we talk about voltage

gain against time

• Frequency domain: we talk about the

voltage gain against frequency.

Time :(Seconds, usually linear scale)

Voltage

Frequency (Hz)

(can use log scale)

Power

Gain (dB)

Vpp=Peak-to-Peak voltage

+1V

0

-1V

0dB

-3dB

Time domain signal plot

Frequency domain signal plot

Important terms for filters:

• Pass band-- range of frequency that are

passed unfiltered

• Stop band -- range of frequency that are

rejected.

• Corner frequency -- where amplitude

dropped by (0.5)1/2=0.707

• I.e. in dB: 20*log(0.707) = -3dB

• Settling time -- time required to rise

within 10% of the final value after a step

input.

Low pass filter

• Only low frequency signal can pass

• one-pole: attenuates slower 20dB/decade

• two-pole: attenuates faster 40dB/decade

• Applications:

– remove high freq. Noise,

– remove high freq. before sampling to avoid

aliasing noise

Diagram for low-pass one pole filter,

Let R2/R1=1, Gain

G(f) in dB

3dB

fc Freq.

20 dB/decade

drop 2

12

1

/)(

cf

f

RRfG

•

CRfc

22

1

Corner frequency fc,

Formula

1

1

1

1since,

1

1||

1

2

1Put

2

2

2

1

2

1

//

2

1 definitionby ,

//Gain Voltage

2

1 where,

1

1|| proof To Frequency.

221

2

1

2

2

21

2

1

2

1

2

22

1

2

1

0

aja

f

fR

RG

f

fjR

RG

CRf

fCj

fCj

fCjRR

fCjR

R

RXG

fCjX

R

RXG

CRf

f

fR

R

V

VGf

c

c

c

c

cc

c

c

Low pass, one pole filter formulas

Let R2/R1=1K

• Corner frequency= fc=1/(2R2C)

• The gain drops 6dB/octave or 20

dB/decade

2

12

1

/)(

cf

f

RRfG

Diagram for Low-pass two-pole filter,

for simplicity Let R3/(R2+R1)=1 Gain

G(f) in dB

6dB

fc Freq.

40 dB/decade

drop 2

123

1

)/()(

cf

f

RRRfG

Where fc=(R1//R2)/2 C1 =(2 R3C2)-1

Low-pass two-pole filter formulas

• Corner frequency=fc

• fc=(R1//R2)/2 C1 =(2 R3C2)-1 when gain

G drops at -6dB.

• G is dropping at 40dB/decade

op-amps (v.5f)

Plotting the comparison of the low

pass filters (one-pole, two-pole)

40dB/decade

Slope more steep

20dB/decade

Slope less steep

High pass filter

• Only high frequency signal can pass

• One-pole: attenuates slower 20dB/decade

• Two-pole: attenuates faster 40dB/decade

• Applications:

– Remove low freq. Noise (50Hz main)

– Remove DC offset drift.

Diagram for high-pass one-pole filter

For simplicity let R1=R2, R3=R2 // R1

Gain G(f) in dB

3dB

Freq.

20 dB/decade

drop

high freq. Cutoff

unintentionally

Created

by

Op-amp

fc CRf

f

f

f

f

fG

c

c

c

1

2

2

1 where

,

1

)(

High-pass one-pole filter

formulas

• Corner frequency= fc=1/{2 (R1C)}

• At low f , |Glow_freq|=f/fc;

• at high f , | Ghigh_freq |=R2/R11

• Since op-amp has a certain gain-bandwidth, so at high

frequency the gain drops. So all op-amp high-pass filters are actually band-pass.

CRf

f

f

f

f

fG

c

c

c

1

2

2

1 where

,

1

)(

op-amps (v.5f) 48

high pass one pole filter

•

Band pass filter

• Passes a frequency band of signal.

Band-pass Filter formulas

• Passes a narrow band of frequencies and

rejects all others.

• High Q,Fc1=(4 RC)-1

• Low Q, Fc2=( RC)-1

Voltage

Gain in dB

frequency

Band stop (notch) filter

• Suppresses a narrow frequency band of

signal

Sample and hold amplifier

• For a fast changing signal, if you want to know

the voltage level of a snap shot (e.g. using a

slow AD converter to view a short pulse), you

need a sample and hold device, e.g. AD582,

AD389 etc.

• At Sample(S), V0=V1; at Hold(H) the output is

held at the level just before switching to H. It is

like taking a photograph of a signal.

• Some AD converter has this circuit incorporated

inside.

Diagram for Sample and hold amplifier, from [1]

Sample: sampling

Hold: When the switch is at

H, Vo keeps unchanged for

a long time. So the Analog–

to-digital converter ADC can

have more time for data

conversion

Hold

Slight

droop

may

occur



Computer Interfacing Techniques for Fourth year

Class Medical Engineering

1st Semester

2016 / 2017

Lecture 3

Analog to Digital Conversion

• ADC Essentials

• A/D Conversion Techniques

• Interfacing the ADC to the IBM PC

• DAS (Data Acquisition Systems)

• How to select and use an ADC

• A low cost DAS for the IBM PC

Why ADC ?

• Digital Signal Processing is more popular – Easy to implement, modify, … – Low cost

• Data from real world are typically Analog • Needs conversion system

– from raw measurements to digital data – Consists of

• Amplifier, Filters • Sample and Hold Circuit, Multiplexer • ADC

ADC Essentials

• Basic I/O Relationship

– ADC is Rationing System

• x = Analog input /

Reference

– Fraction: 0 ~ 1

• n bits ADC

– Number of discrete output level : 2n

– Quantum

• LSB size

• Q = LSB = FS / 2n

• Quantization Error

– 1/2 LSB

– Reduced by increasing n

Converter Errors • Offset Error

• Gain Error

• Can be eliminated by initial adjustments

• Integral Linearity Error

• Differential Linearity Error

• Nonlinear Error

– Hard to remove

Terminologies

• Converter Resolution

– The smallest change required in the analog input of an ADC to change its output code by one level

• Converter Accuracy

– The difference between the actual input voltage and the full-scale weighted equivalent of the binary output code

– Maximum sum of all converter errors including quantization error

• Conversion Time

– Required time (tc) before the converter can provide valid output data

• Converter Throughput Rate

– The number of times the input signal can be sampled maintaining full accuracy

– Inverse of the total time required for one successful conversion

– Inverse of Conversion time if No S/H(Sample and Hold) circuit is used

More on Conversion Time

• Input voltage change during the conversion process introduces an undesirable uncertainty

• Full conversion accuracy is realized only if this uncertainty is kept low below the converter’s resolution

– Rate of Change x tc resolution

–

• Example

– 8-bit ADC

– Conversion Time: 100sec

– Sinusoidal input

•

• Rate of change

• Let FS = 2A

– Limited to Low frequency of 12.4 Hz

• Few Applications

max( )2n c

dV FS

dt t

sin(2 )iv A ft

2 cos(2 ) 2idv fA ft fAdt

22

2

112.4

2

n

c

n

c

AfA

t

f Hzt

S/H increase Performance

• S/H (Sample and Hold)

– Analog circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversion

– Aperture time (ta) • Time delay occurs in

S/H circuits between the time the hold command is received and the instant the actual transition to the hold mode takes place

• Typically, few nsec

• Example

– 20 nsec aperture time

•

• Reasonably good for 100sec converter

162.17

2n a

f KHzt

Analog Input Signal

• Typically, Differential or Single-ended input signal of a single polarity

– Typical Input Range • 0 ~ 10V and 0 ~ 5V

– If Actual input signal does not span Full Input range • Some of the converter output

code never used

• Waste of converter dynamic range

• Greater relative effects of the converter errors on output

• Matching input signal and input range

– Prescaling input signal using OP Amp

• In a final stage of preconditioning circuit

– By proportionally scaling down the reference signal

• If reference signal is adjustable

Converting bipolar to unipolar

• Using unipolar converter when input signal is bipolar

– Scaling down the input – Adding an offset

• Bipolar Converter

– If polarity information in output is desired

– Bipolar input range • Typically, 0 ~ 5V

– Bipolar Output • 2’s Complement • Offset Binary • Sign Magnitude

• Input signal is scaled and an offset is added

scaled

Add

offset

Control Signals

• Start

– From CPU

– Initiate the conversion process

• BUSY / EOC

– To CPU

– Conversion is in progress

• 0=Busy: In progress

• 1=EOC: End of Conversion

• HBE / LBE

– From CPU

– To read Output word after EOC

• HBE

– High Byte Enable

• LBE

– Low Byte Enable

A/D Conversion Techniques

• Counter or Tracking ADC • Successive Approximation ADC

– Most Commonly Used

• Dual Slop Integrating ADC • Voltage to Frequency ADC • Parallel or Flash ADC

– Fast Conversion

• Software Implementation • Shaft Encoder

Counter Type ADC

• Block diagram

• Waveform

• Operation – Reset and Start Counter – DAC convert Digital output

of Counter to Analog signal – Compare Analog input and

Output of DAC • Vi < VDAC

– Continue counting

• Vi = VDAC

– Stop counting

– Digital Output = Output of Counter

• Disadvantage – Conversion time is varied

• 2n Clock Period for Full Scale input

Chap 0 14

Tracking Type ADC

• Tracking or Servo Type

– Using Up/Down Counter to track input signal continuously

• For slow varying input

• Can be used as S/H circuit

– By stopping desired instant

– Digital Output

– Long Hold Time

• Disabling UP (Down) control, Converter generate

– Minimum (Maximum) value reached by input signal over a given period

Successive Approximation ADC

• Most Commonly used in medium to high speed Converters

• Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved

• SAR(Successive Approximation Register) holds the current binary value

• Block Diagram

Successive Approximation ADC

• Circuit waveform

• Logic Flow

• Conversion Time

– n clock for n-bit ADC

– Fixed conversion time

• Serial Output is easily generated

– Bit decision are made in serial order

Dual Slope Integrating ADC • Operation

– Integrate

– Reset and integrate

– Thus

–

• Applications

– DPM(Digital Panel Meter), DMM(Digital Multimeter), …

• Excellent Noise Rejection

– High frequency noise cancelled out by integration

– Proper T1 eliminates line noise

– Easy to obtain good resolution

• Low Speed

– If T1 = 60Hz, converter throughput rate < 30 samples/s

1

0

T

iv dt2

0

t

rV dt1 ( ) 2i AVG rTv t V

2( )

1

i AVG r

tv V

T

Voltage to Frequency ADC

• VFC (Voltage to Frequency Converter)

– Convert analog input voltage to train of pulses

• Counter

– Generates Digital output by counting pulses over a fixed interval of time

• Low Speed

• Good Noise Immunity

• High resolution

– For slow varying signal

– With long conversion time

• Applicable to remote data sensing in noisy environments

– Digital transmission over a long distance

Parallel or Flash ADC

• Very High speed conversion

– Up to 100MHz for 8 bit resolution

– Video, Radar, Digital Oscilloscope

• Single Step Conversion

– 2n –1 comparator

– Precision Resistive Network

– Encoder

• Resolution is limited

– Large number of comparator in IC

Software Implementation

• Implementation with software using microprocessor

– Counting

– Shifting

– Inverting

– Code Conversion

• Limited Practical Use

– Availability of Good performance with very reasonable Cost

Shaft Encoder

• Elctromechanical ADC

– Convert shaft angle to digital output

• Encoding

– Optical or Magnetic Sensor

• Applications

– Machine tools, Industrial robotics, Numerical control

• Binary Encoder

– Misalignment of mechanism causes large error

• Ex: 011 111 (180deg)

• Gray Encoder

– Misalignment causes 1 LSB error

Interfacing the ADC to the IBM PC

• Interface Operations

– Most-recent-data Scheme

• At end of conversion it updates an output FIFO

• Automatically start new conversion

• CPU read FIFO to acquire most recent data

– Start-and-wait Scheme

• CPU initiate conversion every time it needs new data

• CPU check EOC until conversion is finished

– Using CPU Interrupt

• CPU initiate conversion every time it needs new data

• CPU can proceed to do other thing

• ADC interrupt CPU when conversion is complete

• CPU goes to ISR

– Information about the PIC 8259A is required .

Interface Software

• Memory Mapped Transfers

– ADC is assigned in Memory Space

• MRD, MWR signal

• MOV instruction

– More complex decoding logic

• I/O Mapped Transfers

– ADC is in I/O Space

• IOR, IOW signal

• IN, OUT instruction

– More Simple decoding logic

• DMA (Direct Memory Access)

– CPU release system bus by the request of DMA

– DMA controller carried out data transfer by generating the required addresses and control signals

– The system bus control reverts back to CPU when data transfer is finished

• DMA is useful

– High Speed

– High volume data transfer • Disk Drive interface

Interface Hardware

• Parallel Data Format

– Three state output buffer in ADC

– To Interface ADC

• CPU + Decoding logic

– To generate Chip Select signal

– To generate Start Signal

– To Check EOC signal

• Serial Data Format – Asynchronous Serial

transmission to send data over long distance to a monitoring station • UART is commonly used

• Interfacing 10 or 12 bit ADC – Transfer data in chunks of 8

bits one after another

DAS (Data Acquisition System)

• DAS performs the complete function of converting the raw outputs from one or more sensors into equivalent digital signals usable for further processing, control, or displaying applications

• Applications

– Simple monitoring of a single analog variable

– Control and Monitoring of hundreds of parameters in a nuclear plant

Single Channel System

• Transducer

– Generate signal of low amplitude, mixed with undesirable noise

• Amplifier, Filters

– Amplify

– Remove noise

– Linearize

• S/H (Sample and Hold)

– Reduce uncertainty error in the converted output when input changes are fast compared to the conversion time

– In Multi-channel system

• To hold a sample from one channel while multiplexer proceed to sample next one

• Simultaneous sampling of two signal

Sample and Hold Circuits

• Care in selecting hold capacitor Ch

– Low Value

• Reduces acquisition time

• Increase Droop

– High Value

• Minimize Droop

• Increase acquisition time

– Choose capacitor to get a best acquisition time while keeping the droop per conversion below 1 LSB

Commercially Available S/H

Multi-channel System

• Analog multiplexer and a ADC

– Low cost

• Local ADCs and digital multiplexer

– Higher sampling rate

How to select and use an ADC

• Range of commercially available ADCs

• Guidelines for using ADCs – Use the full input range of

the ADC

– Use a good source of reference signal

– Look out for fast input signal changes

– Keep analog and digital grounds separate

– Minimize interference and loading problem

Commercially available monolithic ADCs

Commercially available hybrid ADCs

A low cost DAS for the IBM PC

• Multi-channel system

– Less than $100

– ADC0816 from National Semiconductor

– Constant, repetitive rate

• 1000 samples/s

• Generating clock

– For starting ADC conversion

– For causing interrupt

– Make a pulse stream from TCLK with short pulses of duration = ½ x BCLK/4

• TCLK from 8253 Timer/Counter

– Wide pulse

ADC circuit for PC prototype

board SCSLCT

(Start Conversion SeLeCT)

: Latched trough port 30CH

SCSLCT = H

Selection of 30AH (/E10)

start conversion

SCSLCT = L

TCLK’ start conversion

INTSLCT

(INTerrupt SeLeCT)

: Latched trough port 30CH

INTSLCT = H

EOC cause IRQ2

INTSLCT = L

No Interrupt

CPU read Status register

(Port 309H) to check EOC

Status Register

• For polling TCLK and EOC signal

• Port 309H (/E9)

• Polling of EOC results in a low level after the data from ADC have been read

Throughput rate calculation

4.77MHz / 8

= 596KHz

Chap 0 37

Accuracy Calculation

• Better than 1% accuracy is ensured

• Actual accuracy with smooth input signal at room temperature will be better than 0.5%





1st Semester

2016 / 2017

Lecture 4

Digital to Analogue

Converters

3

Outline

• Purpose

• Types

• Performance Characteristics

• Applications

4

Purpose

• To convert digital values to analog voltages

• Performs inverse operation of the Analog-to-Digital Converter (ADC)

•

DAC Digital Value Analog Voltage

Reference Voltage

Value DigitalOUTV

5

DACs

• Types – Binary Weighted Resistor – R-2R Ladder – Multiplier DAC

• The reference voltage is constant and is set by the manufacturer.

– Non-Multiplier DAC • The reference voltage can be changed during operation.

• Characteristics – Comprised of switches, op-amps, and resistors – Provides resistance inversely proportion to significance of

bit

6

Binary Weighted Resistor Rf = R

8R 4R 2R R Vo

-VREF

iI

LSB

MSB

7

Binary Representation Rf = R

8R 4R 2R R Vo

-VREF

iI

Least Significant Bit

Most Significant Bit

8

Binary Representation

-VREF

Least Significant Bit

Most Significant Bit

CLEARED SET

( 1 1 1 1 )2 = ( 15 )10

9

Binary Weighted Resistor

Rf = R

8R 4R 2R R Vo

-VREF

iI

LSB

MSB

• “Weighted Resistors” based on bit

• Reduces current by a factor of 2 for each bit

10


• Result:

– Bi = Value of Bit i

R

B

R

B

R

B

R

BVI REF

842

0123

842

0123

BBBBVRIV REFfOUT

11


• More Generally:


– n = Number of Bits

ResolutionValue Digital

2 1

REF

in

iREFOUT

V

BVV

12

R-2R Ladder VREF

MSB

LSB

13

R-2R Ladder

• Same input switch setup as Binary Weighted Resistor DAC

• All bits pass through resistance of 2R

VREF MSB

LSB

14

R-2R Ladder

• The less significant the bit, the more resistors the signal must pass through before reaching the op-amp

• The current is divided by a factor of 2 at each node

LSB MSB

15

R-2R Ladder • The current is divided by a factor of 2 at each node

• Analysis for current from (001)2 shown below

0I

VREF

R R R R 2R

2R 2R 2R

Op-Amp input “Ground”

B0

2

0I

4

0I

8

0I

R

V

RRR

VI REFREF

32220

B1 B2

16

R-2R Ladder

• Result:


842

012 BBBV

R

RV REF

f

OUT

Rf

8423

012 BBB

R

VI REF

17

R-2R Ladder

• If Rf = 6R, VOUT is same as Binary Weighted:


12 in

iREFOUT

BVV

in

iREF B

R

VI

23

18

0I

VREF

R R R R 2R

2R 2R 2R

Op-Amp input “Ground”

B0 B2

0I

VREF

R-2R Ladder

• Example: – Input = (101)2 – VREF = 10 V – R = 2 Ω – Rf = 2R

mA67.13222

0

R

V

RRR

VI REFREF

mA04.128

00

III ampop

V17.4 fampopOUT RIV

19

Pros & Cons

Binary Weighted R-2R

Pros Easily understood

Only 2 resistor values

Easier implementation

Easier to manufacture

Faster response time

Cons

Limited to ~ 8 bits

Large # of resistors

Susceptible to noise

Expensive

Greater Error

More confusing analysis

20

Digital to Analog Converters

– Performance Specifications

– Common Applications

21


-Performance Specifications

• Resolution

• Reference Voltages

• Settling Time

• Linearity

• Speed

• Errors

22

• Resolution: is the amount of variance in output voltage for every change of the LSB in the digital input.

• How closely can we approximate the desired output signal(Higher Res. = finer detail=smaller Voltage divisions)

• A common DAC has a 8 - 12 bit Resolution



-Resolution

NLSB

VV

2Resolution Ref N = Number of bits

23



-Resolution

Better Resolution(3 bit) Poor Resolution(1 bit)

Vout

Desired Analog

signal

Approximate

output

2 V

olt

. L

evel

s

Digital Input 0 0

1

Digital Input

Vout

Desired Analog signal

Approximate

output

8 V

olt

. L

evel

s

000

001

010

011

100

101

110

111

110

101

100

011

010

001

000

24

• Reference Voltage: A specified voltage used to determine how each digital input will be assigned to each voltage division.

• Types:

– Non-multiplier: internal, fixed, and defined by manufacturer

– Multiplier: external, variable, user specified



-Reference Voltage

25



-Reference Voltage

Assume 2 bit DAC

Non-Multiplier: (Vref = C)

Digital Input

Multiplier: (Vref = Asin(wt))

0

Voltage

00

01 01

00

10 10

11

0

Voltage

Digital Input 00 00

01 01

10 10

11

26

• Settling Time: The time required for the input signal voltage to settle to the expected output voltage(within +/- VLSB).

• Any change in the input state will not be reflected in the output state immediately. There is a time lag, between the two events.



-Settling Time

27



-Settling Time

Analog Output Voltage

Expected

Voltage

+VLSB

-VLSB

Settling time Time

28

• Linearity: is the difference between the desired

analog output and the actual output over the

full range of expected values.

• Ideally, a DAC should produce a linear

relationship between a digital input and the

analog output, this is not always the case.



-Linearity

29



-Linearity

Linearity(Ideal Case)

Digital Input

Perfect Agreement

Desired/Approximate Output

Anal

og O

utp

ut

Volt

age

NON-Linearity(Real World)

Anal

og O

utp

ut

Volt

age

Digital Input

Desired Output

Miss-alignment

Approximate output

30

• Speed: Rate of conversion of a single digital input to its analog equivalent

• Conversion Rate

– Depends on clock speed of input signal

– Depends on settling time of converter



-Speed

31

• Non-linearity

– Differential

– Integral

• Gain

• Offset

• Non-monotonicity



-Errors

32

• Differential Non-Linearity: Difference in voltage step size from the previous DAC output (Ideally All DLN’s = 1 VLSB)



-Errors: Differential Non-Linearity

Digital Input

Ideal Output

Anal

og O

utp

ut

Volt

age

VLSB

2VLSB Diff. Non-Linearity = 2VLSB

33

• Integral Non-Linearity: Deviation of the actual DAC output from the ideal (Ideally all INL’s = 0)



-Errors: Integral Non-Linearity

Digital Input

Ideal Output

1VLSB Int. Non-Linearity = 1VLSB

Anal

og O

utp

ut

Volt

age

34

• Gain Error: Difference in slope of the ideal curve and the actual DAC output



-Errors: Gain

High Gain Error: Actual slope greater than ideal

Low Gain Error: Actual slope less than ideal

Digital Input

Desired/Ideal Output A

nal

og O

utp

ut

Volt

age

Low Gain

High Gain

35

• Offset Error: A constant voltage difference between the ideal DAC output and the actual. – The voltage axis intercept of the DAC output curve is

different than the ideal.



-Errors: Offset

Digital Input

Desired/Ideal Output Output Voltage

Positive Offset

Negative Offset

36

• Non-Monotonic: A decrease in output voltage with an increase in the digital input



-Errors: Non-Monotonicity

An

alog O

utp

ut

Volt

age

Digital Input

Desired Output

Monotonic

Non-Monotonic

37

• Generic use

• Circuit Components

• Digital Audio

• Function Generators/Oscilloscopes

• Motor Controllers


-Common Applications

38

• Used when a continuous analog signal is required.

• Signal from DAC can be smoothed by a Low pass filter



-Generic

0 bit

nth bit

n bit DAC 011010010101010100101 101010101011111100101 000010101010111110011 010101010101010101010 111010101011110011000 100101010101010001111

Digital Input

Filter

Piece-wise Continuous Output

Analog Continuous Output

39

• Voltage controlled Amplifier

– digital input, External Reference Voltage as control

• Digitally operated attenuator

– External Reference Voltage as input, digital control

• Programmable Filters

– Digitally controlled cutoff frequencies



-Circuit Components

40

• CD Players

• MP3 Players

• Digital Telephone/Answering Machines



-Digital Audio

1 2 3

http://configure.us.dell.com/dellstore/config.aspx?c=us&cs=19&l=en&oc=DDJ20M&s=dhs

41



-Function Generators

• Digital Oscilloscopes

– Digital Input

– Analog Ouput

• Signal Generators – Sine wave generation

– Square wave generation

– Triangle wave generation

– Random noise generation

1 2

http://www.electrorent.com/products/search/detail.aspx?Mfr=Lecroy+Corporation&MfrMod=LEC-LC584AL&Desc=1GHz+4CH+Digital+Scope

42

• Cruise Control

• Valve Control

• Motor Control



-Motor Controllers

1 2 3

43

END





1st Semester

2016 / 2017

Lecture 5

I/O Buses and Interfaces

“I/O bus” “Bus interface” “CPU bus”

or “System bus”

CPU-Memory-I/O Architecture

CPU I/O module

Memory

I/O device

I/O Buses and Interfaces

• There are many “standards” for I/O buses and interfaces

• Standards allow “open architectures”

– Many vendors can provide peripheral (I/O) devices for many different systems

• Most systems support several I/O buses and I/O interfaces

Examples

• Expansion buses or “slots”

• Disk interfaces

• External buses

• Communications interfaces

Expansion Buses

• These are “slots” on the motherboard • Examples

– ISA – Industry Standard Architecture – PCI – Personal Component Interconnect – EISA – Extended ISA – SIMM – Single Inline Memory Module – DIMM – Dual Inline Memory Module – MCA – Micro-Channel Architecture – AGP – Accelerated Graphics Port – VESA – Video Electronics Standards Association – PCMCIA – Personal Computer Memory Card International

Association (not just memory!)

3 ISA slots

5 PCI slots Pentium CPU 6 SIMM slots

2 DIMM slots

Disk Interfaces

• Examples – ATA – AT Attachment (named after IBM PC-AT)

– IDE – Integrated Drive Electronics (same as ATA)

– Enhanced IDE • Encompasses several older standards (ST-506/ST-412, IDE, ESDI,

ATA-2, ATA-3, ATA-4)

– Floppy disk

– SCSI – Small Computer Systems Interface

– ESDI – Enhanced Small Device Interface (mid-80s, obsolete)

– PCMCIA

External Buses

• Examples

– Parallel – sometimes called LPT (“line printer”)

– Serial – typically RS232C (sometimes RS422)

– PS/2 – for keyboards and mice

– USB – Universal Serial Bus

– IrDA – Infrared Device Attachment

– FireWire – new, very high speed, developed by IEEE

Communications Buses

• For connecting systems to systems

• Parallel/LPT – special purpose, e.g., using special software

(Laplink) to transfer data between systems

• Serial/RS232C – To connect a system to a voice-grade modem

• Ethernet – To connect a system to a high-speed network

A Computer System Consists of Multiple Buses

• An I/O module is an interface between the system bus and an I/O bus

• An I/O module may also interface an I/O bus to an I/O bus

Motherboard PCMCIA bus

CPU/system bus

PCMCIA bus

SCSI bus

RS232C bus

CPU I/O

module I/O

module Disk

Disk

PCMCIA slot

PCMCIA SCSI card

I/O module

PCMCIA serial card

I/O module

PCMCIA slot

Modem

Memory

A Detailed Look to Computer Busses

• The following interface buses and ports are common in computer systems

– ISA

– PCI

– AGP

– Serial

– Parallel

– SCSI

– Ethernet

– USB

ISA (1 of 3)

• Industry Standard Architecture

• History – Originally introduced in the IBM PC (1981) as an 8 bit

expansion slot • Runs at 8.3 MHz with data rate of 7.9 Mbytes/s

– 16-bit version introduced with the IBM PC/AT • Runs at 15.9 MHz with data rate of 15.9 Mbytes/s (?)

• Sometimes just called the “AT bus”

– Today, all ISA slots are 16 bit

• Configuration – Parallel, multi-drop

ISA (2 of 3)

• Used for… – Just about any peripheral (sound cards, disk drives, etc.)

• PnP ISA – In 1993, Intel and Microsoft introduced “PnP ISA”, for plug-

and-play ISA – Allows the operating system to configure expansion boards

automatically

• Form factor – Large connector in two segments – Smaller segment is the 8-bit interface (36 signals) – Larger segment is for the 16-bit expansion (62 signals) – 8-bit cards only use the smaller segment

ISA (3 of 3)

• Advancements – EISA

• Extended ISA

• Design by nine IBM competitors (AST, Compaq, Epson, HP, NEC, Olivetti, Tandy, WYSE, Zenith)

• Intended to compete with IBM’s MCA

• EISA is hardware compatible with ISA

– MCA • Micro Channel Architecture

• Introduced by IBM in 1987 as a replacement for the AT/ISA bus

– EISA and MCA have not been successful!

PCI (1 of 2)

• Peripheral Component Interconnect – Also called “Local Bus”

• History – Developed by Intel (1993)

– Very successful, widely used

– Much faster than ISA

– Gradually replacing ISA

• Configuration – Parallel, multi-drop

PCI (2 of 2)

• Used for… – Just about any peripheral

– Can support multiple high-performance devices

– Graphics, full-motion video, SCSI, local area networks, etc.

• Specifications – 64-bit bus capability

– Usually implemented as a 32-bit bus

– Runs at 33 MHz or 66 MHz

– At 33 MHz and a 32-bit bus, data rate is 133 Mbytes/s

AGP

• Accelerated Graphics Port

• History

– First appeared on Pentium II boards

– Developed just for graphics (especially 3D graphics)

• Configuration

– Parallel, point-to-point (only one AGP port / system)

• Specifications

– Data rates up to 532 Mbytes/s (that’s 4x PCI!)

Identifying ISA, PCI, & AGP slots

– Here’s an image to help in identifying slots

AGP slot

PCI slot

ISA slot

Back of

computer

Serial Interfaces

• On PCs, a “serial interface” implies a “COM port”, or “communications port”

– COM1, COM2, COM3, etc.

• COM ports conform to the RS-232C interface standard, so…

RS-232C

• History – Well-established standard, developed by the EIA

(Electronics Industry Association) in 1960s – Originally intended as an electrical specification to connect

computer terminals to modems

• Defines the interface between a DTE and a DCE – DTE = Data Terminal Equipment (terminal) – DCE = Data Communications Equipment (modem) – A “modem” is sometimes called a “data set” – A “terminal” is anything at the “terminus” of the

connection • VDT (video display terminal), computer, printer, etc.

“Traditional” Configuration

RS-232C RS-232C Telephone network

DTE DCE DCE DTE

RS-232C Specifications

• Data rate

– Maximum specified data rate is 20 Kbits/s with a maximum cable length of 15 meters

– However… • It is common to “push” an RS-232C interface to higher data rates

• Data rates to 1 Mbit/s can be achieved (with short cables!)

• Configuration

– Serial, point-to-point

Serial Data Transmission

• Two modes

– Asynchronous • The transmitting and receiving devices are not synchronized

• A clock signal is not transmitted along with the data

– Synchronous • The transmitting and receiving devices are synchronized

• A clock signal is transmitted along with the data (and is used to synchronized the devices)

– Most (but not all) RS-232C interfaces are asynchronous!

Asynchronous Data Transmission

• Data are transmitted on the TD (transmit data) line in packets, typically, of 7 or 8 bits

• Each packet is “framed” by a “start bit” (0) at the beginning, and a “stop bit” (1) at the end

• Optionally, a “parity bit” is inserted at the end of the packet (before the stop bit)

• The parity bit establishes either “even parity” or “odd parity” with the data bits in the packet – E.g., even parity: the total number of bits “equal to 1”

(including the data bits and the parity bit) is an “even number

1’s and 0’s in RS-232C

• A “1” is called a “mark”

• A “0” is called a “space”

• The idle state for an RS-232C line is a 1 (“mark”) – Idle state is called “marking the line”

• Voltages on an RS-232C line – Well… that’s another story, and it’s not really a

concern to us

Data Transmission Example

• Plot of the asynchronous RS-232C transmission of the ASCII character ‘a’ with odd parity:

0 1 0 0 0 0 1 1 0 1

Idle state

Stop bit

Start bit

Idle state

ASCII character ‘a’ • 7 bits • LSB first

Parity bit

time

TD

Exercise – RS-232C

• Plot the transmission of the ASCII character “X” over an asynchronous RS-232C channel with 7 data bits and even parity

Exercise – RS-232C

• Plot the transmission of the ASCII character “X” over an asynchronous RS-232C channel with 7 data bits and even parity

0 0 0 0 1 1 0 1 1 1

time

Answer

TD

RS-232C Connectors

• The original standard specified a 25-pin connector

• Today, a 9-pin connector is more common

• E.g., DB9P

Note: •P = “pin” •Sometimes called a “male” connector •The mate for this is a DP25S, or

“socket” connector – the “female”

RS-232C Connectors

DB25P

DB9P

DB25S

DB9S

Where is pin 1? Where are pins 2, 3, 4, etc.?

Pin 1

Pin 1 Pin 1

Pin 1

RS-232C Pin Numbers 1 2 3 4 5

9 8 7 6

DB9P

RS-232C Pins, Signals, Directions

DB25 1 2 3 4 5 6 7 8

20 22

Signal Name

CD Chassis Ground

TD Transmit Data

RD Receive Data

RTS Request To Send

CTS Clear To Send

DSR Data Set Ready

SG Signal Ground

DCD Data Carrier Detect

DTR Data Terminal Ready

RI Ring Indicator

Direction -

DTE DCE DTE DCE DTE DCE DTE DCE DTE DCE

- DTE DCE DTE DCE DTE DCE

DB9

2 3 7 8 6 5 1 4 9

Pin

Parallel Interfaces

• History – In the context of PCs, a “parallel interface” implies a

Centronics-compatible printer interface – Originally developed by printer company, Centronics – Introduced on the IBM PC (1981) as an LPT (“line printer”)

port – Improvements

• EPP (Enhanced Parallel Port), development by Intel, Xircom, Xenith • Enshrined in the standard IEEE-1284 (1994)

– “Standard Signaling Method for a Bi-directional Parallel Peripheral Interface for Personal Computers”

– Includes Centronics/LPT mode, EPP mode, and… – ECP mode (Enhanced Capability Port)

Parallel Printer Port Interfaces

• Also called LPT, has four modes of operation: 1. Standard Parallel Printer Port, controlled via three I/O ports starting

with address 278H, or 378H, or 3BCH. The first is called the data port (output), the second is called the control port (output), and the third is called the status port (input). Data rate about 150 KB/sec.

2. Bidirectional Printer Port, found on the IBM PS/2 models and modern compatibles. The data bus is bidirectional.

3. Enhance Parallel Printer Port (EPP), has a higher data rate than SPP and Bidirectional mode 9 up to 1MB/sec.).

4. Extended capabilities Printer Port (ECP) introduced by Hewlett-Packard, can Address more than one device.

1. • Configuration

– Parallel data transfer, point-to-point (except in ECP where multiple devices can be addressed)

Typical Printer Cable

DB25P (male) • Connects to PC

Centronics male • 36 pins • Connects to printer

Pinouts (for SPP)

Direc-

tion

out out out out out out out out out in in in in out in out out -

DB25

Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18-25

Centronix.

Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 36 19-30,

33,17,16

Signal

/Strobe Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 /Ack Busy PaperEnd SelectIn /AutoFd /Error /Init /Select Ground

Function

low pulse (>0.5 µs) to send LSB . . . . . . MSB Low pulse ack. (~5 µs) High for busy/offline/error High for out of paper High for printer selected Low to autofeed one line Low for Error Low pulse (>50 s) to init Low to select printer

-

Small Computer System Interface (SCSI) (1 of 2)

• History – Developed by Shugart Associates (1981)

– Originally called Shugart Associates Systems Interface (SASI, pronounced “sassi”)

– Scaled down version of IBM’s System 360 Selector Channel

– Became an ANSI standard in 1986

• Used for… – Disk drives, CD-ROM drives, tape drives, scanners, printers,

etc.

SCSI (2 of 2)

• Configuration – Parallel, daisy chain

– Requires terminator at end of chain

• Versions (data width, data rate) – SCSI-1, Narrow SCSI (8 bits, 5 MBps)

– SCSI-2 (8, bits 10 MBps)

– SCSI-3 (8, bits, 20 MBps)

– UltraWide SCSI (16 bits, 40 MBps)

– Ultra2 SCSI (8 bits 40 MBps)

– Wide Ultra2 SCSI (16 bits, 80 MBps)

SCSI Block Diagram

SCSI bus controller

I/O device

I/O device

I/O device

SCSI bus

System bus or

I/O bus SCSI port

Terminator

SCSI Connectors

Narrow SCSI

Fast SCSI

Fast Wide SCSI

Ultra SCSI

50 pins

50 pins

68 pins

80 pins

Putting it all together

ISA or PCI bus interface

Parallel interface

Serial interface

SCSI interface

LPT port

COM1 port

COM2 port

SCSI port

CPU/system bus

ISA or PCI bus

Ethernet Interfaces

• History

– In 1980, Xerox, Digital Equipment Corporation (DEC, now Compaq), and Intel published a specification for an “Ethernet” LAN (local area network)

– Now exists as a standard - IEEE 802.3 • Physical interface uses either coax cable with BNC connectors or

twisted pair cable with RJ-45 connectors (10Base-T)

– Fast Ethernet • Specified in IEEE 802.3u (100Base-TX)

Ethernet Interfaces

• Data Rate

– 10 Mbits/s for Ethernet (10Base-T) use CAT 3 cables

– 100 Mbits/s for Fast Ethernet (100Base-TX) use CAT 5 cables

– 1Gbits/s for ultra fast Ethernet (1000Base-TX) use CAT 6 cables

• Configuration

– Serial, multi-point (token ring or token bus)

Token Bus

Token Ring

Ethernet Adapter Example - PCI

RJ-45 connector

BNC connector PCI

bus interface

Addtron AEF-360TX

RJ-45 Pinouts Pin Signal Direction Function

1 TD+ Transmit data

2 TD- Transmit data

return

3 RD+ Receive data

4 - - -

5 - - -

6 RD- Receive data

return

7 - - -

8 - - -

1 8

• Use Shielded twisted pair cables (STP) in noisy environment. • Use Unshielded twisted pair cables (UTP) otherwise.

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