computer organization department of cse, sse mukka chapter 2: machine instructions and programs |...
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Computer Organization
Department of CSE, SSE Mukka
Chapter 2: Machine Instructions and Programs
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Memory Location and Addresses In memory of computer, there are
Number and character operands Instructions
Memory consists of Millions of storage cells,
Each cell can hold a bit ( 0 or 1 ) of information So each bit can hold a very small amount of information
Memory is organized so that a group of n bits can be stored or retrieved in a single, basic operation Each group of n bits is referred to as word n is called as wordlength
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second word
first word
Memory words.
n bits
last word
i th word
•••
•••
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Contd… Range of word length of modern computers
16 to 64 bits Group of 8 bits referred to a byte
If the word length is 32 bits A single word can store a 32-bit 2’s complement
number Or Four ASCII characters
As shown in the figure
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Examples of encoded information in a 32-bit word.
(b) Four characters
charactercharactercharacter character
(a) A signed integer
Sign bit: for positive numbers for negative numbers
ASCIIASCIIASCIIASCII
32 bits
8 bits 8 bits 8 bits 8 bits
b31 b30 b1 b0
b31 0=
b31 1=
• • •
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Addresses Access to memory to store or retrieve a single
item of info ( either a byte or a word ) requires distinct names or addresses for each item location
normally used addresses => 0 to 2k -1 as addresses of successive memory locations The 2k addresses constitute address space of the
computer 24-bit address generates an address space of 224
locations = 16M locations 32-bit ?
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Byte Addressability A byte is always 8-bit Word length ranges from 16 to 64 bits. Impractical to assign distinct addresses to
individual bit locations Most practical? Byte-addressable memory Byte locations have addresses 0,1,2,.. If the word length of the machine is 32-bits,
then successive words are located at addresses ?
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Big-Endian and Little-Endian Assignments 2 ways byte addresses can be assigned across
words Big-endian when
Lower byte addresses for more significant bytes (leftmost bytes ) of the word.
Little-endian when Lower bytes addresses used for less significant
bytes (right most bytes ) of the word. In both cases 0,4,8 .. are taken as addresses
of successive words in the memory
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2k
4- 2k
3- 2k
2- 2k
1- 2k
4-2k
4-
0 1 2 3
4 5 6 7
0 0
4
2k
1- 2k
2- 2k
3- 2k
4-
3 2 1 0
7 6 5 4
Byte addressByte address
(a) Big-endian assignment (b) Little-endian assignment
4
Wordaddress
•••
•••
Byte and word addressing.
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Word Alignment Words are said to be aligned in memory if
they begin at a byte address that is a multiple of the number of bytes in a word Eg : if wordlength is 16bits, aligned words begin at
byte addresses 0,2,4,…. If word length is 32 bits, aligned words begin at
0,4,8 etc… If the words don’t begin at byte address that
is a multiple of no of bytes in the word, then words are said to have unaligned addresses
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Accessing numbers, characters and strings Number
By its word address as it usually occupies one word
Character By byte address
Strings They are of variable length Beginning of the string by giving the beginning byte
address which contains first character Successive bytes contains successive characters Termination?
Either by a special control character Or a separate memory word location/ register containing a
number indicating the string length
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Problems1. Given that a memory has 32-bit address & is
byte-addressable, what is the size of the memory(in bytes)?
2. Given that a memory has 24-bit address & is word-addressable with a word length of 32 bits, what is the size of the memory(in bytes)?
3. Given that a memory has 16-bit address and is byte addressable. Word length is 32 bits. How many words can we store in such a memory?
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Answers1. 4GB2. 64MB3. 16K words
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Memory Operations Both program instructions and data operands
are stored in memory To execute an instruction
Processor control circuits must cause the word(s) containing the instruction to be transferred from the memory to the processor
Operands and results must also be moved between memory and the processor
Two basic operations involving the memory Load ( or Read or Fetch ) Store ( or Write )
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Memory Operations – LOAD operation Load transfers a copy of the contents of a
specific memory location to the processor The memory contents remain unchanged To start a load operation
Processes sends the address of the desired location to memory
Request that its contents be read The memory reads the data and sends to the
processor
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Memory operations -Store operation Store operation transfers an item of
information from the processor to a specific memory location
Destroys the former contents of that memory location
Processor needs to send the address of the desired memory location and also the data to be written into that location
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Instructions and Instruction Sequencing Tasks that are carried out by a computer
consists of a sequence of small steps Eg., add two numbers, test for a particular
condition, read a character from keyboard, display a character on screen
A computer must have instructions capable of performing four types of operations Data transfers between the memory and the
processor registers Arithmetic and logic operations on data Program sequencing and control I/O transfers
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Register transfer notation Used to describe transfer of information from one
location in the computer to another Possible locations are memory locations, processor
registers, and registers in the I/O subsystem To identify a location
Symbolic name standing for its hardware binary address Eg., name of memory locations – LOC,A,VAR2 etc Name of registers – R0,R5 Name of I/O registers – DATAIN
Contents of a location denoted by placing square brackets around the name R1 [LOC] means contents of memory location LOC
are transferred into processor register R1 R3 [R1] + [R2] ?
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Assembly language notation Used to represent machine instructions and
programs Example
To perform the data transfer R1 [LOC] the statement is Move LOC,R1
Old contents of register R1 are overwritten but contents of LOC unchanged
R3 [R1] + [R2] is denoted by statement ?
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Basic Instruction Types A high level language program command C =
A + B adds the contents of variables A and B and stores the result in variable C After compilation, the three variable A,B and C are
assigned distinct locations in memory The contents of these locations represent the
value of the three variables The action is C [A] + [B]
Contents of A and B locations are fetched from memory and transferred into processor where the computation is performed
Result is then sent back to the location C
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Accomplish C=A+B using Single Machine Instruction The instruction contains memory addresses of 3
operands – A,B and C Add A,B,C A and B are source operands C is destination operand Add is the operation to be performed
Operation Source1,Source2, Destination If k bits are needed to specify memory address of
each operand In addition to the bits needed to denote Add operation
we need 3k bits more For a modern processor with 32-bit address space,a 3-
address instruction is too large to fit in one word for a reasonable wrodlength
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Accomplish C = A + B using two-address instructions Operation Source, Destination Eg., Add A,B which performs the operation B [A]
+ [B] When sum is calculated result is sent to memory
replacing original contents of location B We cannot use a single two-address instruction as
we don’t want to destroy the contents of A or B Solution?
Use a instruction which copies contents of one memory location to another
Move B,C performs the operation C [B] leaving contents of B unchanged
Actually it only “copies” not “moves” Final solution is
Move B,C Add A,C
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Accomplish C = A + B using one-address instructions Even two-address instructions will not fit into one
single word of memory Use one-address instruction
Second operand , whenever required, is present in a unique location
Eg., usage of accumulator, a processor register Add A
means Add the contents of memory location A to the contents of accumulator register and place the sum back into the accumulator
Load A Copies contents of memory location A into accumulator
Store A Copies contents of accumulator to memory location A
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Contd… Load A Add B Store C
Operand specified may be source or destination depending on the instruction
For load it is source, For store it is destination
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Accomplish C = A + B using one-address instructions, and General purpose registers Most modern computers have 32 General
Purpose Registers or more Only 5 bits sufficient to address 32 GPRs.
How? Registers are used to store data temporarily Since access time to registers is much less
than memory frequent access to memory is reduced hence enhancing speed
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Accomplish C = A + B using one-address instructions, and General purpose registers If Ri is a GPR
Load A,Ri Store Ri,A Add A,Ri are generalizations for the single-
accumulator case Data transfer instruction - Move
When we want to move from one place to another. A single instruction Move can be used in place
of Load and Store Move Source, Destination Move A, Ri is same as Load A,Ri Move Ri,A is same as Store Ri,A
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Contd If artihmetic operations are allowed only on
operands in processor registers then to achieve C = A + B Move A,Ri Move B,Rj Add Ri,Rj Move Rj,C
If one operand can be in memory but other must be in register then Move A,Ri Add B,Rj Move Rj,C
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Zero-Address instructions Locations of all operands defined implicitly Machines which store operands in a structure
called pushdown stack Instructions does not specify any memory
address
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Instruction execution and straight line sequencing
R0,C
B,R0A,R0
Movei + 8
Begin execution here Movei
ContentsAddress
C
B
A
the programData for
segmentprogram
3-instruction
Addi + 4
Figure 2.8. A program for C +
Assumptions
GPRs One addr insts Wordlength 32bits Byte addressable Full address in
Single word instruction The three insts at
i, i + 4, i + 8
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Instruction execution and straight line sequencing PC holds address of instruction to be executed
next To begin execution
place the address of first inst to be executed in PC Processor control circuits use info in PC to fetch
and execute instructions, one at a time, in order of increasing addresses
This is called as Straight-line sequencing During the execution of each instruction, PC is
incremented by 4
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Instruction execution and straight line sequencing Execution is two phase
Instruction Fetch Instruction is fetched from memory location whose
address in PC This instruction is placed in IR
Instruction Execute IR is examined to determine which operation is to be
performed Specified operation is then performed by processor Involves fetching operands from memory or processor
registers, performing arithmetic or logic operations, storing results in destination
At some point during this two-phase, the contents of PC is advanced to point to next instruction
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Branching Branch instruction load a new value to PC
than the address of next immediate instruction following the branch instruction
This new address is called branch target A conditional branch instruction causes
branch only if a specified condition is satisfiedEg., Branch>0 LOOP
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NUM n
NUM2
NUM1
R0,SUM
NUM n ,R0
NUM3,R0
NUM2,R0
NUM1,R0
Figure 2.9. A straight-line program for adding n numbers.
Add
Add
Move
SUM
i
Move
Add
i 4 n+
i 4 n 4-+
i 8+
i 4+
•••
•••
•••
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N,R1Move
NUM n
NUM2
NUM1
R0,SUM
R1
"Next" number to R0
Figure 2.10. Using a loop to add n numbers.
LOOP
Decrement
Move
LOOP
loopProgram
Determine address of"Next" number and add
N
SUM
n
R0Clear
Branch>0
•••
•••
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Assignment to be submitted on Thursday Express the following signed numbers in 2’s
complement notation and perform addition and subtraction. State whether overflow occurs or not
4-bit notation 2&3, 5 & -6, -7 & 6, -8 & -3, 7 & 4
5-bit notation 12 & 3, 7 & -7, -6 & 14, -10 & -4, 12 & 8
Represent the following numbers in 32-bit Big-endian and Little-endian memory organization 81234561 -81234561
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Indirection and pointers Indirect mode – the Effective address of the
operand is the contents of a register or memory location whose address appears in the instruction
The register of memory location that contains the address of an operand is called a pointer
Analogy of treasure hunt Instead of finding the treasure, we find the
address where we find the treasure By changing the contents of register R1 or location
A in the following figure, the same add instruction fetches different operands to add to register R0.
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R1
Add (R1),R0 Add (A),R0
Figure 2.11. Indirect addressing.
RegisterB B Operand
memoryMain
(a) Through a general-purpose register (b) Through a memory location
A BOperandB
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Clear R0
Contents
Move
Add
DecrementAdd
LOOP
Initialization
LOOP
Address
Figure 2.12. Use of indirect addressing in the program of Figure 2.10.
(R2),R0#4,R2R1
R0,SUM
MoveMove N,R1
#NUM1,R2
Branch>0
Indirect addressing logic for the program of adding n numbers using loop
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Operand1020
Figure 2.13. Indexed addressing.
Add 1000(R1),R2
R1
R1
Add 20(R1),R2
Operand1020
201000
20 = offset
20 = offset
10001000
(a) Offset is given as a constant
(b) Offset is in the index register
INDEXED ADDRESSING
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Figure 2.14. A list of students' marks.
Student 1
Student 2
Test 3
Test 2
Test 1
Student ID
Test 3
Test 2
Student ID
nN
LISTTest 1LIST + 4
LIST + 8
LIST + 12
LIST + 16
•••
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Move #LIST,R0
Add
Move
Add
12(R0),R3
LOOP
Figure 2.15. Indexed addressing used in accessing test scores in the list in Figure 2.14.
#16,R0
Clear R1
Clear R3
4(R0),R1
Clear R2
Add 8(R0),R2
N,R4
Add
Decrement R4
LOOP
Move R1,SUM1
Move R2,SUM2
Move R3,SUM3
Branch>0
Note: contents of R0, which is used as indexed register, are not changed when it is used in indexed addressing mode to access test scores.Contents of R0 change only in last Add instruction, to move from one student record to the next
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Indexed addressing contd… Several variations of the basic form of indexed
addressing provide efficient access to memory operands A second register may be used to contain the offset X,
called as based indexed addressing mode Denoted as ( Ri, Rj ) Effective address is the sum of contents of Ri and Rj Second register is called base register. Provides more flexibility to the user Eg., suppose, in the previous example, instead of only 3
items, each student record contain a large no of items, say k
We can replace the three Add instructions by a single instruction inside a second loop
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Indexed addressing contd… Problem The list of student marks shown in prev figure
2.14, is changed to contain j test scores for each student. Assume that there are n students. Write an assembly language program for computing the sums of the scores on each test and store these sums in the memory word locations at addresses SUM, SUM + 4, SUM + 8,…. The number of tests, j, is larger than the number of registers in the processor. Use two nested loops, the inner loop should accumulate the sum for a particular test, and the outer loop should run over the number of tests, j. assume that j is stored in memory location J.
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Solution
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Indexed addressing mode contd.. based indexed addressing mode with offset
Uses two registers plus a constant X( Ri, Rj ) - Effective address is the sum of the
constant X and the contents of registers Ri and Rj This mode implements 3-Dimensional array
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Relative addressing Till now for index mode, registers we used are general purpose
registers A useful variation of this is to use Program Counter PC instead of a
general purpose register X(PC) – to address a memory location that is X bytes away from the
location presently pointed to by the program counter Relative mode- the effective address is determined by the index mode
using the program counter in place of the general-purpose register Ri. MOST common use is to specify the target address in branch
instructions Eg., Branch>0 LOOP If branch condition is true, the program execution goes to branch
target location identified by name LOOP Can compute this location by specifying it as an offset from the
current value of the program counter. Since branch target address can be either before or after the branch
instruction, the offset is given as a signed number
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Example for relative addressing mode
Assume 4 instructions starting from LOOP are located at memory locations 1000,1004,1008 & 1012.
Updated contents at the time branch target address is generated is 1016. to branch to location LOOP(1000), the offset value needed is X = -16
Clear R0
Contents
Move
Add
DecrementAdd
LOOP
Initialization
LOOP
Address
(R2),R0#4,R2R1
R0,SUM
MoveMove N,R1
#NUM1,R2
Branch>0
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Additional modes Autoincrement and autodecrement mode –
useful for accessing data items in successive locations in the memory
Autoincrement mode – The effective address of the operand is the
contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to next element in the list
(Ri)+ The increment is 1 for byte-sized operands, 2 for 16-bit
operands and 4 for 32-bit operands. Usually size of operand is specified in the instruction
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R0Clear
R0,SUM
R1(R2)+,R0
Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Initialization
Move
LOOP AddDecrement
LOOP
#NUM1,R2N,R1Move
Move
Branch>0
Autoincrement addressing logic for the program of adding n numbers
using loop
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Autodecrement mode The contents of a register specified in the
instruction are first automatically decremented and are then used as the effective address of the operand
Denoted by –(Ri) Operands are accessed in descending address
order. The way the autoincrement and autodecrement
modes are specified in very useful when implementing an important data structure called a stack. Always we can use two instructions to perform the
functionality of autoincrement and autodecrement mode
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