computer organization [e & tc] solution manual
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Important Solved Examples
Example 2.2.3
Solution :
Example 2.2.4
Solution : (49)10 = (0110001)2
Example 2.2.5
Solution : (A43)16 = (0101001000011)2
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM(2 - 1)
2
Data Representation
and Arithmetic Algorithms
1 0 1 0 1 1 0 1
0 1 0 1 0 0 1 0
Number
NOT operation
1's complement of number
0 1 1 0 0 0 1
1 0 0 1 1 1 0
Number
NOT operation
1's complement of number
Number
NOT operation
1's complement of number
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
2 Arithmetic Unit
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Example 2.2.6
Solution :
Example 2.2.7
Solution :
Example 2.2.8
Solution :
Example 2.2.11
Solution : We have
( )0111002
( )2810
and
( )01111 2 ( )15 10
( )10000 2 1's complement of 15
( )100011 2 1's complement of 28
Computer Organization 2 - 2 Arithmetic Unit
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0 1 1 1
0 1 0 0
0 0 1 1
0011
1
10100101
Number
1's complement
Add 1
2's complement
+
0 1 0 01 1 0
1
Binary equivalent of (50)10
1's complement of (50)10
Add 1
2's complement of (50)10
1011001+
1 0 0 1 1 1 0
Carry1
1 0 0 11 1 0
1
1
Number
1's complement
Add 1
2's complement
1001010
+
0 1 0 1 0 1 0
Carry
0
1
1
0
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Addition of (– 28) and (– 15) :
Sign-extension
+
1 1 0 0 0 1 1
Sign-extension 1 1 1 0 0 0 0
Carry 1 1 0 1 0 0 1 1
1 Add end-around carry
1 0 1 0 1 0 0 (– 43) Result is in 1'scomplement form
Verification : 1 0 1 0 1 0 0
0 1 0 1 0 1 1 ( )43 10
Note
Here, the magnitude of greater number is 5-bit; however, the magnitude of the result
is 6-bit. Therefore, the numbers are sign-extended to 7-bits.
For proper result we suggest to use 1 sign-bit extension to the number having greater
magnitude and represent the number having smaller magnitude with extended
number of bits.
Example 2.5.8
Solution :
Multiplication :
Computer Organization 2 - 3 Arithmetic Unit
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1 1 1 10 Multiplicand
1
10100
00100 1's complement of multiplicand
Add 1
2's complement of multiplicand
+
Multiplicand =
Multiplier =
Recoded multiplier =
(11011) = (– 5)
(0 0 1 1 0 ) = (3)
0 + 1 0 – 1
2 10
2 10
Implied zero
1
0
00000
0
+
0
1 0 1 1
– 10+ 1×
1010 0 0
0 0
1 1 1 0 1 1
0 0 0 0 0
1 1 1 1 0 100
+
+
(– 15)10
2's complement of multiplicand
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Note Shaded region indicate sign extension.
Example 2.5.9
Solution :
Multiplication :
Note Shaded region indicate sign extension
Example 2.5.10
Solution :
Computer Organization 2 - 4 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
1
0
1 0 1 1
001
+
0
1
0 0 1 0 1
Multiplicand
1's complement of multiplicand
Add 1
2's complement of multiplicand
Multiplicand =
Multiplier =
11011 (– 5)
0 0 1 1 1 0
Implied zero(7)
Recoded multiplier = 0 +1 0 0 – 1
1
+1
1 0 1 1
–1000
1
0 0 0 0
×
0 0 0 0 0 0 1 0
0000
0 0 0 0 0 0 0
1 1 1 0 1 1
0 0 0 0 0
1 1 1 0 1 1 1 0 1
+
+
+
2's complement of multiplicand
(– 35)
+
1
0
0 1 0 1
0101
+ 1
1 0 0 1 1
Multiplicand
1's complement of multiplicand
Add 1
2's complement of multiplicand
Multiplicand =
Multiplier =
Recoded multiplier =
(+13) = (0 1 1 0 1)
(–5) = (1 1 0 1 1)
1 1 0 1 1 0
0 – 1 +1 0 – 1
10 2
10 2 Implied zero
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Multiplication :
Note Shaded region indicate sign extension
Example 2.5.11
Solution :
Example 2.6.7
Solution :
+ 13 = 0 1 1 0 1– 6 = 1 0 1 0 2's complement of 6
Bit pair recoding of – 6
Computer Organization 2 - 5 Arithmetic Unit
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1
– 1
0 1 0 1
– 10+ 10
1 1 1 1 1 0 0 1 1
00000000
0 0 0 1 1 0 1
1 1 0 0 1 1
0 0 0 0 0
1 1 1 0 1 1 1 1 1 1
2's complement of multiplicand
2's complement of multiplicand
(– 65)
+
+
+
+
×
1
0
0 1 1 1
–100+1
Multiplier
Multiplicand
Recoded multiplier
Recoded multiplier
2's complement of – 13
(– 195)
11
0
0 0 1 1
–100+1
00 0 0 0 0 1 1 0 1
000000000
00 0 0 0 0 0 0
00 0 0 0 0 0
11 0 0 1 1
1 1 0 0 1 1 1 1 0 1
+
+
+
+
×
11 0 1Signextension
0 0
–1 –2
Implied 0 toright of LSB
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Multiplication
( 13) ( 6) = (1 0 1 1 0 0 1 0)2 = ( )78 10
Example 2.7.13
Solution :
Computer Organization 2 - 6 Arithmetic Unit
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11 0 0
+
11 0 1
–1 –2
1 1 0
01 0 1 1
01 1 1 0 0 1 0
2's complement of 13 2
2's complement of 13
2's complement of 78
0 1 1 0 1
0 1 1 0
1 0 0 1 1 0
01
13
13 2 by shift left 1-bit
2's complement of 13 2
1
0
0 0 0
111
1
0011
+
Divisor (B)
1's complement
Add 1
2's complement
Initially
Shift left A, Q
Shift left A, Q
Shift left A, Q
Shift left A, Q
Subtract B
Subtract B
Subtract B
Subtract B
Set Q0
Set Q0
Set Q0
Set Q0
Restore (A+B)
Restore (A+B)
A Register
0 0 0 0 0
0 0 0 0 1
0 0 0 1 1
0 0 1 1 0
0 0 1 0 0
1 1 1 0 0
1 1 1 0 0
1 1 1 0 0
1 1 1 0 0
1 1 1 0 1
1 1 1 1 1
0 0 0 1 0
0 0 0 0 0
0 0 1 0 0
0 0 1 0 0
0 0 0 0 1
0 0 0 1 1
1 1 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 1 0
1 0 0 0
0 0 0 0
0 0 0 1
0 0 1 1
Q Register
First cycle
Second cycle
Third cycle
Fourth cycle
Dividend
Remainder
Quotient
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Example 2.7.15
Solution :
Example 2.7.16
Solution :
Computer Organization 2 - 8 Arithmetic Unit
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A Register Q Register
0 0 0 0 1 1 0 0
0 0 0 0 0 1 1 0 0
1 1 1 0 1
1 1 1 0 1
0 0 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
0 0 0 0 0
1 1 1 0 1
1 1 1 0 1
0 0 0 0 0
0 0 0 1 1
1 1 1 0 1
0 0 0 1 1
0 0 0 1 1
1 0 0 0
0 0 0
0 0 1
0 1 0
0 0 0 1
0 0 1 0
0 1 0 0
Initially
Shift
Shift
Shift
Shift
Dividend
First cycle
Second cycle
Third cycle
Fourth cycle
Quotient
Restoreremainder
Subtract B
Subtract B
Add
Add
Add divisor
0 1 1
1 0 0
0
1
1
1 1 0 1
+
Divisor (B)
1's complement
Add 1
2's complement
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Example 2.7.17
Solution :
Computer Organization 2 - 9 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
Initially
Shift left A, Q
Shift left A, Q
Subtract B
Add B
A Register
0 0 0 0 0
0 0 0 0 1
1 1 1 0 0
1 1 1 0 1
0 0 0 1 1
1 1 1 1 0
1 1 1 1 1
0 0 0
Q Register
First cycle
Second cycle
Third cycle
Fourth cycle
Dividend
Quotient
1 0 0 0
0 0 0
Remainder
0 0 0 0
0 0 0 0
Shift left A, Q
Add B
1 1 1 0
0 0 0 0 1
0 0 0
0 0 0 1
1
0 0 1 10
Shift left A, Q
Subtract B
0 0 1 0
1 1 1 1 1
0 0 1
0 0 1 0
0
1 1 0 11
Add B
1 1 1 1
0 0 0 1 0
1
0 0 1 10 Restore remainder
Divisor
1's complement
Add 1
2's complement
0 0 1 1
1 1 0 0
1 01 1
+ 1
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Example 2.8.9
Solution :
Step 1 : Convert decimal number in binary format.
Integer part :
Computer Organization 2 - 10 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
Initially
Shift left A, Q
Shift left A, Q
Shift left A, Q
Shift left A, Q
Subtract B
Add B
Subtract B
A Register
0 0 0 0 0
0 0 0 0 1
1 1 1 0 0
1 1 1 1 1
0 0 1 0 1
1 1 1 0 1
0 0 0 1 1
0 0 0 1 1
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
0 0 0 1 0
0 0 0 1 0
1 0 1 1
0 1 1
1 1 0 0
1 0 0
0 0 1
1 1 0
1 0 0
0 0 1
Q Register
First cycle
Second cycle
Third cycle
Fourth cycle
Dividend
Remainder Quotient
0 1 1 00
Add B
1
1
16 309
19
1
0
1
3
5 LSD
MSD
RQ
16
16
(309)10 = (135)16
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(309)10
= (135)16
= (000100110101)2
Fractional part :
(0.1875)10 = (0.001)2
(309.1875)10 = (100110101.001)2
Step 2 : Normalize the number
100110101.001 = 1.00110101001 28
Step 3 : Single precision representation for a given number
S = 0, E = 8, M = 0011 0101 0010
Bias for single precision format is = 127
E = E + 127 = 8 + 127 = (135)10 = (10000111)2
Number in single precision format is given as
Step 4 : Double precision representation
For a given number
S = 0, E = 8, M = 0011 0101 0010
Computer Organization 2 - 11 Arithmetic Unit
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0 0
1
1
Hex number
0 0 1
3
10 1 0
5
10 Binary number
0.1875 2 = 0 375.
0.375 2 = 0 75.
0.75 2 = 1 5.
MSD
LSD
0
0
1
Fraction Base Product
×
×
×
0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 0
31 30 23 22
0
0
1 0 0 1 0
Sign Exponent Mantissa
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Bias for double precision format is = 1023
E = E + 1023 = 8 + 1023 = (1031)10 = (10000000111)2
Number in double precision format is given as
Example 2.8.10Solution :
Step 1 : Convert the decimal number in binary format.
Fractional part :
(0.0625)10 = (0.0001)2
Step 2 : Normalize the number
0.0001 = 1.0000 2– 4
Computer Organization 2 - 12 Arithmetic Unit
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Sign Exponent Mantissa (52 - bits)
0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0
0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0
63 62 52 51
0 0
1 0
1 0 1 0 0 1 0
Sign Exponent Mantissa
0.0625 2 = 0 125.
0.125 2 = 0 25.
0.25 2 = 0 5.
MSD
0
0
0
Fraction Base Product
×
×
×
0.5 2 = 1 0.
LSD
1×
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Step 3 : Single precision representation
For a given number
S = 0, E = – 4, M = 0000
Bias for a single precision format is = 127
E = E + 127 = – 4 + 127 = (123)10 = (01111011)2
Number in single precision format is given as
Step 4 : Double precision representation
For a given number
S = 0, E = – 4, M = 0000
Bias for double precision format is = 1023
E = E + 1023 = (1019)10 = (01111111011)2
Number in double precision format is given as
Example 2.8.11
Solution : i) 32.75
Step 1 : Convert the decimal number in binary format.
Integer part :
Computer Organization 2 - 13 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
0 0 1 1 1 1 0 1 1 0 0 0
31 30 23 22
0
Sign Exponent Mantissa
0 0
0
0 0 1 1 1 1 1 1 1 0 1 1
63 62
0
Sign Exponent Mantissa (52 bits)
00 0 0
52 51 1 0
16
16
32
2
0
0
2
Q R
MSD
LSD
(32)10 = (020)16
0 0 0 0 0 0 1 0 0 0 0 0
0 2 0 Hex number
Binary number
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(32)10 = (020)16 = (0000 0010 0000)2
Fractional part :
(0.75)10 = (0.110)2
(32.75) = (010000.110)2
Step 2 : Normalize the number
0100000.110 = 1.00000110 25
Step 3 : Single precision representation
For a given number
S = 0, E = 5, M = 00000110
Bias for a single precision format is = 127
E = E + 127 = 5 + 127 = (132)10 = (10000100)2
Number in single precision format is given as
ii) 18.125
Step 1 : Convert the decimal number into binary format
Integer part :
Computer Organization 2 - 14 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
0.75 2 = 1 5.
0.5 2 = 1 0.
0.0 2 = 0 0.
MSD
LSD
1
1
0
Fraction Base Product
×
×
×
0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0
31 30 23 22 0
Sign Exponent Mantissa
16
16
18
1
0
2
1
Q R
MSD
LSD
(18)10 = (12)16
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(18)10 = (12)16 = (000 100 10)2
Fractional part :
(0.125)10 = (0.001)2
(18.125)10 = (010010.001)2
Step 2 : Normalize the number
10010.001 = 1.00100010 24
Step 3 : Single precision representation
For a given number
S = 0, E = 4, M = 00100010
Bias for a single precision format is = 127
E = E + 127 = 4 + 127 = (131)10 = (10000011)2
Number in single precision format is given as
Example 2.8.12
Solution : Refer section 2.3.1
Computer Organization 2 - 15 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
0 0 0 1 0 0 1 0
1 2 Hex number
Binary number
0.125 2 = 0 25.
0.25 2 = 0 5.
0.5 2 = 1 0.
MSD
LSD
0
0
1
Fraction Base Product
×
×
×
0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0
31 30 23 22 0
Sign Exponent Mantissa
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Step 1 : Convert decimal number in binary format integer part.
Integer part :
2 84 0 LSD
2 42 0
2 21 1
2 10 0
2 5 1
2 2 0
2 1 1 MSD
0
(84)10 = (1010100)2
Fractional part :
0.25 2 = 0.50 = 0.50 with carry 0 MSD
0.50 2 = 1.00 = 0.00 with carry 1 LSD
(0.25)10 = (0.01)2
– (84.25)10 = (1010100.01)2
Step 2 : Normalize the number
– 1010100.01 = – 1.01010001 26
Step 3 : Single precision representation
For a given number
S = 1, E = 6 and M = 0101 0001
Bias for single precision format is = 127
E = E + 127 = 6 + 127 = (1 3 3 )10
= (1 0 0 0 0 1 0 1) 2
Number in single precision format is given as
1
ign
1 0 0 0 0 1 0 1
Exponent
0 1 0 1 0
S
0 0 1 0 0 . .. . 0
Mantissa (23-bits)
Step 4 : Double precision representation for a given number
S = 1, E = 6 and M = 0101 0001
Computer Organization 2 - 16 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
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Bias for double precision format is = 1023
E = E + 1023 = 6 + 1023 = (1 0 2 9 )10
= (10000000101)2
Number in double precision format is given as
1
ign
1 0 0 0 0 0 1 0 1
Exponent
0 1 0 1
S
0 0 0 0 0 1 0 0 .... 0
Mantissa (52-bits)
Computer Organization 2 - 17 Arithmetic Unit
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM
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Important Solved Examples
Example 5.3.7
Solution : Word bits : Each block consists of 128 words.
Word bits are : 7 (27 = 128)
Block bits : Block in cache = 1128
K = 1024128
= 8
Block bits are : 3 (23 = 8)
Address bits : 16 address bits. Since 216 = 64 K
Tag bits : Address bits – (word bits + block bits)
= 16 – (7 + 3) = 6 bits
Main memory address =
Tag Block Word
6 3 7
Example 5.4.1
Solution : The Fig. 5.1 shows the address space and memory space split into groups of
1K words. At any given time, up to four pages of address space may reside in main
memory in any one of the four blocks.
TECHNICAL PUBLICATIONS - An up thrust for knowledgeTM(5 - 1)
4 Memory Organization5 Memory Organization
Block 0
Block 1
Block 2
Block 3
Memory space
M = 4 K = 212
Page 2
Page 1
Page 0
Page 3
Page 4
Page 5
Page 6
Page 7
Address space
N = 8 K = 213
Fig. 5.1 Address space and memory space
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i) LRU : Least Recently Used
ii) LFU : Least Frequently Used
iii) FIFO : First in First Out
Example 5.4.2
Solution :
Cache trace for LRU policy
Cache trace for FIFO policy
Computer Organization 5 - 2 Memory Organization
TM
Initial 4 2 0
0
1
1
2
2
6
6
1 4 0 1 0 2 3 5 7
4 4 4 4
222
0 01
6
2
41
6
0
41
2 2 2 2
0 0 0 7
4 3331 1 5 5
Initial 4 2 0
0
1
1
2
2
6
6
1 4 0 1 0 2 3 5 7
4 4 4 4
222
0 0
1
6
0
4
1
4
1
2
3
2
5
2
7
6 6
4
5
4
2
3 3
Initial 4 2 0
0
1
1
2
2
6
6
1 4 0 1 0 2 3 5 7
4 4 4 4
222
0 0
1
6
2
4
1
0
4
1
2 2
0 0
3
1
5
2
1
0
2
1
7
Initial 1 6 4
4 4 4 44 4 4
5 1 4 3
3 3 6 63 5 3
2
2 2 2 76 6 6
1 2 1 4 6 7 4
1 1 1 11 1 1
Fig. 5.2 (a)
Initial 1 6 4
4 3 33 74 4 4 3
5 1 4 3
3 1 61 63 3 1 1
2
2 5 44 42 5 5 5
1 2 1 4 6 7 4
1 2 22 26 6 6 6
Fig. 5.2 (b)