computer organization & programming chapter 5 synchronous components
TRANSCRIPT
Computer Organization & Programming
Chapter 5
Synchronous Components
Clocks
Synchronization toolA clock allows separate circuits to do their work at precisely the same time.
Set Reset Latch (SR Latch)
Clocked latches
Control exactly when the S or R input is provided
Clocked D latch
No need for separate variables R, S since they are mutually exclusive. D and D’ provide the same effect.
Latch using Mux
Standard representations
Latch loaded when clock is 1
Latch loaded when clock is 0(Note inversion bubble on CK)
Flip flop loaded when clock is changing from 0 to 1 (rising edge)
Flip flop loaded when clock is changing from 1 to 0 (falling edge)
Do we care? Not much. Just know that boxes that look like this hold a value
8-bit register
Pin 1 drives clear on all the flip flopsPin 11 drives enable (CK) on all. Pin 11’s inverter serves as an amplifier also.
FF with asynchronous Set & Reset
Shift Register
Right-Left Shift Register
Synchronous Up-Counter
Synchronous Up-Counter + Count Enable and Parallel Load
Sequential Circuits
So far, all outputs have been determined completely by the current input.
Having a clock pulse allows us to determine the time at which each circuit fires.
Circuits that allow the output of a circuit to become an input to the next iteration of the circuit are called sequential circuits.
A sequential logic unit is also known as a Finite State Machine
Finite State Machines
A finite state machine takes an input and a current state and produces an output and a next state
Classical model of FSM
Abstraction of a delay mechanism. This will hold the value of the state output and release it as input in the next cycle.
Example –Pseudo Random Numbers
FSM for thePseudo Random Numbers
FSM by a Graph
FSM – Formal Definition
State Transition Diagram
Example
Look for the sequence ‘110’ (output ‘1’ when found)
Step 1 – Build the Graph
Step 2 – write transition table
Step 3 – Allocate State Values
Step 4 – Get Functions
Step 5 – Implement