This course covers the following topics: Introduction to computer evolution, technology trends, system performance by Amdhal’s law. Computer structure that consists of structure & function of computer system, bus systems and bus arbitrations. Instruction Set Architecture (ISA) such as instruction set design issue and classifying ISA. Memory addressing such as addressing mode, CISC and RISC. ALU design. Computer architecture using MIPS architecture. Computer memory such as main memory design, memory hierarchy design, cache performance and virtual memory for paging and segmentation. Pipelining such as instruction pipeline, MIPS pipeline, pipelined vector processor and RISC pipelining. Parallel processors such as SIMD, MIMD, processors array, superscalar and I/O devices such as hard disk, RAID and multicore programming.

Minimum 80%

8.00 - 9.00

9.00 - 10.00

10.00 - 11.00

11.00 - 12.00

12.00 - 1.00

1.00 – 2.00

2.00 - 3.00

3.00 - 4.00

4.00 - 5.00

5.00 - 6.00

6.00 - 7.00

MONDAY

TUESDAYConsultation

KT6144 / KT6213

WEDNESDAY

THURSDAYKT6144 / KT6213

DK4 FKAB

FRIDAY

Items Weightage

Quizzes / Test 20% - 30%

Assignments / Project 10% - 30%

Final Exam 30% - 50%

TOTAL 100%

We shall assign you :We shall assign you : Items

Assignments

Project

Mid-Semester Test

Final Exam

• Hennessy, J.L. & Patterson, P.A. 2007. Computer architecture: A quantitative approach, 4th Ed., Elsevier Science and Technology Book.• Hesham El-Rewini, Mostafa Abd-El-Barr.2005. Advanced computer architecture and parallel processing, Wiley.• Hill, M.D. 2009. Fault tolerant computer architecture, Morgan & Claypool Publishers.• Keckler, S.W., Olukotun K., Hofstee. H.P. 2009. Multicore processors and systems, Springer.

Author: William StallingsTitle: Computer Organization and ArchitectureEdition: 2010, 8th EditionPublisher: Pearson

Week Date Topics Lecturer 1 12-16 Sep Introduction

Dr. Nasharuddin Zainal

2 19-23 Sep Computer Structure

3 26-30 Sep Instruction Set Architecture (ISA)

4 3-7 Oct Instruction Set Architecture (ISA)

5 10-14 Oct Data Representation

6 17-21 Oct Parallel Processor

7 24-28 Oct Addressing Modes

8 31 Oct – 4 Nov Mid Semester Exam

9 14-18 Nov Computer Architecture

Prof. Dr. Kasmiran Jumari

10 21-25 Nov Pipelining

11 28 Nov – 2 Dec Computer Memory

12 5-9 Dec Virtual Memory

13 12-16 Dec I/O Devices

14 19-23 Dec Operating Systems and applications

Sem break: 7-11 Nov 2011

Exam starts : 3-20 Jan 2012

http://www.spin.ukm.my

Ability to apply transfer register notation to describle data flow in CPUsAbility to explain interrupt operation and exception handling mechanismsAbility to compare main and virtual memory, and cache systems operationAbility to design datapath logic in CPUs and microprogrammed control units