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R. V. COLLEGE OF ENGINEERING

(Autonomous Institution under VTU)

VI Semester B. E. Examinations, May/Jun 14

Computer Organization and Architecture

(Model question paper )

Time: 03 Hours Maximum Marks: 100

Instructions to candidates:

1. Answer all questions from Part A. Part A questions should be answered in first 3 pages of

the answer book only

2. Answer FIVE full questions from Part B.

Part A

1.1 The ____________ are used to designate the source or destination of the data on the data bus. 1.2 What is thrashing?

1.3 If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be ______ bits

1.4 The performance of cache memory is frequently measured in terms of a quantity called

1.5 Draw the typical DRAM cell 1.6 What is soft error with respect to memory?

1.7 Expand RAID 1.8 What is the international reference alphabet ?

1.9 Express -1/32 in IEEE 32-bit floating point format 1.10 What is the sign-extension rule for twos complement numbers?

1.11 Consider the following operation on a binary word. Start with the least significant bit. Copy all bits that are 0 until the first bit is reached and copy that bit, too. Then take the complement of each bit there after. What is the result?

1.12 What is a delayed branch?

1.13 What is the relationship between instructions and micro-instructions? 1.14 What is the purpose of control memory?

1.15 What is the difference between a hardwired implementation and a microprogrammed implementation of a control unit?

1.16 What is the function of HOLDA ?

1.17 Expand MISD 1.18 What is interleaved multithreading ?

1.19 Give one benefit of clustering 1.20 What is passive standby ?

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Part - B

2 a List andexplain the classes of interrupt 4

b Elicit with timing diagram data transfer on the PCI 8

c Draw the bus configuration in high-performance architecture 4

OR

3 a Discuss set associative Mapping Cache Organization with a neat diagram. 10

b Briefly describe the three possible approaches to cache coherency. 06

4 a How does SDRAM differ from ordinary DRAM ? 04

b Write characteristics of Winchester Disk Format. 06

c Explain how redundancy achieved in RAID system? 06

OR

5 a Draw the flow chart of simple interrupt processing 06

b Describe with neat diagram the characteristics of I/O channels 06

c A microprocessor scans the status of an output I/O device every 20 ms. This is accomplished by means of a timer alerting the processor every 20 ms. The interface

of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8 MHz? Assume for simplicitythat all pertinent instruction cycles take 12 clock cycles.

04

6 a Describe the geometric depection of twos complement integers 07

b Draw the Hardware Implementation of Unsigned Binary Multiplication 04

c Show how the following floating-point additions are performed (where significands are truncated to 4 decimal digits). Show the results in normalized form. 5.566 * 102 + 7.777 * 102

05

OR

7 a List four alternative methods of rounding the result of a floating-point operation. 04

b Briefly explain the following representations: sign magnitude, twos complement, biased.

06

c Write the six stage CPU Instruction pipeline 06

8 a Explain the distinction between the written sequence and the time sequence of an

instruction.

04

b Your ALU can add its two input registers, and it can logically complement the bits of either input register, but it cannot subtract. Numbers are to be stored in twos complement representation. List the micro-operations your control unit must perform

to cause a subtraction.

08

c Provide a typical list of the inputs and outputs of a control unit. 04

OR

9 a Describe the implementation of the multiply instruction in the hypothetical machine designed by Wilkes. Use narrative and a flowchart.

08

b Assume a microinstruction set that includes a microinstruction with the following symbolic form: where is the sign bit of the accumulator and are the first seven bits of the microinstruction. Using this microinstruction, write a microprogram that

implements a Branch Register Minus (BRM) machine instruction, which branches if the AC0 is

negative. Assume that bits C1through Cnof the microinstruction specify a parallel set

04

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of micro-operations. Express the program symbolically

c A simple processor has four major phases to its instruction cycle: fetch, indirect, execute,

and interrupt.Two 1-bit flags designate the current phase in a hardwired implementation. a. Why are these flags needed?

b. Why are they not needed in a microprogrammed control unit?

04

10 a Give the A Taxonomy of Parallel Processor Architectures 06

b Explain the different approaches to executing Multiple Threads 10

OR

11 a Let be the percentage of program code that can be executed simultaneously by

n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of x MIPS. (i). Derive an expression for the effective MIPS rate when using the system for

exclusive execution of this program, in terms of n, and x. (ii) If n = 16 and x=14 MIPS, determine the value of that will yield a system

performance of 40 MIPS.

08

b What are some of the potential advantages of an SMP compared with a uniprocessor? 04

c What are the differences among UMA, NUMA, and CC-NUMA? 04

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