conditional-sum adders and parallel prefix network adders ece 645: lecture 5
TRANSCRIPT
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Conditional-Sum Addersand
Parallel Prefix Network Adders
ECE 645: Lecture 5
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Required Reading
Chapter 7.4, Conditional-Sum AdderChapter 7.5, Hybrid Adder Designs
Chapter 6.4, Carry Determination as Prefix ComputationChapter 6.5, Alternative Parallel Prefix Networks
Note errata at:http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errors
Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design
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Recommended Reading
J-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Chapter 11.1.9, Prefix Adders
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Conditional-SumAdders
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One-level k-bit Carry-Select Adder
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Two-level k-bit Carry Select Adder
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Conditional Sum Adder
• Extension of carry-select adder• Carry select adder
• One-level using k/2-bit adders• Two-level using k/4-bit adders• Three-level using k/8-bit adders• Etc.
• Assuming k is a power of two, eventually have an extreme where there are log2k-levels using 1-bit adders• This is a conditional sum adder
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Conditional Sum Adder:Top-Level Block for One Bit Position
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Three Levels of a Conditional Sum Adder
2 2
2 2
xi+3 yi+3
c=0c=1
2 2
xi+2 yi+2
c=0c=1
1 1
1
1
3c=0
3c=1
2 2
2 2
xi+1 yi+1
c=0c=1
2 2
1-bit conditional sum block
xi yi
c=0c=1
1 1
1
1
3c=0
3c=1
22
1
1
3 3
5
c=1
5
c=0
1+1
2+1
4+1
branch point
concatenation
block carry-indetermines selection
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16-Bit Conditional Sum Adder Example
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Conditional Sum Adder Metrics
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Parallel Prefix Network Adders
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Basic component - Carry operator (1)
B” B’
g” p” g’ p’
g p
g = g” + g’p”p = p’p”
(g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”)
B
Parallel Prefix Network Adders
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Basic component - Carry operator (2)
B” B’
g” p” g’ p’
g p
g = g” + g’p”p = p’p”
(g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”)
B
overlap okay!
Parallel Prefix Network Adders
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Associative
Not commutative
[(g1, p1) ¢ (g2, p2)] ¢ (g3, p3) = (g1, p1) ¢ [(g2, p2) ¢ (g3, p3)]
(g1, p1) ¢ (g2, p2) (g2, p2) ¢ (g1, p1)
Properties of the carry operator ¢
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Major concept
Given:
Find:
(g0, p0) (g1, p1) (g2, p2) …. (gk-1, pk-1)
(g[0,0], p[0,0]) (g[0,1], p[0,1]) (g[0,2], p[0,2]) … (g[0,k-1], p[0,k-1])
ci = g[0,i-1] + c0p[0,i-1]
Parallel Prefix Network Adders
block generate from index 0 to k-1
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Parallel Prefix Sum Problem
Given:
Find:
Parallel Prefix Adder Problem
Given:
Find:
x0 x0+x1 x0+x1+x2 … x0+x1+x2+ …+ xk-1
x0 x1 x2 … xk-1
x0 x0 ¢ x1 x0 ¢ x1 ¢ x2 … x0 ¢ x1 ¢ x2 ¢ … ¢ xk-1
x0 x1 x2 … xk-1
where xi = (gi, pi)
Similar to Parallel Prefix Sum Problem
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Parallel Prefix Sums Network I
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Cost = C(k) = 2 C(k/2) + k/2 = = 2 [2C(k/4) + k/4] + k/2 = 4 C(k/4) + k/2 + k/2 = = …. = = 2 log k-1C(2) + k/2 (log2k-1) = = k/2 log2k
2
Example:
C(16) = 2 C(8) + 8 = 2[2 C(4) + 4] + 8 = = 4 C(4) + 16 = 4 [2 C(2) + 2] + 16 = = 8 C(2) + 24 = 8 + 24 = 32 = (16/2) log2 16
C(2) = 1
Parallel Prefix Sums Network I – Cost (Area) Analysis
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Delay = D(k) = D(k/2) + 1 = = [D(k/4) + 1] + 1 = D(k/4) + 1 + 1 = = …. = = log2k
Example:
D(16) = D(8) + 1 = [D(4) + 1] + 1 = = D(4) + 2 = [D(2) + 1] + 2 = = 4 = log2 16
D(2) = 1
Parallel Prefix Sums Network I – Delay Analysis
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Parallel Prefix Sums Network II (Brent-Kung)
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Cost = C(k) = C(k/2) + k-1 = = [C(k/4) + k/2-1] + k-1 = C(k/4) + 3k/2 - 2 = = …. = = C(2) + (2k - 2k/2(log k-1)) - (log2k-1) = = 2k - 2 - log2k
Example:
C(16) = C(8) + 16-1 = [C(4) + 8-1] + 16-1 = = C(2) + 4-1 + 24-2 = 1 + 28 - 3 = 26 = 2·16 - 2 - log216
C(2) = 1
2
Parallel Prefix Sums Network II – Cost (Area) Analysis
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Delay = D(k) = D(k/2) + 2 = = [D(k/4) + 2] + 2 = D(k/4) + 2 + 2 = = …. = = 2 log2k - 1
Example:
D(16) = D(8) + 2 = [D(4) + 2] + 2 = = D(4) + 4 = [D(2) + 2] + 4 = = 7 = 2 log2 16 - 1
D(2) = 1
Parallel Prefix Sums Network II – Delay Analysis
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x0x1x2x3x4x5x6x7
s0s1s2s3s4s5s6s7
4 –bit B-K PPN
8-bit Brent-Kung Parallel Prefix Network
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x1’x3’
s1’s3’
2 –bit B-K PPN
x5’x7’
s5’s7’
4-bit Brent-Kung Parallel Prefix Network
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8-bit Brent-Kung Parallel Prefix Network Adder
GP GP GP GP GP GP GPGPGP
x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0
g7,p7 g6,p6 g5,p5 g4,p4 g3,p3 g2,p2 g1,p1 g0,p0
ccc ccc ccc ccc
ccc ccc
ccc
ccc
ccc ccc ccc
g[0,0]
p[0,0]
g[0,1]
p[0,1]
g[0,2]
p[0,2]
g[0,3]
p[0,3]
g[0,4]p[0,4]
g[0,5]p[0,5]
g[0,6]p[0,6]
g[0,7]
p[0,7]
CC
c0
C C C C C C C
SS S S S S S S S
c7 p7 c6 p6 c5 p5 c4 p4 c3 p3 c2 p2 c1 p1
p0
s7 s6 s5 s4 s3 s2 s1 s0
c8
criticalpath
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Critical Path
GP
c
C
S
gi = xi yi
pi = xi yi
g = g” + g’ p”p = p’ p”
ci+1 = g[0,i] + c0 p[0,i]
si = pi ci
1 gate delay
2 gate delays
2 gate delays
1 gate delay
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Brent-Kung Parallel Prefix Graph for 16 Inputs
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Kogge-Stone Parallel Prefix Graph for 16 Inputs
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Comparison of architectures
HybridNetwork 2Brent-Kung
Kogge-Stone
Cost(k)
Delay(k)
Cost(16)
Delay(16)
Cost(32)
Delay(32)
2 log2k - 2
2k - 2 - log2k
log2k+1 log2k
k/2 log2k k log2k - k + 1
6 5 4
26 32 49
8 6 5
57 80 129
Parallel Prefix Network Adders
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Latency vs. Area Tradeoff
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Hybrid Brent-Kung/Kogge-Stone Parallel Prefix Graph for 16 Inputs