conference on adaptive hardware and systems (ahs'14) - flextiles introductions
DESCRIPTION
FlexTiles is a FP7 Project with the goal of designing a tool-chain for the design of a 3D SoC and prototype on a FPGA Development Platform. This presentation covers the "why, how, when and where" of the Project that will complete in Year 2015TRANSCRIPT
www.thalesgroup.com
Research & Technology
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Designing Sophisticated Signal Processing Architectures for
challenging real-time applications The FP7 - FlexTiles
projectwww.flextiles.euPhilippe MILLET, PhD, AHS 2014
www.thalesgroup.com
2 /2 / 60
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FlexTiles Workshop
FlexTiles : Self-Adaptive Heterogeneous Many-Core Technology Based on Flexible Tiles
Workshop On Friday 18th in the morning (9:00 - 13:00)
• 3-D Stacked Chip Technology and Strategies for Optimal Usage of Through Silicon Vias (TSV)
• FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)
• Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core Architecture.
• Dynamically Reconfigurable Embedded FPGA System
• FPGA-Based Emulation of FlexTiles Platform
• Demonstration: OVP Simulation of the FlexTiles Platform
3 /3 / 60
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Some challenging applications within THALES
Cognitive radio
Source: the India economy review
Adapt continuously the frequency and protocol to available ones
Avoid jammers or obfuscated communications
4 /4 / 60
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Some challenging applications within THALES
Smart camera
Highway: follow cars, detect traffic jam or accidents
Airport : find and follow people, detect abandoned luggage, strange or dangerous behaviours.
Dynamicity depends on the number of detections
Cameras have local processing capability to send data only when something "interesting" has been detected.
5 /5 / 60
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Some challenging applications within THALES
UAV
Autonomous, take decisions without or with low control.React to the environment.
Self-repair.
Adapt the mission to what the UAV finds.
Activate software parts to match the actual situation.
The software is dynamically activated and mapped to the available resources.
6 /6 / 60
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Real-time embedded products at THALES
Embedded Real-Time Market
low power consumption target in a range from 10W - 40W
some products are designed with <1W (low adaptivity)
General Purpose Processors are too hungry
low volumes (less than 1000 pieces/year) designing dedicated ASIC is not an option
long life-time (~20 years) Long Life No Maintenance
hardware upgrade or retrofit must cost as little as possible
programmable device is preferred
7 /7 / 60
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Some challenging applications within THALES
Embedded Real-Time Market
low power consumption
low volumes
long life-time (~20 years)
Adapt to environment dynamicity, flexibility & dependability
Smart cameraCognitive radio UAV
We need more than static dataflow.We need adaptability in the software as well as in the hardware
Source: the India economy review
8 /8 / 60
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Homogeneous Manycore a solution?
One way to get high performance / watt is parallelism.
• Instead of 1 big core with high computation power but also high power consumption, get more "smaller" cores in parallel
9 /9 / 60
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Homogeneous manycores: Good at Parallelism
Parallelisation: raise computing power / lower power consumption.
Homogeneity eases programming (C-Like + tools) but:
Maximum performance only with static application.
automatic optimisation (data parallelism)
static allocation and scheduling.
Else Average performances / No guaranty
Tilera - Tile-Gx72 – 72 cores
C/C++
Nvidia - Kepler 2000+ cores
OpenCL/CUDA (C like+kernels)
Kalray - MPPA - 256/1024 cores
SigmaC (C++ like for dataflow)
source: www.tilera.com
http://www.kalray.eu
source: www.nvidia.fr
10 /10 / 60
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Manycore is a main issue for the industry
Programmability (industrial view): Time to market
SW Development costs
Reuse of legacy code
What about Manycores? Homogeneous?
Heterogeneous?
11 /11 / 60
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Manycore is a main issue for the industry
Programmability (industrial view): Time to market
SW Development costs
Reuse of legacy code
What about Manycores? Homogeneous?
Heterogeneous?
Why taking risks with Manycores ?
We want to continue like in the good days:
compile “without thinking” and get performances
(keep it as long/simple as possible) !
12 /12 / 60
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Manycore
No more choice, we HAVE TO jump
ManyCores! Problem Solved...?
13 /13 / 60
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Manycore
No more choice, we HAVE TO jump
ManyCores! Problem Solved...?
WAIT!
14 /14 / 60
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Parallelisation is not enough: did we miss something?
Homogeneous?
15 /15 / 60
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Challenge
PROCESSORS (GPPs)
FPGA
DSP
available architectures: already homogeneous systems
With ManyCores and integration, the architectures are changing...
16 /16 / 60
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Challenge
PROCESSORS
FPGA
DSPSource: http://www.gamearenaph.com
Source: http://www.vision.caltech.edu
APPLICATIONS
computation demanding applications
Usual way: put as many resources as necessary to execute the application in any situation.=> hardware must allow the hardest case to execute
Dynamicity:=> the hardest case is unknown=> too costly, too heavy, too high power consumption.
17 /17 / 60
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Challenge
PROCESSORS
FPGA
DSPSource: http://www.gamearenaph.com
Source: http://www.vision.caltech.edu
APPLICATIONS
Source: http://www.funtoosh.com
how can we fit big applications in the hardware?
How to efficiently map complex applications
to heterogeneous many-core architectures with limited budget
(power, performance, …)
???
LIMITED BUDGET
Source: http://www.lnci.org.au
www.thalesgroup.com
Research & Technology
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www.flextiles.eu
Philippe [email protected]
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
Duration: 36 months (42)
www.thalesgroup.com
19 /19 / 60
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Consortium and questions
Partners & Third Party
Country Main scientific and technical contributions
THALES France Infrastructure and applications
KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United Kingdom
FPGA Demonstrator
ACE Netherlands Parallelisation and compilation Tools
RUB Germany IntegrationFPGA scheduling
9 partners in 5 countries
20 /20 / 60
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Did I mension our FlexTiles Workshop?
FlexTiles : Self-Adaptive Heterogeneous Many-Core Technology Based on Flexible Tiles
Workshop On Friday 18th in the morning (9:00 - 13:00)
• 3-D Stacked Chip Technology and Strategies for Optimal Usage of Through Silicon Vias (TSV)
• FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)
• Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core Architecture.
• Dynamically Reconfigurable Embedded FPGA System
• FPGA-Based Emulation of FlexTiles Platform
• Demonstration: OVP Simulation of the FlexTiles Platform
21 /21 / 60
The
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ent
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ents
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A Town close to Madrid
22 /22 / 60
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Customized/Customizable chips vs. FPGA
Xilinx – ZYNQ : FPGA with a dual ARM A9 core
MPCore with reconfiguration capabilities
ClusterCluster ClusterCluster ClusterCluster
ClusterCluster ClusterCluster ClusterCluster
ClusterCluster ClusterCluster ClusterCluster
Fabric Controller
core
Fabric Controller
core
Fabric
GOOD Parallelization
POOR CustomizationPOOR Parallelization
GOOD Customization
ST – P2012 aka STHORM (Heterogeneous manycore fabric)
Once done: Dedicated to a specific domain of applications
Affordable only for large series of products.
Main issue: Domain dedication
idem with MPSoCs (TI-OMAPs)
23 /23 / 60
The
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rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
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atta
chm
ents
are
the
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pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
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iew
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inat
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ictly
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hibi
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out
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ritte
n ap
prov
al.
©T
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201
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FlexTiles Proposes
A 3D stacked chip based on:
A manycore layer GPPs
DSPs
A FPGA layer
A 3D-NoC
GOOD Parallelization
GOOD Customization
Customization at low price
Opportunity: self adaptive capabilities Future application needs
24 /24 / 60
The
info
rmat
ion
cont
aine
d in
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s do
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ent
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chm
ents
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pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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iew
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inat
ion,
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utio
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ictly
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out
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201
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Self adaptive?
Adapt the architecture to application requests at "real-time"
Improve yield and extend life-time of sub-micron technologies
Fault tolerance
Increase energy efficiency
give the right task to the best available processor
finalize the mapping at runtime
Temperature management re-mapping
Triplication, voting fault / error detection
Self-repair re-mapping taking dead cores into account
How to program it?
25 /25 / 60
The
info
rmat
ion
cont
aine
d in
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s do
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ent
and
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y of
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S.
You
are
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eby
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ied
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iew
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inat
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ictly
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prov
al.
©T
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201
1. T
empl
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Holistic Approach: Model of Execution
Model of ComputationModel of Computation
Optimisation toolsOptimisation tools
ProgrammingEfficiency
Self-AdaptiveCapabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of Execution
26 /26 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
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ent
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atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
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iew
, di
ssem
inat
ion,
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utio
n, c
opyi
ng o
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men
t is
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ictly
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hibi
ted
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out
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ritte
n ap
prov
al.
©T
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Model of Execution
Master NodesMaster Nodes
Slave NodesSlave Nodes
GPP nodes
eFPGA nodesDSP nodes
GPP Node
acceleratornode
NI
NoC
NI
Accelerator Interface (AI)
accrequestscontrol /
status control / status
DMA
DMArequests
data
Master-slave execution model
AI HW / SW independency regarding accelerator specificities
27 /27 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
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atta
chm
ents
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pert
y of
TH
ALE
S.
You
are
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eby
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ied
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iew
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inat
ion,
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opyi
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ictly
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hibi
ted
with
out
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n ap
prov
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©T
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1. T
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M
Model of Computation & Model of Programmation
Optimisation toolsOptimisation tools
ProgrammingEfficiency
Self-AdaptiveCapabilities
Relocation strategiesRelocation strategies
Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of Computation Model of ExecutionModel of Execution
Model of programmation
28 /28 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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iew
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ssem
inat
ion,
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utio
n, c
opyi
ng o
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men
t is
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ictly
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hibi
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out
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n ap
prov
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©T
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: Clusters group managed by a state management
: Cluster group input/output
ActAct ActAct
ActAct ActAct
ActAct
ActAct ActActActAct
state 1state 1
state 2state 2
state 3state 3
states managementstates managementcluster groupcluster groupevent
Model of Computation & Model of Programmation
Optimisation and parallelisation tools work on static applicationsfind static clusters inside the applications based on SDF/CSDF MoCBring Dynamicity with higher hierarchical level
: actor ~ task or tasks
: static cluster
ActAct
: Cluster input/output
actor: consumes and produces token of data with predefined and static rules
SDF, CSDF MoC
29 /29 / 60
The
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rmat
ion
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You
are
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eby
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ied
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iew
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ictly
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ritte
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prov
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ActAct
sensordata
states managementstates managementevent
ActAct
state 1state 1
nopnop
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
Model of Programmation
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
30 /30 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
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chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
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ied
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iew
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inat
ion,
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opyi
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men
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ictly
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ted
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out
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ritte
n ap
prov
al.
©T
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M
Dynamicity at cluster group level
ActAct
sensordata
states managementstates managementevent
ActAct
state 1state 1
nopnop
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
31 /31 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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utio
n, c
opyi
ng o
r ot
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ise
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men
t is
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ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
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201
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Start a new part of the application
ActAct
sensordata
states managementstates managementevent
ActAct
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
32 /32 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
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ise
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of t
his
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men
t is
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ictly
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hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
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201
1. T
empl
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M
Modification of the behaviour
sensordata
states managementstates managementevent
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActActActAct ActAct
ActAct
state 2state 2
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
33 /33 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
r ot
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ise
use
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his
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men
t is
str
ictly
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hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
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201
1. T
empl
ate
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M
Modification of the parallelisation level
sensordata
states managementstates managementevent
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActActActAct ActAct
ActAct
state 2state 2
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
34 /34 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
any
rev
iew
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ion,
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ictly
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prov
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©T
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empl
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ActAct
sensordata
states managementstates managementevent
ActAct
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates managementevent
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActscatter
scatter
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
gather
gather
sensordata
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
Model of Programmation
: Actor
: static cluster
ActAct
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
35 /35 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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rev
iew
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ion,
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opyi
ng o
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men
t is
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ictly
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out
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prov
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©T
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201
1. T
empl
ate
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p ve
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M
Programming efficiency: Model of Computation
ProgrammingEfficiency
Self-AdaptiveCapabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of ExecutionModel of Execution
Optimisation tools
Model of ComputationModel of Computation
36 /36 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
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ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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ion,
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men
t is
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ictly
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prov
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©T
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1. T
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Application (C code)
Application (C code)
C to SpearDE representation
Conversion (Thales)
C to SpearDE representation
Conversion (Thales)
Data parallelisation Mapping (Thales)Data parallelisation Mapping (Thales)
Graphic input (manual)
+C kernels
Graphic input (manual)
+C kernels
Streaming optimisation (ACE)
Streaming optimisation (ACE)
Compilation & Link(ACE)
Compilation & Link(ACE)
architecture representation
architecture representation
Master coresMaster coresSlave coresSlave cores
Library of IPsLibrary of IPs
Tool flow and MoC
Tool flow based
Programming efficiency: Model of Computation
Binaries
Acc compiler or C2VHDL tools(CSEM / UR1 / RUB)
Acc compiler or C2VHDL tools(CSEM / UR1 / RUB)
37 /37 / 60
The
info
rmat
ion
cont
aine
d in
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s do
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ent
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ents
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y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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rev
iew
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ion,
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men
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ictly
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prov
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©T
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201
1. T
empl
ate
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p ve
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M
Programming efficiency: Model of Computation
ProgrammingEfficiency
Self-AdaptiveCapabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Common Interfaces
Optimisation toolsOptimisation tools
38 /38 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
any
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iew
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ion,
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©T
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201
1. T
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Modularity and scalability: common interfaces
Homogeneous GPP nodes
Heterogeneous accelerators
nodes
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Generic Interfaces
eFPGA Domain (Reconfigurable HW acc.)
Dedicated Accelerator
Node
Dedicated Accelerator
Node
39 /39 / 60
The
info
rmat
ion
cont
aine
d in
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ent
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You
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TILE TILE
AIAI Accelerator InterfaceInterpret requests from GPP
NININetwork InterfaceInterfaces a node with NoC
Modularity and scalability: common interfaces
40 /40 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Relocation Strategies
ProgrammingEfficiency
Self-AdaptiveCapabilities
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Relocation Strategies
Common InterfacesCommon Interfaces
41 /41 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
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201
4/0
7/14
/ Ph
M
A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•FPGA•FPGA•GPP•GPP
•FPGA•FPGA
A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•DSP•DSP•GPP•GPP
•DSP•DSP
A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•DSP•DSP•DSP•DSP
•DSP•DSP
timerelocation relocation relocation
Relocation Strategies
42 /42 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
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201
4/0
7/14
/ Ph
M
Self-adaptation
Accelerator/Virtual Code
Dynamicallocation / binding
DIAGNOSISO = F(L)
ACTION
SYSTEM
MONITORING
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Dedicated Accelerator
Node
Dedicated Accelerator
Node
eFPGA Domain (Reconfigurable HW acc.)
43 /43 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Flexible Hardware
ProgrammingEfficiency
Self-AdaptiveCapabilities
Model of programmationModel of programmation
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Common InterfacesCommon Interfaces
Flexible Hardware
Relocation strategiesRelocation strategies
44 /44 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
3D stacked reconfigurable layer
45 /45 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Map Accelerated functions
46 /46 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Duplicate
47 /47 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Migrate
48 /48 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
3D Network
ProgrammingEfficiency
Self-AdaptiveCapabilities
Model of programmationModel of programmation
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Common InterfacesCommon Interfaces
Flexible Hardware
Relocation strategiesRelocation strategies
The Flexibility of the tile is based on the capabilities of the 3D Network
49 /49 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
did you say 3D?
50 /50 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
NoC QoS
chipchip
GPP
icache
dcache
dLMEM GPP
NI
iLMEM eFPGA
eFPGA
dLMEM eFPGA
iLMEM DSP
DSP
dLMEM DSP
DDR
NI+
DDR ctrl
on chipshMEM
NI NI
controlNOC
bitstreamNOC
dataNOC
instructionNOC
test/debugNOC
Avoid Bus contention, QoS depends on what you send through the NoC
51 /51 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
ANoC (CEA)
GALS: asynchronous logic in nodes, local synchronous cores-highly scalable-between nodes: no global clock, not even local clock-power efficient and dependable-packet switching-wormhole protocol-low latency
52 /52 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
AElite NoC (TUe)
Guaranteed levels of services and performancesContention free routing by construction- wormhole routing specified at design time Globally Synchronous with time slots
53 /53 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Demonstration
On a FPGA board provided by Sundance we demonstrate the self adaptive capabilities of the solution.
An OVP simulator is also available.
54 /54 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Demonstration: Building the HW platform
55 /55 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
FlexTiles Development Board
Virtex6FPGA 2
Virtex6FPGA 1
Implementation of multicore Implementation of
accelerators
Auroraor
Ethernet
Demonstration
56 /56 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Demonstration
FlexTiles Board
FPGA 2FPGA 1
FPGA 1
NOC
NI
AI
Acc
FPGA 2
AURORA interface
AURORA interface
NI
MultiGPPcore
AI Acc
57 /57 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
FPGA BOARDFPGA BOARD
NoC
Monitor
uBlaze
DMA
2x
uBlaze
DMA
2x
256kbyte
256kbyte
8 kbyte
8 kbyte
8 kbyte
8 kbyte
256kbyte
256kbyteTile 1
Tile 2
Host PC
Debug Link
256kbyte
SharedMemory
58 /58 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Demonstration: monitoring
59 /59 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
M
Conclusion FlexTiles … a complete platform
Virtualisation layerVirtualisation layer
relocatable binary coderelocatable binary code
Parallelisation, partioning Parallelisation, partioning
Application
Hardware Nodes
CompilationCompilation Synthesis, P&RSynthesis, P&Rrelocatable bitstreamrelocatable bitstream
Hardware Abstraction Layer
Hardware Abstraction Layer API
Operating Library API
KernelKernel Resource Monitoring &
Allocation
Resource Monitoring &
Allocation
DIAGNOSISO = F(L)
ACTION
SYSTEM
toolchain
operating library
heterogenousmanycore
MONITORING
60 /60 / 60
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out
Tha
les
prio
r w
ritte
n ap
prov
al.
©T
HA
LES
201
1. T
empl
ate
trt
p ve
rsio
n 7
.0.8
201
4/0
7/14
/ Ph
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Conclusion
Parallelisation is the only way to reach HPC for low power consumption.
But parallelism is not enough, customisation is also necessary
Only affordable for high volumes
Reconfigurable customisation is the solution:
Increase accessibility to heterogeneous manycore technology
Offers self-adaptive capabilities
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The
info
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thi
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and
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You
are
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any
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, di
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opyi
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herw
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str
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Tha
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ritte
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©T
HA
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1. T
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/ Ph
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Come visit us next Friday Morning
FlexTiles : Self-Adaptive Heterogeneous Many-Core Technology Based on Flexible Tiles
Workshop On Friday 18th morning (9:00 - 13:00)