conference proceedings from the 34th international symposium for

ISTFA 2008

TM

Conference Proceedings from the 34th International Symposium

for Testing and Failure Analysis

November 2–6, 2008 Oregon Convention Center

Portland, Oregon, USA

Sponsored by

www.asminternational.org/istfa www.asminternational.org

Published by ASM International®

Materials Park, Ohio 44073-0002

© 2008 ASM International. All Rights Reserved. Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis (#02210Z) www.asminternational.org

Copyright © 2008 by

ASM International® All rights reserved

No part of this book may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the written permission of the copyright owner.

First printing, November 2008

Great care is taken in the compilation and production of this Volume, but it should be made clear that NO WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE GIVEN IN CONNECTION WITH THIS PUBLICATION. Although this information is believed to be accurate by ASM, ASM cannot guarantee that favorable results will be obtained from the use of this publication alone. This publication is intended for use by persons having technical skill, at their sole discretion and risk. Since the conditions of product or material use are outside of ASM's control, ASM assumes no liability or obligation in connection with any use of this information. No claim of any kind, whether as to products or information in this publication, and whether or not based on negligence, shall be greater in amount than the purchase price of this product or publication in respect of which damages are claimed. THE REMEDY HEREBY PROVIDED SHALL BE THE EXCLUSIVE AND SOLE REMEDY OF BUYER, AND IN NO EVENT SHALL EITHER PARTY BE LIABLE FOR SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES WHETHER OR NOT CAUSED BY OR RESULTING FROM THE NEGLIGENCE OF SUCH PARTY. As with any material, evaluation of the material under end-use conditions prior to specification is essential. Therefore, specific testing under actual conditions is recommended. Nothing contained in this book shall be construed as a grant of any right of manufacture, sale, use, or reproduction, in connection with any method, process, apparatus, product, composition, or system, whether or not covered by letters patent, copyright, or trademark, and nothing contained in this book shall be construed as a defense against any alleged infringement of letters patent, copyright, or trademark, or as a defense against liability for such infringement. Comments, criticisms, and suggestions are invited, and should be forwarded to ASM International.

ISBN-13:978-0-87170-714-7 ISBN-10: 0-87170-714-4

SAN: 204-7586

ASM International® Materials Park, OH 44073-0002

www.asminternational.org

Printed in the United States of America

Multiple copy reprints of individual articles available from Technical Department, ASM International.


iii

EDFAS 2008-2009 BOARD OF DIRECTORS

EDFAS President EDFAS Vice President Mr. Tracy D. Myers Dr. Thomas Moore ON Semiconductor OmniProbe

Board Members Affiliation Mr. Tracy D. Myers EDFAS President ON Semiconductor Dr. Thomas Moore EDFAS Vice President OmniProbe Mr. Jeremy A. Walraven Secretary Sandia National Laboratories Dr. Lee Knauss Finance Officer Booz Allen Hamilton Mr. Gary Shade Past President Insight Analytical Labs Ms. Sandra Delgado Member at Large Nanolab Technologies Mr. Thomas S. Passek Executive Director ASM International Ms. Susan Li Member at Large Spansion Dr. Philippe Perdu Member at Large CNES Mr. Matthew Thayer Member at Large Advanced Micro Devices Mr. David P. Vallett Member at Large IBM Systems and Technology

Board Committees Affiliation Dr. Charles A. Parker ASM BOT Liaison Honeywell Aerospace Ms. Rosalinda M. Ring EDFA Chair SMSC Austin Mr.Thomas Zanon Education Chair PDF Solutions Inc. Mr. Nicholas Antoniou Events Chair Independent Consultant Mr. John West Membership Chair Texas Instruments Mr. Gary Shade Nominating Chair Insight Analytical Labs Mr. Jeremy Walraven Website Chair Sandia National Laboratories


iv

OORRGGAANNIIZZIINNGG CCOOMMMMIITTTTEEEE

David P. Vallett Nicholas Antoniou William E. Vanderlinde Jeremy Walraven Philippe Perdu General Chair Vice General Chair Technical Chair Tutorial Chair Tutorial Vice Chair IBM Systems & Consultant Laboratory for Sandia National Labs CNES Technology Physical Sciences Group

Chris Henderson Immediate Past General Chair

SemiTracks, Inc.

AAccttiivviittiieess CChhaaiirrss Zhiyong Wang User Groups Chair Intel Corporation Janet Teshima Local Arrangements Chair IBM Marsha Abramo Local Arrangements Vice-Chair

Dave Vallett EDFAS Liaison IBM Systems & Technology Group Chris Richardson Exposition Chair LSI Corporation Tracy Myers Publicity Chair ON Semiconductor Martin Keim Publicity Vice-Chair Mentor Graphics

Dan J. Bodoh Audio/Visual Chair Freescale Semiconductor Tom Woods Audio/Visual Vice-Chair Biotronic Ed Keyes Panels Chair Semiconductor Insights


v

ISTFA 2008 TUTORIAL COMMITTEE ISTFA 2008 Tutorial Program Chair Jeremy Walraven Sandia National Labs

Tutorial Committee Chair Topic Affiliation Cosme Furlong Fault Isolation, Failure Analysis Basics Worcester Polytechnic Institute

James Griffin Analog Device Failure Analysis Analog Devices

Leo G. Henry EOS/ESD, Failure Mechanisms ESD-TLP Consulting & Testing

Becky Holdford Packaging Texas Instruments

Susan Li Device and Memory FA Spansion

Tracy Myers Yield, Test and Logic Diagnostics ON Semiconductor

Chris Richardson Focused Ion Beam (FIB) LSI Logic Corporation

Rose M. Ring Device and Memory FA, Emerging Technologies AMD

Kendall Scott Wills Failure Analysis Basics Independent Consultant

Sam Subramanian Materials Characterization Freescale Semiconductor, Inc.

Jeremy A. Walraven MEMS Devices, Microscopy Tools Sandia National Laboratories

Zhiyong Wang Packaging, Lab Management Intel Corporation


vi

ISTFA 2008 SYMPOSIUM COMMITTEE

ISTFA 2008 Technical Program Chair

William E. Vanderlinde Laboratory for Physical Sciences

CIRCUIT EDIT BOBBY HOOGHAN, CHAIR Hooghan Consultancy & Services STEVE HERSCHBEIN, CO-CHAIR IBM Systems & Technology Marsha Abramo Steve Herschbein, IBM Mike Phaneuf, Fibics Inc. EMERGING CONCEPTS DAN BODOH, CHAIR Freescale Semiconductor MICHAEL BRUCE, CO-CHAIR AMD Alex VanVianen, Freescale Semiconductor Steve Kasapi, NVIDIA FAILURE ANALYSIS PROCESS 1&2 DAVID BURGESS, CHAIR Accelerated Analysis Pete Carelson, FEI Company Apek Mulay, Independent Consultant Johnny Lee, X-Fab Texas Randy Lee, Keithley Instruments Inc. METROLOGY JANET TESHIMA, CHAIR FEI Company JEREMY RUSSELL, CO-CHAIR Inotera Chas Archie, IBM Roger Alvis, Imago Loek Kwakman, FEI Company Barbara Miner, Intel Corp. Bart Rijpers, ASML

NANOPROBING SHAWN DECKER, CHAIR South Dakota School of Mines TAYLOR CAVANAH, CO-CHAIR Zyvex Instruments Terrence Kane, IBM Phil Kaszuba, IBM PACKAGE & ASSEMBLY LEVEL FA 1&2 DEEPAK GOYAL, CHAIR Intel Corporation ZEZHONG FU Intel Corporation Stephane Barbeau, IBM J. Robert Crawford, DoD Jessica Hoskins, The Aerospace Corp. on Ted Kolasa, Freescale Semiconductor, Inc. Andrew Mawer Freescale Semiconductor, Inc. Roger Stierman, Texas Instruments PHOTON BASED TECHNIQUES 1 STEPHEN IPPOLITO, CHAIR IBM AARON FALK, CO-CHAIR OptoMetrics, Inc. PHOTON BASED TECHNIQUES 2 FELIX BEAUDOIN, CHAIR IBM PHILIPPE PERDU, CO-CHAIR CNES Frank Zachariasse, NXP Semiconductors Alan Street, QUALCOMM, Inc Jerome Touzel, Infineon Technologies PHOTON BASED TECHNIQUES 3 STEPHEN IPPOLITO, CHAIR IBM KENDALL SCOTT WILLS, CHAIR Independent Consultant POSTERS KENDALL SCOTT WILLS, CHAIR Independent Consultant REENA CHANPURA, CO-CHAIR Texas Instruments

SAMPLE PREPARATION EFRAT RAZ-MOYAL, CHAIR Gatan Bernd Krüeger, Infineon Tech. Astrid Krehan David Su, TSMC David MacHahon, Micron Arthur Rawers, Xilinx, Inc. SPM PHIL KAZUBA, CHAIR IBM TERRY KANE, CO-CHAIR IBM Ben Schrag, Micro-Magnetics Jim Slinkman, IBM Pai Tangyunyong, Sandia SYSTEM LEVEL FA JAMES DEMERST, CHAIR IBM JEFF HARTSELL, CO-CHAIR Dell, Inc. Ted Levin, IBM Jeff Birdsley, Dell Carol Boye, IBM Ted Levin, IBM TEST BRADY BENWARE, CHAIR Mentor Graphics SHAWN BLANTON, CO-CHAIR Carnegie Mellon University Stephan Eichenberger, NXP Ken Butler, Texas Instruments John Carulli, Texas Instruments YIELD ENHANCEMENT SARMA GUNTURI, CHAIR Texas Instruments CATHY KARDACH, CO-CHAIR DCG Systems Alfredo Herrera, Spansion Yi Feng, IBM Cathy Kardach, DCG Systems


2009 FIRST ANNOUNCEMENT AND CALL FOR PAPERS

November 15-19, 2009McEnery Convention CenterSan Jose, California USA

“It’s All About Resolution”

35th International Symposium for Testing and Failure Analysis™

EDFAS 2008 Photo Contest Winner, First Place False Color: An EBSD (Electron Backscatter Diffraction) map of a wire bond, showing grain size and crystallographic grain orientation.

Nat

asha

Erd

man

and

Ver

n R

ob

erts

on,

JE

OL

US

A

Submit your abstract today.

Go to www.istfa.org.

Abstract Submisson Deadline:

April 3, 2009


ix

Contents

IPFA 08 Best Paper Effect of Refractive Solid Immersion Lens Parameters on the Enhancement of Laser Induced Fault Localization Techniques .................................... 1

S.H. Goh1, A.C.T. Quah1, C.J.R. Sheppard1, C.M. Chua2, L.S. Koh2, J.C.H. Phang1 (1) National University of Singapore, Singapore (2) SEMICAPS Pte Ltd, Singapore

Session 1: Emerging Concepts High Current Focused Ion Beam Instrument for Destructive Physical Analysis Applications ..................................................................... 7

P. Tesch, N. Smith, N. Martin, D. Kinion Oregon Physics LLC, Hillsboro, OR USA

Recent Developments in TEM Applications for the IC Industry .................................... 14

L.F. Fu, Y.C. Wang, B. Jiang, F. Shen, M. Strauss, B. Van Leer, C. Senowitz, A. Buxbaum FEI Company, Hillsboro, OR, USA

Automated Serial-Section Polishing Tomography ......................................................... 21

J.A. Hunt1, P. Prasad1, E. Raz2 (1) Gatan Research & Development, Pleasanton, CA, USA; (2) Gatan FA Products Division, Pleasanton, CA, USA

Applications of Scanning Near-Field Photon Emission Microscopy ............................ 25 D.V. Isakov1, B.W.M. Tan1, J.C.H. Phang1, Y.C. Yeo1, A.A.B. Tio2, Y. Zhang2, T. Geinzer3, L.J. Balk3 (1) National University of Singapore, Singapore; (2) Singapore Institute of Manufacturing Technologies, Singapore; (3) University of Wuppertal, Germany

Session 2: Packaging and Assembly Level FA I New Developments in High-Resolution X-ray Computed Tomography for Non- Destructive Defect Detection in Next Generation Package Technologies ........................................................................ 30

M. Pacheco, D. Goyal Intel Corporation,Chandler, AZ, USA


x

Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow .......................................... 36

Z. Wang, Sr. International Rectifier Corp., Temecula, CA, USA

PCB Pad Cratering – Characterization Techniques and Challenges ............................ 43

S. Parupalli1, K. Newman2, M. Ahmad3 (1) Intel Corporation, Hillsboro, OR, USA (2) Sun Microsystems, Sunnyvale, CA, USA (3) Cisco Systems, San Jose, CA, USA

Stitch-Bond-Shearing in Optoelectronic Devices, Caused by Lead-Free-Wave- Soldering – Do We Need Improved Wire-Bonding Methods? ................................................................................. 49

P. Jacob1, M. Rütsch2 (1) EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland, (2) Vossloh-Kiepe GmbH, Duesseldorf, Germany

Lead-Free Solder/Gold Metallization Interdiffusion in Electronic Interconnects – Challenges and their Control ............................................. 53

N. Asrar Schlumberger Technology Center, Sugar Land, TX, USA

Thick Film Resistor Failures ............................................................................................ 59

A. Shrivastava1, A. Amin1, B. Sood1, M. Azarian1, M. Pecht1, M. Zagami2 (1) University of Maryland, College Park, MD, USA (2) Fairchild Controls, Frederick, MD, USA

Session 3: Failure Analysis Process I

Active Voltage Contrast and Seebeck Effect Imaging as Complementary Techniques for Localization of Resistive Interconnections .............. 65

I. Österreicher, U. Rossberg, S. Eckl Infineon Technologies Dresden GmbH & Co., Dresden, Germany

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis ..................................................................... 70

K. Li, P. Liu, J. Teong, M. Lee, H.L. Yap Chartered Semiconductor Manufacturing Ltd., Singapore, Singapore

Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques .............................................................................75

Z.G. Song1, S.B. Ippolito1, P.J. McGinnis1, A. Shore1, B. Paulucci1, T. Kane1, M.P. Tenney1, F.G. Trudeau1, A.W. Kozaczka2 (1) IBM Systems and Technology Group, New York, NY, USA (2) IBM Systems and Technology Group, Essex Junction, VT, USA


xi

Physical Failure Analysis Techniques and Studies on Vertical Short Issue of 65 nm Devices ............................................................................ 79

P.K. Tan, Z.H. Mai, S.L. Toh, E. Hendarto, Q. Deng, Y.W. Goh, J.L. Cai, Y.Z. Ma, H.B. Lin, L. Zhu, J. Yu, H.L. Li, Q.F. Wang, R. He, H. Tan, J. Lam Chartered Semiconductor Manufacturing Pte. Ltd.

Fast Root Cause Analysis Based on Electrical Defect Localization ............................ 85

M. Schmidt1, L. Dworkin1, C. Hess2, M. Squcciarini2, S. Yu2, J. Burrows2 (1) FEI Company, Hillsboro, OR, USA (2) PDF Solutions Inc., San Jose, CA, USA

Failure Analysis for Gate Oxide Breakdown .................................................................. 88

X. Chen, M. Li, Q. Guo, K. Chien, Y.-B. Gao Semiconductor Manufacturing International Company, Shanghai, P.R.China

Session 4: Package and Assembly Level FA II

Non Invasive Failure Analysis of Passive Electronic Devices in Wireless Modules Using X-ray Micro Tomography (MicroCT) ...................................... 92

T. Pendleton1, L. Hunter2, S.H. Lau2 (1) RFMD, Greensboro, NC, USA (2) Xradia, Inc., Concord, CA, USA

Scanning Acoustic Microscopy for Solder Joint Failure Analysis and Design Improvements ............................................. 99

R. Varma, J. Bartolovitch, V. Brzozowski, C. Sokolowski Northrop Grumman Electronic Systems, Baltimore, MD, USA

Lock-In-Thermography for 3- Dimensional Localization of Electrical Defects inside Complex Packaged Devices ................................................ 102

C. Schmidt1, F. Altmann1, C. Grosse1, A. Lindner2, V. Gottschalk3, (1) Fraunhofer Institute for Mechanics of Materials, Halle, Germany (2) Micronas GmbH, Freiburg, Germany (3) Elmos Semiconductor AG, Dortmund, Germany

An Analytical Technique to Assess the Risk of Laser Damage to Encapsulated Integrated Circuits during Package Laser Marking ............................. 108

J. Patterson1, C. Schuring2 (1) Applied MicroCircuits Corporation, San Diego, CA, USA (2) Quantum Focus Instruments, Vista, CA, USA

Techniques for Identification of Silver Migration in Plastic Encapsulated Devices Assembled with Molding Compound Containing Red Phosphorus Flame Retardant Material ........... 112

R.R. Hylton Maxim Integrated Products, Hillsboro, OR, USA


xii

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components ................................ 121

N. Randall, R.P. Nair CSM Instruments, Needham MA, USA

Session 5: Circuit-Edit

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification ................................................................... 128

S.B. Herschbein, H.H. Kang, S.L. Jansen, A.S. Dalton IBM Systems & Technology, Hopewell Junction, NY, USA

An Analysis of Tungsten FIB-Fabricated Via Resistance ............................................ 133 D.W. Niles1, J. Meyer1, R.W. Kee1, M. DiBattista2 (1) Avago Technologies, Fort Collins, CO, USA (2) FEI Corporation, Hillsboro, OR, USA

Backside Circuit Edit on Full-Thickness Silicon Devices ............................................ 141 C. Rue1, S. Herschbein2, C. Scrudato2 (1) FEI Company, Hillsboro, OR, USA (2) IBM Corporation, Hopewell Junction, NY, USA

Insulator Deposition for Through Conductor Editing .................................................. 151

C. Richardson1, M. Martin1, T. Malik2, J.P. Barone2 (1) LSI Corporation, Fort Collins, CO, USA (2) DCG Systems, Fremont, CA, USA

Creation of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Backside Editing Techniques ....................................................... 157

P. Scholz1, U. Kerst1, C. Boit1, C.-C. Tsao2, T. Lundquist2 (1) Berlin University of Technology, Berlin, Germany (2) DCG Systems, Fremont, CA, USA

Session 6: Sample Preparation I

S/D LDD Junction Stain/Delineation by Electrochemical Displacement with Illumination ......................................................... 163

R.-L. Chiu, T. Chen, S. Chen WaferTech LLC Camas, WA, USA

A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam ................................................................................. 168

H.H. Kang1, M.A. Gribelyuk1, O.D. Patterson1, S.B. Herschbein1, C. Senowitz2 (1) IBM Microelectronics, Hopewell Junction, NY, USA (2) FEI Company, Hillsboro, OR, USA


xiii

Embedded Gold Markers for Improved TEM/STEM Tomography Reconstruction ......................................................................................... 172

J.-S. Luo, C.-C. Huang, J.D. Russell Inotera Memories, Inc., Taoyuan, Taiwan, Republic of China

Session 7: Photon Based Techniques I

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation ........................ 180

T. Kiyan1, C. Boit1, C. Brillert2 (1) Berlin University of Technology, Berlin, Germany (2) Infineon Technologies, Munich, Germany

Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation ................................................................. 188

J. Shaw1, C. McMahon1, Y.S. Ng2, F. Beaudoi2 (1) LSI Corporation, Fort Collins, CO, USA (2) DCG, Fremont, CA, USA

Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis ................................................................................ 193

Z. Qian, C. Brillert, C. Burmer (1) Infineon Technologies, Munich, Germany

Differentiation between Artifacts and True Defects in 45 nm BEOL Structures in M-TLS Technique .............................................................. 198

A. Reverdy1, P. Perdu3, M. de la Bardonnie1, H. Murray2, P. Poirier1, B. Domengès2 (1) NXP Semiconductors, Caen, France (2) LaMIPS, Laboratoire commun NXP-CRISMAT, Caen, France (3) CNES, Toulouse, France

Session 8: Scanned Probe Microscopy

Calibration of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) ..................... 204

T. Kane1, M.P. Tenney1, A. Erickson2, P. Harris2 (1) IBM Systems and Technology Group, New York, NY, USA (2) Multiprobe, Inc., Santa Barbara, CA, USA

Analysis of Deep Trench Node Leakage Depth by Applying Current Imaging Technique at Silicon Level ................................................ 209

S. Doering, M. Seitz, U. Zimmermann, P. Rodger, W. Werner Qimonda Dresden GmbH & Co. OHG, Dresden, Germany


xiv

Session 9: Photon Based Techniques II

Backside Failure Analysis by Electroluminescence on Microwave Devices ............. 214 M. Bouya1, D. Carisetti1, P. Delaqueze1, J.C. Clement1, N. Malbert2, N. Labat2, P. Perdu3 (1) Thales Research and Technology, Palaiseau, France (2) IMS Laboratory, Talence, France (3) CNES Laboratory, Toulouse, France

Photon Emission Spectral Signatures of AlGaN/GaN HEMT for Functional and Reliability Analysis ............................................................................... 220

A. Glowacki1, C. Boit1, R. Lossy2, J. Würfl2 (1) Berlin University of Technology, Berlin, Germany (2) Ferdinand Braun Institut für Höchstfrequenztechnik, Berlin, Germany

Laser Scanning Localization Technique for Fast Analysis of High Speed DRAM Devices ................................................................ 227

M. Versen1, A. Schramm1, J. Schnepp1, S. Hoch1, T. Vikas1, D. Diaconescu2 (1) Qimonda AG, Neubiberg, Germany (2) Infineon AG, München, Germany

Novel Application of the OBIRCh Amplifier for Timing Failure Localization ............................................................................................ 233

M. Sienkiewicz1, S. Brule2, P. Perdu1, A. Firiti2, O. Crepel2 (1) CNES - French Space Agency, Toulouse, France (2) Freescale Semiconductor, Toulouse, France

Session 10: Posters

Novel Sample Preparation Technique for Backside Analysis of Singulated Die ............................................................................238

S. Elliott, M. LaPierre, P. Plourde Fairchild Semiconductor, South Portland, ME, USA

Innovative Method & Use of UV Technologies for Dye Penetrant Sample Preparation ...............................................................................242

T.R. McDonald Intel Corporation, Hillsboro OR, USA

The Failure Analysis of Specific Source-to-Drain Dislocation and Case Study ...................................................................................................................... 245

C.H. Wang, S.W. Lai, C.Y. Wu, B.T. Chen, J.Y. Chiou, J.H. Chou Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, R.O.C.

Next Generation Laser Voltage Probing .......................................................................249

Y.S Ng, W. Lo, K. Wilsher DCG Systems, Inc., Fremont, CA, USA


xv

A Study of the Photoelectric Effect Caused by a Laser Beam Used in a Beam Bounce Technique in a C-AFM System ....................... 256

H.-S. Lin, M.-S. Wu United Microelectronics Corporation, Ltd. Taiwan, R.O.C.

Applications of C-AFM and CBED Techniques to the Characterization of Substrate Dislocations Causing SRAM Soft Single-Column Failure Contained in a Wafer with (001) Plane/[100] Notch ..................................................... 260

H.-S. Lin, T.-H. Chen, W.-C. Shu United Microelectronics Corporation, Ltd., Taiwan, R.O.C.

Electroluminescence Analysis by Precise Tilt Polish Technique of Edge-Emitting Laser Diode ............................................................................................ 265

H. Ichikawa, K. Sasaki, K. Hamada, A. Yamaguchi Sumitomo Electric Industries, Ltd., Japan

A Novel OBIRCH Fault Isolation Method to Locate the Leakage Failure Point ......... 269

C.-L. Huang ,Y.H. Shu United Microelectronics Corporation, Ltd., Taiwan, R.O.C.

Case Study of High Temperature Failure Analyses Using an On-Chip “Heater” ............................................................................................ 273

F. Zhang, C. Lewis, T. Duryea Texas Instruments Inc., Dallas, TX, USA

Development of PECS Application for Sample Preparation ....................................... 277

X. Chen, M. Li, Q. Guo, W.T. Kary Chien Semiconductor Manufacturing International Company, Shanghai, P.R. China

Automated Sample Preparation of Packaged Microelectronics for FESEM .............. 280 R.R. Cerchiara, P.E. Fischione, M.F. Boccabella, A.C. Robins E. A. Fischione Instruments, Inc., Export, PA, USA

Studies of Fluorine-Induced Corrosion and Defects on Microchip Al Bondpads and Elimination Solutions ..................................................... 285

H. Younan, N.R. Rao, T. Jennifer Chartered Semiconductor Manufacturing Ltd., Singapore, Singapore

Optimization of SEM Analytical Conditions for Low K and Ultra Low K Dielectric Materials ................................................................. 291

L. Binghai, M. Zhiqiang, H. Younan, T. Jennifer Chartered Semiconductor Mfg. Ltd., Singapore

Using Cross-Triggering in Oscilloscope for Debugging Multiphase Converter Circuit of Personal Computer (PC) Motherboard ......................................................................... 294

B. Nguyen, O. Diaz Intel Corporation, Hillsboro, OR, USA


xvi

Doping Profile Measurements in a 65-nm Commercial Product Using Atom Probe Tomography ............................................................................................... 297

L. Klibanov1, D. James1, D. Isheim2 (1) Chipworks Inc., Ottawa, Ontario, Canada (2) Northwestern University Center for Atom-Probe Tomography (NUCAPT), Evanston, IL, USA

Failure Analysis of Nitride-Trapping Memory Cell Failures ........................................ 301

W.-R. Chen, Y.-J. Chen, I.-C. Chang, H.-H. Chiang, L.-K. Kuo, S. Yin, C.-Y. Lu Macronix International Co., Ltd., Hsinchu, Taiwan

Advanced Methodologies for Backside Circuit Edit .................................................... 305

E. O’Donnell1, D. Scott1, T. Malik2, R. Jain2, T. Lundquist2, R. Schlangen3, U. Kerst3, C. Boit3 (1) Intel Corporation, Folsom, CA, USA (2) DCG Systems, Fremont, CA, USA (3) Berlin University of Technology, Berlin, Germany

Physical Failure Analysis Techniques Using 3D Rotation Imaging Method by STEM ......................................................................... 315

T.-S. Back, J.-H. Kim, S.-J. Lee, J.-W. Jung, T.-O. Jung, H.-J. Kim, S.-Y. Lee Hynix Semiconductor Inc., Ichon-si, Kyoungki-do, Korea

High Precision Ion Beam Milling with Time of Flight Compensation ......................... 317

T. Holtermann, A. Graupera, S. Rosenberg, M. DiBattista FEI Company, Hillsboro, OR, USA

Applications of In-situ Sample Preparation and Modeling of SEM-STEM Imaging ........................................................................................................ 320

R.J. Young1, A. Buxbaum1, B. Peterson1, R. Schampers2 (1) FEI Company, Hillsboro, OR, USA (2) FEI Company, Eindhoven, The Netherlands

Sample Preparation Technique for Bond Pad IMD (Inter-Metal Dielectric) Damage Observation ...................................... 328

Y.S. Huan, Y.L. Kuo, Y.T. Lin, J. Chen, K.Y. Lee Taiwan Semiconductor Manufacture Company, Ltd. Hsinchu, R.O.C.

Session 11: System Level Failure Analysis

Dynamic Laser Stimulation Technique for Device Qualification Process ................. 332 A. Deyine-Barth1, P. Perdu1, G. Benetti1, K. Sanchez1, F. Battistella1, D. Lewis2 (1) CNES & THALES Laboratory, Toulouse Cedex France (2) IMS, Talence Cedex, France


xvii

Lead Frame Metal Migration in an Encapsulated IC Package ..................................... 339 W. Eslinger Boston Scientific, St. Paul, MN, USA

Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis .............................................................................................................. 344

H.-Y. To, D. Nguyen, C. Dunn, D. Davis Texas Instruments Inc., Houston, TX, USA

Reliability for Pure CMOS One-Time Programmable Memory Using Gate-Oxide Anti-Fuse (eFuse) ....................................................................................... 349

N. Wakai Toshiba Corporation, Yokohama, Japan

Laser Failure Isolation Techniques Demonstrated On Test Structures ..................... 354

F.S. Arnold Texas Instruments, Dallas, TX, USA

Session 12: Sample Preparation II

Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering ..................................................................... 363

T. Moor1, E. Malyanker2, E. Raz-Moyal2 (1) Datel Design and Development Ltd, Stone, Staffs, UK (2) Gatan, Pleasanton, CA, USA

Characterization and Failure Analysis of Wafer Bonded Devices and Unfilled Through-Silicon-Vias (TSVs) ........................................................................... 368

C. Cassidy1, J. Kraft1, G. Koppitsch1, E. Brandlhofer1, M. Steiner1, F. Schrank1, D. Erwin2, E. Raz-Moyal2 (1) austriamicrosystems AG, Graz, Austria (2) Gatan Inc., Pleasanton, CA, USA

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages ........................................................................................... 375

P. Schwindenhammer, H. Murray, P. Descamps, P. Poirier NXP Semiconductors, Caen, France

Session 13: Test

Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE ....................... 383

C. Burmer1, R. Guo2, W.-T. Cheng2, X. Lin2, B. Benware2 (1) Infineon Technologies, Munich, Germany (2) Mentor Graphics Corp., Wilsonville, OR, USA


xviii

Improving Fault Isolation Using Iterative Diagnosis .................................................... 390 K. Gearhardt1, C. Schuermyer2, R. Guo 2 (1) LSI Logic Corporation, Ft. Collins, CO, USA (2) Mentor Graphics Corporation, Wilsonville, OR, USA

Deterministic Localization and Analysis of Scan Hold-Time Faults ........................... 396

J. Hwang1, D. Kim1, N. Seo1, E. Lee1, W. Choi1, Y. Jeong1, J. Orbon2, S. Cannon2 (1) Samsung Electronics Co., Ltd., Youngin-City, Gyeonggi-Do, Korea (2) Verigy Inc – Inovys DfX Solutions, Pleasanton CA, USA

Session 14: Photon Based Techniques III

Combining Refractive Solid Immersion Lens and Pulsed Laser Induced Techniques for Effective Defect Localization on Microprocessors ...................................................... 402

A.C.T. Quah1, S.H. Goh1, V.K. Ravikumar2, S.L. Phoa2, V. Narang2, J.M. Chin2, C.M. Chua3, J.C.H. Phang 3 (1) National University of Singapore, Singapore (2) Advanced Micro Devices Pte. Ltd, Singapore (3) SEMICAPS Pte. Ltd., Singapore

Evaluating PICA Capability for Future Low Voltage SOI Chips .................................. 407

F. Stellari1, P. Song1, J. Vickers2, C. Shaw2, S. Kasapi3, R. Ispasoiu4 (1) IBM T.J. Watson Research Center, Yorktown Heights, NY, USA (2) DCG Systems, Fremont, CA, USA (3) NVIDIA Corp., Santa Clara, CA, USA (4) Fairchild Imaging, Milpitas, CA, USA

Session 15: Nanoprobing

An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices ............................................................................................... 417

H.-S. Lin, C.-M. Chen United Microelectronics Corporation, Ltd., Taiwan, R.O.C.

Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique ............................................................................................... 423

S.M. Kim, J.H. Lee, J.H. Lee, H.K. Kim, M.S. Chang, J.H. Lee, S.J. Hong Hynix Semiconductor Inc., Kyoungki-do, Korea

Low Voltage, Low Current AFP Characterization of Non-Visible Soft Transistor Defects .............................................................................. 428

R. Mulder, S. Subramanian, T. Chrastecky Freescale Semiconductor, Inc., Austin, TX, USA


xix

Characterization and Analysis of 45nm Node SRAM Standby Leakage .................... 437 D.E. Albert, Z.G. Song, S.B. Ippolito, L. Fischer, M.P. Tenney IBM, Hopewell Junction, NY, USA

Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing ................................................................................ 445

E. Hendarto, S.L. Toh, P.K. Tan, Y.W. Goh, J.L. Cai, Y.Z. Ma, Z.H. Mai, J. Lam, J. Sudijono Chartered Semiconductor Manufacturing Ltd., Singapore

Session 16: Yield Enhancement

Oxidation of TiN ARC Layer as a Reliability Issue for ICs .......................................... 449

M. McVeigh1, A. Raz1, W.J. Kindt1, A. Gomes1, K.Y. Wong1, T. Inamine1, T.J. Bold2 (1) National Semiconductor, Santa Clara, CA, USA (2) Bold Productions, Roanoke, TX, USA

Timing Problems Due to Spacer Bridging in a Sub-100 nm Product ......................... 459

J. van Hassel NXP Semiconductors, Nijmegen, Netherlands

A Study of Pad Contamination Defect and Removal ................................................... 464

K.A. Mohammad, L.J. Liu, S.F. Liew, S.F. Chong, D.G. Lee, S.F. Lee and B.C. Lee X-Fab Sarawak SDN. BHD., Kuching, Sarawak, Malaysia

A Study to Remove Heavy Polymer Remain on Thick Metal (> 3 micron) Sidewall Profile after Metal Etch Solvent Clean Step .................................................. 468

S.F. Liew, K.A. Mohammad, L.J. Liu, S.F. Chong, D.G. Lee, S.F. Lee, B.C. Lee X-Fab Sarawak SDN. BHD., Kuching, Sarawak, Malaysia

Yield Enhancement Using a Combination of Wafer Level Failure Analysis and Defect Isolation Software: Case Studies ...................................................................... 471

P. Simon1, M. Thétiot1, B. Picart1, C. Kardach2, H. Deslandes2, F. Dudkiewicz3, J.-P. Roux4 (1) Atmel, Rousset, France (2) DCG Systems, CA, USA (3) Credence Systems Corporation, France (4) Sector Technologies SAS, France

Session 17: Failure Analysis Process II

A Procedure for Identifying the Failure Mechanism Responsible for a Pin-To-Pin Short Within Plastic Mold Compound Integrated Circuit Packages ........ 476

C. Nail, J. Rocha, L. Wong National Semiconductor Corporation, Santa Clara, CA, USA


xx

Mis-identified Failures in FETs ...................................................................................... 481 M. Gores, Hi-Rel Laboratories, Spokane, WA, USA

Frontside and Backside Analysis of Surface ESD ....................................................... 485

D. Daly, L. Grogan, F. Keating, Xilinx, Ireland

Intermittent Failures, Challenges and Strategies Involved with Finding Root Cause ........................................................................................................ 490

N. Konkol Intel Corporation

Transient Latch-Up Analysis of Power Control Device with Combined Light Emission and Backside Transient Interferometric Mapping Methods ................................................................................. 493

M. Heer1, D. Pogany1, M. Street2, I. Smith2, F. Riedlberger2, D. Bonfert3, H.A. Gieser3 (1) Vienna University of Technology, Vienna, Austria (2) Diodes Incorporated, Oldham, United Kingdom (3) PS ATIS Analysis & Test of Integrated Systems, Munich, Germany

Session 18: Metrology

3D STEM Tomography Based Failure Analysis of 45 nm CMOS Devices .................. 499 F. Lorut1, D. Delille2 (1) STMicroelectronics, Crolles, France (2) FEI Company, Eindhoven, The Netherlands

Dopant Analysis on Advanced CMOS Technologies ................................................... 505

F. Siegelin, A. Dübotzky, B. Danzfuss, S. Schömann Infineon Technologies, Munich, Germany

SEM Si Dopant Contrast Enhancement Using Sample Charging ............................... 510

Y.-W. Hsieh, J.D. Russell, P.-Y. Chen Inotera Memories, Inc., Taiwan, Republic of China

3-D Image Reconstruction in the Scanning Electron Microscope .............................. 515

W.E. Vanderlinde Laboratory for Physical Sciences, College Park, MD, USA

Author Index .................................................................................................................... 525


ASM International is the society for materials engineers and scientists, a worldwide network dedicated to advancing industry, technology, and applications of metals and materials. ASM International, Materials Park, Ohio, USA www.asminternational.org

This publication is copyright © ASM International®. All rights reserved. Publication title Product code ISTFA 2008 02210Z To order products from ASM International:

Online Visit www.asminternational.org/bookstore

Telephone 1-800-336-5152 (US) or 1-440-338-5151 (Outside US)

Fax 1-440-338-4634

Mail Customer Service, ASM International 9639 Kinsman Rd, Materials Park, Ohio 44073, USA

Email [email protected]

In Europe

American Technical Publishers Ltd. 27-29 Knowl Piece, Wilbury Way, Hitchin Hertfordshire SG4 0SX, United Kingdom Telephone: 01462 437933 (account holders), 01462 431525 (credit card) www.ameritech.co.uk

In Japan Neutrino Inc. Takahashi Bldg., 44-3 Fuda 1-chome, Chofu-Shi, Tokyo 182 Japan Telephone: 81 (0) 424 84 5550

Terms of Use. This publication is being made available in PDF format as a benefit to members and customers of ASM International. You may download and print a copy of this publication for your personal use only. Other use and distribution is prohibited without the express written permission of ASM International. No warranties, express or implied, including, without limitation, warranties of merchantability or fitness for a particular purpose, are given in connection with this publication. Although this information is believed to be accurate by ASM, ASM cannot guarantee that favorable results will be obtained from the use of this publication alone. This publication is intended for use by persons having technical skill, at their sole discretion and risk. Since the conditions of product or material use are outside of ASM's control, ASM assumes no liability or obligation in connection with any use of this information. As with any material, evaluation of the material under end-use conditions prior to specification is essential. Therefore, specific testing under actual conditions is recommended. Nothing contained in this publication shall be construed as a grant of any right of manufacture, sale, use, or reproduction, in connection with any method, process, apparatus, product, composition, or system, whether or not covered by letters patent, copyright, or trademark, and nothing contained in this publication shall be construed as a defense against any alleged infringement of letters patent, copyright, or trademark, or as a defense against liability for such infringement.

conference proceedings from the 34th international symposium for

Documents