configurable 8-bit microcontroller ip core as a basis for effective system on chip implementation

7/26/2019 Configurable 8-Bit Microcontroller Ip Core as a Basis for Effective System on Chip Implementation

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CONFIGURABLE 8-BIT MICROCONTROLLER IP COREAS A BASIS FOR EFFECTIVE SYSTEM ON CHIP IMPLEMENTATION

Maciej Pyka*), Wojciech Sakowski**)

*) Evatronix S.A. Electronic Design Department

Dubois 16, 44-100 Gliwice, POLAND [email protected]

**) Institute of Electronics, Silesian University of Technology Akademicka 16, 44-100 Gliwice, POLAND

[email protected]

Abstract: This paper explains why the 8-bit microcontroller IP cores are still popular insystem on chip designs. It presents R8051XC configurable microcontroller core(developed at Evatronix SA) with a focus on the implemented enhancements of this

popular instruction set architecture and on the configurability of the core. Formicrocontrollers embedded in ASIC or ASSP circuits effective support for softwaredevelopment is very important. Therefore on chip debug support (OCDS) solutionsdeveloped for R8051XC are presented along with prototyping environment and real timeoperating system port available for R8051XC follows. Finally application specific

solutions based on R8051XC and oriented towards USB-interfaced and Ethernet-interfaced systems have been presented. Copyright 2002 IFAC

Keywords: IP cores, electronic virtual components, design reuse, hardware descriptionlanguages, 8051 compliant ISA (instruction set architecture), microcontrollers,microcontroller applications

1. INTRODUCTION

Some form of design reuse takes place in more than80 per cent of system on chips designed nowadays.This is not only true for highly complex, multimillion

gate leading edge designs but also for much moremodest (in terms of complexity and performance)applications for which 8-bit microcontrollers are stillgood enough as main control and computing engines.

It should be noted though that a range of applicationsthat can be served by 8-bit microcontrollers have beenvastly extended due to increased processing poweroffered by IP cores based on classic 8-bit instructionset architectures. This is a result of optimizedarchitectures as well as higher circuit performanceachievable in the newer semiconductor processes. ForR8051XC this performance gain when compared to

original 8051 Intel chip running at 12 MHz may behigher than 100 (depending on target technology).

This is why the popularity of 8-bit microcontroller IPcores is still high. They are used in applications wherethe complexity still counts (despite perception thatsilicon surface is now for free). Therefore anyunnecessary part of microcontroller should be

removed to avoid waste of space. The concept ofconfigurable microcontroller was conceived atEvatronix long time ago (Bandzerewicz andSakowski, 1999). However, only recently, with alaunch of R8051XC core a fully automatedconfiguration process was made possible. No manualchanges are required to the code source files to adaptthe actual microcontroller core feature set to its userneeds and to remove all what is unnecessary for a

particular application.

The design reuse is all about minimizing the effortnecessary to integrate given set of functions intolarger design. We assume here that such design is asystem on chip.


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Major part of such effort nowadays is allocated tosoftware development. Debugging and testing of suchsoftware running in a target hardware environmentrequires access to CPU resources. But microprocessorand microcontroller cores embedded in ASICs orASSPs may offer no access to CPU buses. Knownapproaches (Nexus standard, 1999) to that problem

propose use for instance JTAG interface and on chipcircuitry to support software debugging. Solutionsdeveloped for R8051XC enables user to use industrystandard C compiler and debugger (Keil uVison IDE)while developing and debugging application software.

Developing of multithreaded control applications may be easier if proven real time operating system forms a backbone for the software architecture. Thereforeavailability of a prototyping environment with anRTOS (Labrosse, 2002) ported to it makesdevelopment of applications for R8051XC easier.

For many control systems connectivity to theirenvironment supporting particular protocols may bean important requirement. For instance, consumerapplications may need support for USB interfacewhile for some control applications ability to senddata over Ethernet cable and support TCP/IP protocolor CAN bus may be crucial. Providing pre-integratedsolutions built of hardware and software thatimplement such connectivity further reduce the effortof system on chip developers.

2. EXTENSIONS TO THE ORIGINAL 8051MICROCONTROLLER FEATURE SET

2.1 Enhancing performance of the 8051 instruction set architecture

The major improvements to 8051 instruction setarchitecture were implemented as early as in 1999,during development of R80515 microcontroller core.It implemented peripheral set that was a mixture of

peripherals from 80535 and 80537 chips oncemanufactured by Siemens Semiconductors. It was

presented briefly in (Bandzerewicz and Sakowski,1999). One year later the same CPU was used as a

basis for R8051 microcontroller core that differedfrom the R80515 by peripheral set which matchedexactly that of original Intel chip.

The improvements were based on the fundamentalreduction of the number of clock cycles necessary toexecute each instruction. A single clock cycle FETCH

phase is interleaved with the last clock cycle of theexecution phase of the previous instruction. Thenumber of clock cycles necessary to implement eachinstruction is only limited by the number of memoryread/write cycles. Performance improvement close tothe factor of eight over original architecture running

at the same clock speed is achieved this way. Amultiplying dividing unit (MDU) may be added toenhance some arithmetic operations on 16 bit data.

R8051XC did not introduce major improvements tothis architecture, although execution of a fewinstructions was further enhanced. More advanced isexpected from a pipelined version of 8051 ISA whichis under development now and should bring 50%

performance increase when compared to R8051XC.

Fig 1. Block diagram of R8051XC microcontrollerIP core.

2.2. Enriched peripheral set.

Apart from optimization of instruction executionmajor extensions to the original 8051 architectureinclude configurable interrupt and DMA controllersas well as advanced power management options.Configurable interrupt controller enables the user tochoose (with certain restrictions) a number ofavailable priority levels and interrupt sources. One ofthe power management options is based on separationof CPU and peripheral clock domains with ahandshake-based synchronization between them.

R8051XC enables to tune the peripheral set to userneeds. In addition to the standard peripherals(timers, uarts, watchdog timer) SPI and I2Ccontrollers can be added too.

Special Function Registers

PORTS

p1p2p3

SERIAL0

s0con s0buf

PMURSTCTRLWAKEUPCTRLSYNCNEG

R8051XC_CPU

accb

pswdptrpc

ExternalMemory

Interface

Timer 0inputs

dptr1dps

On-ChipMemory/SFR

Interface

OCI Interface

P e r

i p h

e r a

l c

l o c

k

g a

t e c

t r l .

P e r

i p h

e r a

l c

l o c

k

E n g

i n e

c l o

c k

g a

t e

c t

r l .

E n g

i n e

c l

o c

k

Clock

Hardware

reset

Port 0Port 1Port 2Port 3

Constant elements

p0

Serial 0Interface

TIMER2

4 x

C C U P O R T

t2con

tl2 th2

crch crcl

ccl1

ccl2

cch3

cch1

ccl3

cch2

WATCHDOGwdtrel

Timer 2inputs

Watchdoginput

MDU

md0

md1

md2 md4

md5md3

arcon

SERIAL1

s1con s1bufSerial 1Interface

Configurable elements

Optional elements

51-like

ipien

ExternalInterrupt

inputs

515-like

ip0ien0

ip1ien1 ien2

One of two possible components

ISR

I2C i2cconI2C Interface

SPI_MS

spstaSPI Interface

i2cdat i2cadr

i2csta

spcon spdat

sp

pconckcon

TIMER0

tl0 th0 tcon tmod

Timer 1inputs

TIMER1

t l1 th1 tcon tmod

spssn

EXTINTtcon ircon ircon2

SFRMUX

clock sync

OCDS

OCDS Interface


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2.3 Testing & testbench

During development of R8051XC a personalhardware modeler (Pyka M et al., 2003) was used toregister behavior of a chips based on 8051architecture.

Major challenge in developing the testbench forR8051XC was to achieve automatic configuration ofthe testbench and the testsuite. It was achieved,although the current state of the testbench is still notsatisfactory due to high dependency of peripheraltesting on the timing of instruction execution. Slightchanges in the CPU timing require important changesof many test cases.

2.4 Adding configurability

Every second sale of our products from 8051 familyinvolved a customization which required removingsome standard peripherals and / or adding some thatextended original architecture to match current needs(like I2C, SPI or in some cases USB devicecontrollers or Ethernet MAC).

The idea of adding configurability to themicrocontroller core was introduced pretty early(Bandzerewicz and Sakowski, 1999), but it was notavailable as an automated solution till recently, with alaunch of a configurable microcontroller core basedon 8051 instruction set architecture. We named itR8051X-C. It is based on our best selling R8051 andR80515. These two shared the same CPU design anddiffered with peripheral set that was derived fromIntel and Siemens chips respectively.

Fig 2. GUI version of configurator enables easy

definition of required microcontroller features..

Tcl based configurator enables customer to composea peripheral set that meets exactly his/her needs. Once

the parameters are set the configurator produces proper set of RTL files and what is even moredifficult to do by hand configures also the testbenchto work with that particular configuration of the core.Graphical User Interface is also available to makechoosing the configuration easier (Fig. 2).

Along with peripheral set quite a few other importantfeatures of the 8051 architecture are configurable inR8051X-C. The configurable capabilities cover(Fig. 1):

size of external program memory (64kB up to8 MB)

number of DPTR registers: 1, 2 or 8 two types of interrupt controller:

- interrupt sources: 0..6, externalinterrupts: 0..2, priority levels: 2 or

- interrupt sources: 0..8, externalinterrupts: 0..13, priority levels: 4

MUL, DIV, DA instructions implemented or

not separate Multiplication-Division unit: 0 or 1 number of 8-bit I/O ports: 0 ... 4 number of 16-bit timers: 0, 1, 2 or 3 number or serial ports: 0, 1 or 2 Watchdog timer: 0 or 1 I2C master-slave interface: 0 or 1 SPI master-slave interface: 0 or 1 On chip debug support options: none or

interface to FS2 OCI (connected externally tothis interface) or Evatronix OCDS circuitry.

R8051XC was to achieve automatic configuration ofthe testbench and the testsuite. It was achieved,although the current state of the testbench is still notsatisfactory due to high dependency of peripheraltesting on the timing of instruction execution. Slightchanges in CPU timing require important changes ofmany test cases.

3. ON CHIP DEBUG SUPPORT

Our JTAG-based circuitry was inspired by the Nexusstandard (Nexus 1999), known also as IEEE ISTO5001 It consists of JTAG controller that enables

passing control messages to chip and retrieveinteresting data and the circuit that controls the CPUin the debugging mode (it is called OCDS for on-chipdebug support).

Thanks to well defined application programminginterfaces of the debugger from Keil we coulddevelop a software layer (called EDI for Evatronix

Debug Interface ) that interfaces this debugger to ouron chip debug supporting (OCDS) circuit (Fig. 3).

For the moment the following debugging capabilitiesare available:

Stop, Run, Step, Reset program Unlimited number of software breakpoints to

stop program execution on code fetches.


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Limited number of hardware breakpoints to

stop program execution on code fetch, data,xdata, idata read/write access with value andaddress range comparisons,

Code, data, sfr, xdata memory full read/writeaccess.

Fig 3. Architecture of debugging solution combiningsoftware and on chip hardware.

Many of these functions as well as the number ofhardware breakpoints are configurable allowing theuser to trade space for debugging capabilities.Different OCDS configurations may be used forFPGA based prototype and final ASIC.

Fig 4. OCDS circuitry links embedded processorto software development environment

R8051XC core may be also configured to work the onchip debugging instrumentation (OCI) from FirstSystem Silicon (FS2) is available as an alternative tousing Evatronix OCDS solution. This solution

provides tracing capabilities while for EvatronixOCDS simple trace functionality is going to be addedin the near future.

4. DEVELOPMENT ENVIRONMENT

An important part of the overall design time reductionthat can be achieved by use of a microcontroller IPcore depends on the ease of use of an available

prototyping system and availability of supportingsoftware.

A prototyping board called EB5 tiny was developed toenable easy prototyping of systems build aroundR8051XC. The board may be interfaced to daughter

boards containing FPGAs and transceiversimplementing different available options forconnectivity. Additional plug-in modules can bedeveloped to enable prototyping of applicationspecific features (like circuits needed to interfacedifferent kind of sensors to R8051XC).

Micriums uC OS II (Labrosse, 2002) real timeoperating system was ported to R8051XC prototypedin the EB5-tiny environment. A set of example driversrunning under this RTOS is delivered with the core.Availability of the RTOS and driver library furtherreduce the effort related to development ofapplications for R8051XC.

In order to further cut the time of development ofsystem-on-chip based on R8051XC a software driversfor I2C and SPI controllers are available for thoseusers that need them in their applications.

5. REFERENCE DESIGNS OFFER SUPPORT FORPOPULAR CONNECTIVITY STANDARDS

There are USB device controllers (supporting fullspeed and high speed transfers and a few versions of

USB On The Go controllers) as well as EthernetMedia Access Controllers (both 10/100 Mhz and1 GHz versions) in the Evatronix product portfolio.While most of the versions of these controllers areoriented towards high performance applications (e.g.they are equipped with AMBA interface to be easilyintegrated in ARM-based systems) there is a few thatare well suited for lower end embedded systems.

As such controllers were available, it was logical stepto define extensions to the R8051XC platformdiscussed in the previous section to support pre-integrated connectivity solutions based on USB and

Ethernet standards. Such solutions are often neededfor consumer products (e.g. MP3 pleyer with USBinterface) or medical or industrial applications (smallcontroller with Ethernet connection) .

FPGA - basedprocessor prototype

plugged into theprototyping board

3rd part IDE interfacedto hardware prototype

by means of EDI(Evatronix Debug

Interface) software layer

CPU

OCDS JTAG

EDI

3 rd PARTY DEBUGGER


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5.1 USB connectivity

Among USB device controllers available threeversions were chosen for integration into R8051XC

platform: CUSB (supporting full speed transfers),CUSB2 (supporting FS / HS transfers with FIFOinterface) and a customized version of the latter coreequipped with USB protocol aware DMA controller.Pre-integrated miniplatforms for USB-connectedapplications based on this IP cores were defined andtested.

It should be noted that a large part of USB protocol isimplemented in software organized in a layersforming so called USB software stack. Generalimplementation of this software developed atEvatronix was meant for 32-bit applications, so it wasnecessary to optimize it in order to run effectively onan 8-bit microcontroller.

5.2 Embedded Internet connectivity

Ethernet MAC (Media Access Controller) coresavailable in Evatronix product portfolio, being meantfor higher bandwidth applications, are generally notwell suited for 8-bit systems. On the other hand thereis an obvious need for Ethernet based connectivityeven for small control systems. Ability to readcontrolled system parameters or to set them viaregular web browser running or PC is a veryattractive feature. Therefore a simple version ofEthernet MAC was developed (known as MAC-LIP core) that provides an 8-bit FIFO interface to thehost processor (i.e. R8051XC microcontroller core).It was enhanced with hardware accelerator of CRCsum generation / analysis.

Fig 5. Reference design integrating R8051XC corewith Ethernet media access controller andsupporting software

CMX company offers a software library (Stephens,2002) that supports tcp/ip and http protocolsoptimized for 8051-based systems. Evatronix adoptedthis library to make use of the above mentionedhardware support for check sum generations /analysis. Such approach resulted in solution that

provides R8051XC-based systems with Ethernetconnectivity and full tcp/ip and http protocol supportwith minimal impact on the system performance, asthe time-consuming calculations related to CRCgeneration/analysis are implemented in hardware.

6. CONCLUSIONS AND FURTHERDEVELOPMENT DIRECTIONS

Configurability of the peripheral set and a few otherfeatures of R8051XC microcontroller core makes itsoptimization for a particular application easy. Effortneeded for development of an integrated system

based on this core is reduced thanks to its debuggingcapabilities, availability of prototyping environmentand pre-tested software. Development of applicationsthat require presence of popular connections (likeUSB or Ethernet) is simplified with existing referencedesigns.

There are two ongoing development projects based on8051 architecture at Evatronix. One is aimed atoptimization of the 8051 CPU towards higher

performance, the other towards lower gate countand lower power consumption. Future availability ofthese optimized CPUs will increase availablespectrum of options for potential systems based oneight bit microcontroller.

It has been recognized though that the currenttestbench and test suite is not well suited toaccommodate changes of instruction executiontiming. Therefore the major part of the futuredevelopment effort will be aimed at removal of stricttiming relationships between the operation of CPUand peripherals. Assertion based verification will bedeployed to solve this problem.

REFERENCES

Bandzerewicz M., W.Sakowski (1999) Developmentof the configurable microcontroller core,

Proceedings of the FDL'99 Conference , LyonThe Nexus 5001 Forum Standard for a Global

Embedded Processor Debug Interface, IEEE-ISTO, 1999

Pyka M., W. Sakowski, W. Wrona (2003).Developing the concept of hardware modeling toenhance verification process in virtualcomponent design, Proceedings of IEEEWorkshop on Design and Diagnostics of

Electronic Circuits and Systems , Poznan, 2003Labrosse J. (2002). MicroC/OS II The Real-Time

Kernel, Second Edition, CMP Books LawrenceSakowski W., M. Pyka (2005). From Obsolete Part

Replacement To Enhanced LegacyMicroprocessor Architectures, Proceedings of

IP/SoC2005: IP Based SoC Design Conference,Grenoble , Dec. 2005

Stephens C. L. (2002). TCP/IP - An Introduction for 8& 16 bit Microcontroller Engineers ( issued byComputer Solutions Ltd. )

R8051XC

CRChw acce l

EthernetMAC

Ethernetnetwork

CMX software(tcp/ip etc.)

CRCplug-inUser

application

configurable 8-bit microcontroller ip core as a basis for effective system on chip implementation

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