conformal computing program july 26, 2007
DESCRIPTION
Conformal Computing Program July 26, 2007. NDSU Center for Nanoscale Science & Engineering. Center for Bits and Atoms MIT Media Lab. CNSE CC Team. (not pictured: Ahana Gosh and Jordan Dahl). Wallpaper Computing Display. Extensible Medium Integrated Computation and Display - PowerPoint PPT PresentationTRANSCRIPT
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Conformal Computing ProgramJuly 26, 2007
NDSU Center for Nanoscale Science & Engineering
Center for Bits and AtomsMIT Media Lab
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CNSE CC Team
(not pictured: Ahana Gosh and Jordan Dahl)
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Wallpaper Computing Display
• Extensible Medium
• Integrated Computation and Display
• Flexible Substrate
• Similarities to Wallpaper
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WCD Prototypes
• Rigid 2x2 and 8x8 Prototypes
• Strip Concept
• Strip Prototypes
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2x2 Prototype
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Each processor scans 48 LEDs …
Processor + R’s + C
4 x 4 RGB Pixels
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… and connects to 4 neighbors.
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8x8 Prototype (1 processor and 16 pixels / cm2)
computing side display side
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Chassis
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Strip Concept
• Uses only two metal layers Lower cost, thinner, more flexible
• Strips combine to form sheets Extensible
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1x8 Strip Layout
Layer 1 (display side)
Layer 2 (computing side)
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2nd Strip Prototype
computing side display side
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Flat Strip Display
• Top: thin 2-layer boards• Bottom: thick multi-layer boards• Must include processor-to-display cxns• No vias in strip-to-strip power distribution
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Applications
• Application Services
• CA Emulation
• Distributed Graphics
• Interactive I/O
• Tactile Array
• LED Camera
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Application Services
• Provides common application functions
• Functions include:– Initial program loading (IPL)– Display setting and refreshing– Inter-processor communication (IPC)– Message passing– Thread management– Subsequent program loading
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CA Emulation
• Each cell has 8 configuration bits and 1 state bit• A text file format has been defined to specify the
configurations and initial states of an array of cells
• The text file is used to define the program to be loaded into a wallpaper computing display
• A message passing sequence is used to exchange data between the subarrays emulated by individual processors
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Distributed Graphics
• Purpose
– Explore distributed applications capabilities using the 2x2 and 8x8 prototypes
• Objective
– Render a single graphics primitive (a quadrilateral) in a distributed fashion
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Approach
• Load all processors with same program
• Inject a message into the array via one of the peripheral processors; the message describes the primitive to be rendered
• Each processor renders a sub-image and passes a copy of the message to two of its neighbors
• Duplicate messages are discarded
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Algorithm
A (a1, a2)
B (b1, b2)
C (c1, c2)
D (d1, d2)
FAB = (a2-b2)x + (a1-b1)y + (a1*b2-a2*b1) FBC = (b2-c2)x + (b1-c1)y + (b1*c2-b2*c1)FCD = (c2-d2)x + (c1-d1)y + (c1*d2-c2*d1) FDA = (d2-a2)x + (d1-a1)y + (d1*d2-d2*a1)
border border pixelpixel
inside inside pixelpixel
outside outside pixelpixel
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Controller and 8x8 WCD
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Tactile Array
• Purpose– Produce an example of actuation
integrated with a conformal computer
• Objective– Tactile array for sensory substitution
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Tactile Display Prototype
• Testbed for tactile transduction on forehead; uses biofeedback
• Sensor system– Ultrasound range finders in fly’s
eye configuration– Accurate 3.5 meter range
sensing
• Display system– Electromechanical actuators
• Processing– 3 microcontrollers in master-
slave configuration
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Tactile Display Schematic
Master MCU
Slave MCU 1
Slave MCU 2
Ultrasound Range Finder
Ultrasound Range Finder
Ultrasound Range Finder
TactileActuator
TactileActuator
TactileActuator
Ultrasound
Pulses
Ultr
asou
nd
Pul
ses
Ultras
ound
Pul
ses
Tactile
Stim
ulation
Tactile
Stim
ulation
Tactile
Stim
ulation
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• Transduction produced by brush on plastic disk
• Stepper motor driven by– Pulse-width modulation– Short envelope duty cycle
• Performance– No audible noise– Relatively low power
Stepper Motor & Brush
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LED Camera
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Programmable Cellular Arrays
• (Larger Arrays of Microcontrollers)
• Programmable Cellular Array ASIC
• Assembling Large Arrays of ASICs
• (Using the 3rd Dimension)
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CA Processors
• Purpose
– Scale processors down in size (and complexity) and up in number
• Objectives– Design CMOS ASICs with arrays of
simple computational cells
– Consider sync & async approaches
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Single CA Cell
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Assembly Methods
• Via-to-Pad
• Roll-to-place (Part Printer)
• FSA
• R2R Flip-Chip on Flex
• Selective Device Transfer
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Via-to-Pad
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Roll-to-Place
• Parts are “printed” from dispensers
• Dispensers are at fixed locations relative to the roll
• (See MIT-CBA for dispenser mock-up)
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Nanoblocks
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FSA Process
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R2R Flip-Chip on Flex Automated Assembly Corporation
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Selective Device TransferFigure from www.zurich.ibm.com/st/server/selectivetrans.html