Constant Current Bias:In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the value of bdc. To make operating point stable IE current should be constant irrespective value ofbdc.For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is increased to very large value, IE (quiescent operating current) decreases. To maintain same value of IE, the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.

Figure 5.1fig1 shows the dual input balanced output differential amplifier using a constant current bias. The resistance RE is replace by constant current

transistor Q3. The dc collector current in Q3 is established by R1, R2, & RE.Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or the base of Q3.Besides supplying constant emitter current, the constant current bias also provides a very high source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the performance equations obtained for differential amplifier using emitter bias are also valid.As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and current IE also changes. To improve thermal

stability, a diode is placed in series with resistance R1as shown in fig2.

Fig. 2

This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of the added diode D. Without D the current would vary with temperature because VBE3 decreases approximately by 2mV/° C. The diode has same temperature dependence and hence the two variations cancel each other and IE3 does not vary

appreciably with temperature. Since the cut � in voltage VD of diode approximately the same value as the base to emitter voltage VBE3 of a transistor the above condition cannot be satisfied with one diode. Hence two diodes are used in series for VD. In this case the common mode gain reduces to zero.Some times zener diode may be used in place of diodes and resistance as shown in fig3 Zeners are available over a wide range of voltages and can have matching temperature coefficientThe voltage at the base of transistor QB is

Fig. 3

The value of R2 is selected so that I2 » 1.2 IZ(min) where IZ is the minimum current required to cause the zener diode to conduct in the reverse region, that is to block the rated voltage VZ.

Current Mirror:

The circuit in which the output current is forced to equal the input current is said to be a current mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The current mirror circuit is shown in fig4

Fig. 4Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The current mirror is a special case of constant current bias and the current mirror bias requires of constant current bias and therefore can be used to set up currents in differential amplifier stages. The current mirror bias requires fewer components than constant current bias circuits.Since Q3 and Q4 are identical transistors the current and voltage are approximately same

For satisfactory operation two identical transistors are necessary.

Example - 1 

Design a zener constant current bias circuit as shown in fig5 according to the following specifications.    (a). Emitter current -IE = 5 mA    (b). Zener diode with Vz = 4.7 V and Iz = 53 mA.    (c). βac = βdc = 100, VBE = 0.715V    (d). Supply voltage - VEE = - 9 V. 

Solution:

 

Fromfig6using KVL we get

Fig. 5Practically we use RE = 820 kΩ

Practically we use R2 = 68 ΩThe designed component values are:                RE = 860 Ω                R2 = 68 Ω

Fig. 6

Example - 2Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following specifications.

1. supply voltage = ± 12 V.2. Emitter current IE in each

differential amplifier transistor = 1.5 mA.

3. Voltage gain ≤ 60.

Solution:The voltage at the base of transistor Q3 is

Assuming that the transistor Q3 has the same characteristics as diode D1 and D2 that is VD = VBE3, then

Practically we take RE = 240 Ω.

Practically we take R2 = 3.6 kΩ.

To obtain the differential gain of 60, the required value of the collector resistor is

fig7

The following fig7 shows the dual input, balanced output differential amplifier with the designed component values as RC = 1K, RE = 240 Ω, and R2 = 3.6KΩ. 

The operation amplifier:An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential (OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package.The block diagram of OPAMP is shown in fig1

Fig. 1The input stage is a dual input balanced output differential amplifier. This stage provides most of the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The intermediate stage of OPAMP is another differential amplifier which is driven by the output

of the first stage. This is usually dual input unbalanced output.Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above ground potential. Therefore level shifting circuit is used to shift the dc level at the output downward to zero with respect to ground. The output stage is generally a push pull complementary amplifier. The output stage increases the output voltage swing and raises the current supplying capability of the OPAMP. It also provides low output resistance.

    

      

Level Translator:Because of the direct coupling the dc level at the emitter rises from stages to stage. This increase in dc level tends to shift the operating point of the succeeding stages and therefore limits the output voltage swing and may even distort the output signal.To shift the output dc level to zero, level translator circuits are used. An emitter follower with voltage divider is the simplest form of level translator as shown in fig2.Thus a dc voltage at the base of Q produces 0V dc at the output. It is decided by R1 and R2. Instead of voltage divider emitter follower either with diode current bias or current mirror bias as shown in fig3 may be used to get better results.In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V. If this shift is not sufficient, the output may be taken at the junction of two resistors in the emitter leg.

Fig. 2

             

Fig. 3fig4, shows a complete OPAMP circuit having input different amplifiers with balanced output, intermediate stage with unbalanced output, level shifter and an output amplifier. 

Example-1:

For the cascaded differential amplifier shown in fig5, determine:

The collector current and collector to emitter voltage for each transistor.

The overall voltage gain. The input resistance. The output resistance.

Assume that for the transistors used hFE = 100 and VBE = 0.715V

Fig. 5

Solution:

(a). To determine the collector current and collector to emitter voltage of transistors Q1 and Q2, we assume that the inverting and non-inverting inputs are grounded. The collector currents (IC ≈ IE) in Q1 and Q2 are obtained as below:

That is, IC1 = IC2 =0.988 mA.

Now, we can calculate the voltage between collector and emitter for Q1 and Q2 using the collector current as follows:

VC1 = VCC = -RC1 IC1 = 10 � (2.2kΩ) (0.988 mA) = 7.83 V = VC2

Since the voltage at the emitter of Q1 and Q2 is -0.715 V,

VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V

Next, we will determine the collector current in Q3 and Q4 by writing the Kirchhoff's voltage equation for the base emitter loop of the transistor Q3:

VCC � RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0 10 � (2.2kΩ) (0.988mA) - 0.715 - (100) (IE3) � (30kΩ) IE3 + 10=0 10 - 2.17 - 0.715 + 10 - (30.1kΩ) IE3 = 0 

Hence the voltage at the collector of Q3 and Q4 is

VC3 = VC4= VCC � RC3 IC3 = 10 � (1.2kΩ) (0.569 mA)

        = 9.32 V

Therefore,

VCE3 = VVCE4 = VC3 � VE3 = 9.32 � 7.12 = 2.2 V

Thus, for Q1 and Q2:               ICQ = 0.988 mA             VCEQ = 8.545 V and for Q3 and Q4:              ICQ = 0.569 mA           VCEQ = 2.2 V

[Note that the output terminal (VC4) is at 9.32 V and not at zero volts.]

(b). First, we calculate the ac emitter resistance r'e of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where

 Ri2 = input resistance of the second stage 

The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the voltage gain of which is

Hence the overall voltage gain is

Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85

Thus we can obtain a higher voltage gain by cascading differential amplifier stages.

(c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the first stage, that is

Ri = 2βac(re1) = (200) (25.3) = 5.06 kΩ

(d). The output resistance of the cascaded differential amplifier is the same as the output resistance of the last stage. Hence,

RO = RC = 1.2 kΩ

 

Example-2:

For the circuit show in fig6, it is given that β =100, VBE =0715V. Determine

The dc conditions for each state The overall voltage gain The maximum peak to peak output voltage

swing.

Fig. 6

Solution:

(a). The base currents of transistors are neglected and VBE drops of all transistors are assumed same.

From the dc equivalent circuit,

and

b) The overall voltage gain of the amplifier can be obtained as below:

Therefore, voltage gain of second stage

The input impedance of second stage is

The effective load resistance for first stage is

Therefore, the voltage gain of first stage is

The overall voltge gain is AV = AV1 AV2

(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - VE7)                                                 = 2 x (5.52 - 3.325)                                                 = 4.39 V

 

 

 Practical Operational AmplifierThe symbolic diagram of an OPAMP is shown in fig1.

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

Parameters of OPAMP:The various important parameters of OPAMP are follows:1.Input Offset Voltage:

Input offset voltage is defined as the voltage that must be applied between the two input terminals of an OPAMP to null or zero the output fig2, shows that two dc voltages are applied to input terminals to make the output zero.Vio = Vdc1 � Vdc2

Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Viois the difference of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage ± 6 mV is

Fig. 2

required to one of the input to reduce the output offset voltage to zero. The smaller the input offset voltage the better the differential amplifier, because its transistors are more closely matched.

2. Input offset Current:The input offset current Iio is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier.Iio = |   IB1 � IB2 |The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further.For a precision OPAMP 741C, Iio is 6 nA3.Input Bias Current:The input bias current IB is the average of the current entering the input terminals of a balanced amplifier i.e.IB = (IB1 + IB2 ) / 2For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA

4. Differential Input Resistance: (Ri)Ri is the equivalent resistance that can be measured at either the inverting or non-inverting input terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2 MΩ. For some OPAMP it may be up to 1000 G ohm.5. Input Capacitance: (Ci)Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C.6. Offset Voltage Adjustment Range:741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig3.

Fig. 3By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to

zero volts. Thus the offset voltage adjustment range is the range through which the input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is ± 15 mV.

 

Parameters of OPAMP:7. Input Voltage Range :Input voltage range is the range of a common mode input signal for which a differential amplifier remains linear. It is used to determine the degree of matching between the inverting and noninverting input terminals. For the 741C, the range of the input common mode voltage is ± 13V maximum. This means that the common mode voltage applied at both input terminals can be as high as +13V or as low as �13V.8. Common Mode Rejection Ratio  (CMRR).  CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM

CMRR = Ad / ACM.For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two input terminals and the smaller is the output common mode voltage.9. Supply voltage Rejection Ratio: (SVRR)SVRR is the ratio of the change in the input offset voltage to the corresponding change in power

supply voltages. This is expressed in m V / V or in decibels, SVRR can be defined asSVRR = D Vio / D VWhere D V is the change in the input supply voltage and D Vio is the corresponding change in the offset voltage.For the 741C, SVRR = 150 µ V / V.For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3 £ 10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR. 

10. Large Signal Voltage Gain:Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain is commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically.11. Output voltage Swing:The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage can swing positive or negative. This also indicates the values

of positive and negative saturation voltages of the OPAMP. The output voltage never exceeds these limits for a given supply voltages +VCC and �VEE. For a 741C it is ± 13 V.12. Output Resistance: (RO)RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP.Example - 1Determine the output voltage in each of the following cases for the open loop differential amplifier of fig4:

a. vin 1 = 5 m V dc, vin 2 = -7 µVdc

b. vin 1 = 10 mV rms, vin 2= 20 mV rms

Fig. 4Specifications of the OPAMP are given below: A = 200,000, Ri = 2 M Ω , R O = 75Ω, + VCC = + 15 V, - VEE = - 15 V, and output voltage swing = ± 14V.Solution:(a). The output voltage of an OPAMP is given by

Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input signals are zero.(b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP saturates at ± 14 V. Therefore, the actual output waveform will be clipped as shown fig5. This non-sinusoidal waveform is unacceptable in amplifier applications.

Fig. 5

13. Output Short circuit Current :In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output current is limited. The 741C can supply a maximum short circuit output current of only 25mA.14. Supply Current :IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8 m A.15. Power Consumption:Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W. 

Parameters of OPAMP:16. Gain Bandwidth Product:The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in. fig6, It can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is 10Hz.

 

Fig. 617. Slew Rate:Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / m secs.

To understand this, consider a charging current of a capacitor shown in fig7.

Fig. 6If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited.Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input frequency with input amplitude constant. The slew rate changes with change in voltage gain and is normally specified at unity gain.If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is low 0.5 V / m S. which limits its use in higher frequency applications.18. Input Offset Voltage and Current Drift:It is also called average temperature coefficient of input offset voltage or input offset current. The input offset voltage drift is the ratio of the change in input offset voltage to change in temperature and expressed in m V /° C. Input offset voltage drift = ( D Vio / D T).Similarly, input offset current drift is the ratio of the change in input offset current to the change in temperature. Input offset current drift = ( D Iio / D T).For 741C,D Vio / D T = 0.5 m V / C. D Iio/ D T = 12 pA / C.  

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Parameters of an OPAMPExample - 1A 100 PF capacitor has a maximum charging current of 150 µA. What is the slew rate?Solution:C = 100 PF=100 x 10-12 F I = 150 µA = 150 x 10-6 A

Slew rate is 1.5 V / µs.Example - 2An operational amplifier has a slew rate of 2 V / µs. If the peak output is 12 V, what is the power

bandwidth?Solution:The slew rate of an operational amplifier is

As for output free of distribution, the slews determines the maximum frequency of operation fmax for a desired output swing.

so    So bandwidth = 26.5 kHz.Example - 3For the given circuit in fig1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential input voltage?. If A = 105, what does the output offset voltage equal?

Fig. 1Solutin:Iin(off) = 20 nAVin(off) = 0(i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20µ V(ii) If A = 105 then the output offset voltage Vin(off) =

20 µ V x 105 = 2 voltOutput offset voltage = 2 volts.Example - 4R1 = 100Ω, Rf = 8.2 k, RC = 10 k. Assume that the amplifier is nulled at 25°C. If Vin is 20 mV peak sine wave at 100 Hz. Calculate Er, and Vo values at 45°C for the circuit shown in fig2.

Fig. 2Solution:

The change in temperature ΔT = 45 - 25 = 20°C.

Error voltage = 51.44 mV

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV dc level.Example - 5Design an input offset voltage compensating network for the operational amplifier µA 715 for the circuit shown in fig3. Draw the complete circuit diagram.

Fig. 3Solution:From data sheet we get vin = 5 mV for the operational amplifier µA 715.V = | VCC | = | - VEE | = 15 VNow,

If we select RC = 10Ω, the value of Rb should be                   Rb = (3000) RC = 30000Ω = 304Ω

Since R > Rmax, let RS = 10 Rmax where Rmax = Ra / 4. Therefore,

If a 124Ω potentiometer is not available, we may prefer to use to the next lower value avilable, such as 104Ω, so that the value of Ra will be larger than Rb by a factor of 10. If we select a 10 kΩ potentiometer a s the Ra value, Rb is 12 times larger than Ra, ThusRa = 10 kΩ potentiometer  Rb = 30 kΩ Rc = 10Ω.The final circuit, which also includes the pin connections for the µA 715, shown in fig4.

Fig. 4  

The ideal OPAMP :An ideal OPAMP would exhibit the following electrical characteristic.

1. Infinite voltage gain Ad

2. Infinite input resistance Ri, so that almost any signal source can drive it and there is no loading of the input source.

3. Zero output resistance RO, so that output can drive an infinite number of other devices.

4. Zero output voltage when input voltage is zero.

5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified without attenuation.

6. Infinite common mode rejection ratio so that the output common mode noise voltage is zero.

7. Infinite slew rate, so that output voltage changes occur simultaneously with input voltage changes.

There are practical OPAMPs that can be made to approximate some of these characters using a negative feedback arrangement.Equivalent Circuit of an OPAMP:fig5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin voltage source and RO is the Thevenin equivalent impedance looking back into the terminal of an OPAMP.

Fig. 5This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in observing the effects of standard feedback arrangementsvO = Ad (v1 � v2) = Ad vd.This equation indicates that the output voltage vO is directly proportional to the algebraic difference between the two input voltages. In other words the OPAMP amplifies the difference between the two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity of the difference voltage vd.Ideal Voltage Transfer Curve:The graphic representation of the output equation is shown infig6 in which the output voltage vO is plotted against differential input voltage vd, keeping gain Ad constant.

Fig. 6The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages are specified for given values of supply voltages. This means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage remains constant.Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If the curve is drawn to scale, the curve would be almost vertical because of very large values of Ad. 

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