control code device function connector * see … · ltx_port2_2-ltx_port2_c-ltx_port2_3+...

A INITIAL RELEASE E OMORUYIMAR-2015

B CHANGES PER ECR-056824 OCT-2015 E OMORUYI

1 15

<User Define><User Define><User Define>

: Pitch-pitch StyleVendor StylePACKAGE : PinCount-lead 9X9_MM Package-family

: ADV7613Product(s): ADV7613HW TYPE : Customer Evaluation

no_template

BCodeID1:1

02_039678TBD

-

-

-

MVALE

-

E OMORUYI

-

-

-

-

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

CONNECTORFUNCTIONCODE DEVICE

2

2

6JUMPER TABLE

4

7

5

A

3

DATE APPROVED

D

B

DESCRIPTION

34

OFFON

5

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

1

RELAY CONTROL CHART

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.

SHEET OF

REV.

DA A

ENV C

L GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

* SEE ASSEMBLY INSTRUCTIONS

CONTROL

D

HDMI

2 15

14

15

16

17

1819

13

2

8

GND4

GND3

GND1

GND2

12

11

10

9

7

6

5

4

3

1

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0

10029449-001TLF

0000

RCLAMP0524P.TCT

RCLAMP0524P.TCT

0

RCLAMP0524P.TCT

0

0

SMBJ5.0A

TBD040247K

1K

DNI

0.1UF

24LCS22A-I/SNSMBJ5.0A

100K

270

R5

R3

R1

R7

R6

R8

R12

R2

R4

D1

C1

D2

U16

J1

R14R10

D3

Q1

Q3

Q2

LED1

R11

D4

D5

JP2

JP1

R9

RXA_2PRXA_2N_FRXA_1P_FRXA_1N_FRXA_1N

RXA_1P

RXA_2P_F

HDMI_5V

RXA_0P RXA_0P_F

BRD_VCC_3V3RXA_CLKN_FHPA

RXA_CLKPRXA_0N

RXA_CLKPRXA_0NRXA_CLKPRXA_CLKN

RXA_0N_FRXA_CLKP_F

RXA_0N

RXA_CLKN

RXA_0P

RXA_2NRXA_2P

RXA_1PRXA_1N

RX_DDC_SDA

HPACEC

RX_DDC_SCL

RXA_2N

BRD_VCC_3V3

RX_DDC_SCLRXA_2P

RX_DDC_SDA

RX_DDC_SCL

RXA_1PRXA_1N

RXA_2N

HDMI_5VRX_DDC_SDARX_DDC_SCLCECRXA_CLKN

RXA_0P

BRD_VCC_3V3

HDMI_5V

HPA

EDID_POWER

HPA

EDID_POWER

SCL

SDA

RX_DDC_SDA

RX_DDC_SCL

RX_DDC_SDACECHPA

HDMI_5V

7

101112

171615

1918

GND3

74

2 9

1

4 6

8

7

5

2

10

13

23

1

9

10

3

8

9

1

5

GND4

GND2GND1

14

9

65

1

46

8

6

3 8

1

2

4

5

10

7

3

2

3

1

23

1

2

CA

CA

CA

12

65

87

43

1 321 32

3

GND

BCO

MA

BCO

MA

PINSGND

DGND

VCCVCLK

SCLSDAVSS

WP_NNCNC

DGND

DGNDDGND

DGND

DGND

DGND

DGND

GND

GND

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

ALL BYPASS CAPS ARE SIZE 0402

TO BLACKFIN PAGE

ADV7613_DUT

3 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

TBD0402

28.6

3636

MEGH

Z

47PF

TBD0402

TRUE

142-0701-201

DNI

DNI

DNI

TBD0402

DNI

47PF

0.1UF

0.1UF 0.1UF

0.1UF

0.1UF

0.1UF

0.1UF 0.1UF 0.1UF

0.1UF 0.1UF

0.1UF 0.1UF 0.1UF 0.1UF

0.1UF

0.1UF 0.1UF

4.7K

330OHM

330OHM

0

0

0

3333

22UF

ADV7613

1K

330OHM

330OHM

330OHM

22UF

22UF

22UF

22UF

22UF

330OHM

TBD0402

R31

C24

C10

R16

Y2

R19

R15

R20

R40

C7C22

C26

C8C9C11C16

C6C25

C27C20C18

C15

C21

C13

C23C28

C5

J6

E7

E6

E4

E5

E3

E2

R17

C12

C19

C14

C17

C3

C2

TP13

R51

R13

R18

U1

O_P0

L_C

O_P12

O_P13

O_P18

O_P16

O_P15

O_P14

O_P8

O_P7

O_P9

R49

O_P10

O_P11

O_P17

ADV7613_TVDD_3V3_FADV7613_DVDDIO_3V3_F

ADV7613_PVDD_1V8_F

RXA_2P_F

ADV7613_LTX_VDD_1V8_F

BRD_VCC_3V3

ADV7613_CVDD_1V8

ADV7613_LTX_VDD_1V8_F

ADV7613_CVDD_1V8_F

ADV7613_DVDDIO_3V3_F

ADV7613_DVDD_1V8_F

BRD_VCC_3V3

ADV7613_LTX_VDD_1V8

LTX_P2_0-

LTX_P1_3+

LTX_P1_2+

LTX_P1_1+

LTX_P1_0+

XTALN

ADV7613_DVDD_1V8_F

LTX_P1_C+LTX_P1_3-

LTX_P1_2-

LTX_P1_1-

LTX_P1_0-

ADV7613_PVDD_1V8

ADV7613_DVDD_1V8

LTX_P2_3+

CECSDA

HDMI_5V

RX_DDC_SCL

RXA_CLKP_F

I2S4_LRCLK

I2S2

I2S0SPDIF

LTX_P2_3-

XTALP

RXA_0P_F

XTALN

LTX_P2_1-

XTALP

SCLMCU_INT1

RXA_0N_FRXA_1P_FRXA_1N_F

RXA_2N_F

RXA_CLKN_F

ADV7613_RESET

RX_DDC_SDA LTX_P2_0+HPA

LTX_P2_C+

CSB

I2S1

I2S3

MCLKOUTSCLK

LTX_P2_2+LTX_P2_2-

LTX_P2_C-

ADV7613_CVDD_1V8_F

ADV7613_TVDD_3V3_F

LTX_P2_1+

LTX_P1_C-

ADV7613_PVDD_1V8_F

ADV7613_TVDD_3V3

ADV7613_DVDDIO_3V3ADV7613_DUT_INT

H6

J8

J5

5432

1

1

1

1

1

1

A5

B5

G3

F3

B8

D10

A8

C2C1

B1

F2F1

E2E1

D2D1

A7

A6

B4A4

D9H7H3H2

J2K2

H1J1

J3K3

J4K4

K5

J7K7

J6K6

K8

J9K9

H10J10

B7

B2

G7

F7E7E6D6C6

K10K1H5H4G6

G5

G4F6F5E5D5C5A10

A2A3

G2

G1

E3D3C3

B6

F4E4D4C4A1

B3

A9B9

C10E10

H8

1

11

11

C7

11

1

G9 H9G

10F9

C9B10

C8 D7 D8 E8 F8

1

E9 G8

1

F10

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

LTX_PORT1_1+

LTX_PORT1_2+

LTX_PORT1_C+

LTX_PORT1_3+

LTX_PORT2_0+

LTX_PORT2_1+

LTX_PORT2_2+

LTX_PORT2_C+

DGND

LTX_PORT1_0+

LTX_PORT1_1-

LTX_PORT1_2-

LTX_PORT1_C-

LTX_PORT1_3-

LTX_PORT2_0-

LTX_PORT2_1-

LTX_PORT2_2-

LTX_PORT2_C-

LTX_PORT2_3+

LTX_PORT1_0-

O_P

18

L_C

LTX_

VDD4

LTX_

VDD3

DGND

DGND

LTX_

VDD2

LTX_

VDD1

LTX_PORT2_3-

O_P

17O

_P16

O_P

15

DVDD

IO

DGND

DGND

DGND

TVDD

CVDD

CVDD

O_P

14O

_P13

O_P

12

DVDD

IO

DGND

DGND

CGND

TVDD

RXA_2-RXA_2+

AP0

O_P

11O

_P10

DVDD

DVDD

DGND

CGND

CVDD

RXA_1-RXA_1+

SCLKMCLKOUT

O_P

9O

_P8

DVDD

DGND

CGND

CVDD

RXA_0-RXA_0+

AP1AP2

O_P

7O

_P0

DVDD

DGND

CGND

CVDD

RXA_C-RXA_C+

AP3AP4

SDA

INT

CSB

XTALN

PGND

CEC

HPA_ARXA_5V

DGND

AP5

SCL

RESETB

PVDD

XTALP

PGND

DDCA_SCLDDCA_SDA

CGND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

5 GND

ALL DIFFERENTIAL LINES MUST BE THE SAME LENGTH [MATCHING LENGTHS]

********LEGEND**********

SMA_CONNECTORS

2 SPDIF

6 GND

8 MCKLOUT

10 LRCK_AP5

1 I2S3

3 I2S2

7 I2S1

9 I2S0

REMOVE SERIES RESISTORS WHEN USING SMA CONNECTORS

REMOVE SERIES RESISTORS WHEN USING SMA CONNECTORS

4 SCLK

4 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0

0

0

SL 11 SMD 062 10 Z

SL 11 SMD 062 10 Z

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

142-0701-201

GND_6GND_5

GND_3 GND_4

J17

R28

R21

R22

R23

R25

R27

R29

R30

R55

R32

R33

R34

R35

R36

R37

R38

R39

R41

R42

R43

R44

R45

R46

R47

R48

R54

R26

P2

P2

R24

J12

J13

J14

J15

J16

J18

J19

J20

J21

J8

J11

J7

J10

J5

J4

J3

J2

J22

J9

LTX_P1_C+

LTX_P1_3-P1_3-

P1_3+

P1_C-

P1_C+

LTX_P1_1+

LTX_P1_1-

P1_2-

P1_2+

LTX_P2_C-

LTX_P2_0-

FPGA_I2S2_AP3

FPGA_SPDIF_AP0

FPGA_SCLK

FPGA_MCLKOUT

FPGA_LRCLK_AP5

FPGA_I2S3_AP4

FPGA_I2S1_AP2

FPGA_I2S0_AP1

I2S4_LRCLK

MCLKOUT

SPDIF

P2_3+

P2_3-

LTX_P2_2+

P2_0+

LTX_P2_3-

I2S1

P2_2-

SCLK

I2S3

I2S2

I2S0

LTX_P2_1+

P2_0-

LTX_P2_C+

LTX_P1_0-

LTX_P1_0+

LTX_P1_2-

LTX_P1_2+

LTX_P1_3+

LTX_P1_C-

LTX_P2_0+

LTX_P2_1-

P1_0+

P1_1+

P2_1-

P2_1+

P2_2+

P1_0-

P1_1-

P2_C-

P2_C+

LTX_P2_2-

LTX_P2_3+

9

246810

1357

1

2 3 4 5

1

3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5

1

2 3 4 5 1

2 3 4 5

1

2 3 4 5

2

DGNDDGND

DGNDDGND

DGND

DGND

DGND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE


TTL O/P TO ADV7511

FPGA_1

LVDS INPUTS TO FPGA

LVDS OUTPUTS FROM FPGA

5 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF0.1UF0.1UF 0.1UF0.1UF0.1UF 0.1UF 0.1UF0.1UF 0.1UF

0.1UF 0.1UF 0.1UF0.1UF

33

3333

33

10K

33

0

33

4.7K

DTSMW-64N-V

4.7K

S25FL127SABMFI101

680

22UF 22UF

4.7K

4.7K

KP-2012SGC

XC6SLX45-3CSG324I

XC6SLX45-3CSG324I

3333

33

33

33

22UF

XC6SLX45-3CSG324I

10K

DNI

TBD0402

TBD0402

DNI

33

0

3333

3333

33

33

3333

33

33

33

33

33

33

3333

C36 C42C34C32

C37C33 C46C45C44 C48 C50C49C31 C35

C38

C39

C52

C40

C51

C41

U3

RN4

RN4RN4

RN1RN6RN6

U3

R59

C30

C29

R62

R61

R56

R60

C43

U2

S1

R64

R67

DS1

U3

R52

RN3

RN2

RN3

RN3

R58

RN2RN2

RN6

R63

R53

R57

RN1

RN6

R65RN5

RN4

R66R50

RN2

RN1

RN5RN3RN5

RN1RN5

P1_C+

P1_1+

P1_0-P1_0+

L1_3-

L1_3+

TX_HSYNCTX_DE

TX_D15TX_D12

TX_D16

TX_D3

CFG_WP#CFG_CLKCS#

FPGA_3V3 FPGA_3V3

FPGA_3V3

FPGA_3V3

FPGA_3V3

FPGA_3V3

CS#

FPGA_3V3

FPGA_3V3

FPGA_3V3

PROGRAM

CFG_HOLD#

FPGA_DONE

P2_3-P2_3+

P1_3-

P1_C-

P1_3+

P2_0+P2_0-

P2_1+P2_1-P2_2+P2_2-

P1_2+P1_2-

P1_1-

P2_C+P2_C-

TX_D4

TX_D19

TX_D5

TX_D17

TX_D7

TX_D21

TX_D22

TX_D20

TX_D18

TX_LRCLK

TX_CLK

TX_SCLK

MISO2

CFG_SOCFG_SI

L2_0-

CFG_WP#CFG_HOLD#

FPGA_DONE

MISO2

PROGRAM

CFG_CLK

FPGA_3V3

L2_1+

FPGA_3V3

L2_C+

L2_2+L2_2-

CFG_SOCFG_SI

L2_1-

L2_0+

L2_C-

L2_3-L2_3+L1_0-L1_0+

L1_2-

L1_2+

L1_1+L1_1-

L1_C+L1_C-

TX_D14

TX_D13

TX_D11

TX_D2

TX_D1

TX_D8

TX_VSYNCTX_D10

TX_D6

TX_D23

TX_D9

TX_D0

R17

V4T4

V7U8

N7

V8

T6T7R7

M8N8

J16

7 245

H1514

H145

54

K15

J14

C17

1

T18

U18

N14

5

7

H137

C4D4A2B2C6D6A3

B4A5C5A6B6A7C7

D8A8B8

B9

C10F9G9A11

A12B12A13C13A14

A15C15C14D14A16B16

B10

B15

B5 D13

D7 E10

E17

G15

J17

M15

61

4

7

5

8

3

1

2

3

4

CA

B14

A9D9C9

C11D11A10

C8

B3A4 B11

E13F13

P16P15

K16

3

L15

K18

L16H17H18

M13L14

J135G18

8 K14L12L13

U17

6

3

G13

7

6

2

L18

U9U4U14

R6R12

P9

V2

U3V3N5P6

R3

R5T5

P7

V6

U10

V11

N9

P11

U13V13

P12T14

U16V16

T15V17P13

M11

R10

V12

N12

N6T11R11

T12

R15

N10

T13R13V15U15V14

U11

T8V10

M10

2

N11

T10

T3

V5

U7P8

R8V9T9

U5

D18D17

C18F14G14

H12

F18

8

6 3

M16

H16

7 2

K17

4

32

G16

J18

E16

L17

6

1 8

14

8

F16

F17K13

M14

T17N16N15P18P17

E18

6

N17M18

3

N18K12

2

F15

54

13

12

8678

DGND

DGNDN4

N3N1

N2

DGND

DGND

WP_N/IO2HOLD_N/IO3_OR_IO3/RESET_N

SI/IO0CLK

VCC

GND

SO/IO1CS_N

DGND

DGND

DGND

DGND

VCCO

_2VC

CO_2

VCCO

_2VC

CO_2

VCCO

_2VC

CO_2PROGRAM_B_2_N

IO_L65N_CSO_B_2IO_L65P_INIT_B_2

IO_L64N_D9_2IO_L64P_D8_2

IO_L63N_2IO_L63P_2



IO_L48N_RDWR_B_VREF_2IO_L48P_D7_2

IO_L47N_2IO_L47P_2

IO_L46N_2IO_L46P_2

IO_L45N_2IO_L45P_2

IO_L44N_2IO_L44P_2

IO_L43N_2IO_L43P_2

IO_L41N_VREF_2IO_L41P_2

IO_L40N_2IO_L40P_2

IO_L32N_GCLK28_2IO_L32P_GCLK29_2

IO_L31N_GCLK30_D15_2IO_L31P_GCLK31_D14_2

IO_L30N_GCLK0_USERCCLK_2

IO_L30P_GCLK1_D13_2


IO_L23N_2IO_L23P_2

IO_L22N_2IO_L22P_2

IO_L20N_2IO_L20P_2

IO_L19N_2IO_L19P_2


IO_L15N_2IO_L15P_2

IO_L14N_D12_2IO_L14P_D11_2

IO_L13N_D10_2IO_L13P_M1_2

IO_L12N_D2_MISO3_2IO_L12P_D1_MISO2_2

IO_L5N_2IO_L5P_2

IO_L3N_MOSI_CSI_B_MISO0_2IO_L3P_D0_DIN_MISO_MISO1_2

IO_L2N_CMPMOSI_2IO_L2P_CMPCLK_2

IO_L1N_M0_CMPMISO_2IO_L1P_CCLK_2

DONE_2CMPCS_B_2

DGND

DGND

VCCO

_1VC

CO_1

VCCO

_1VC

CO_1

VCCO

_1VC

CO_1

IO_L74N_DOUT_BUSY_1IO_L74P_AWAKE_1

IO_L61N_1IO_L61P_1


IO_L52N_M1DQ15_1IO_L52P_M1DQ14_1IO_L51N_M1DQ13_1IO_L51P_M1DQ12_1

IO_L50N_M1UDQSN_1IO_L50P_M1UDQS_1IO_L49N_M1DQ11_1IO_L49P_M1DQ10_1IO_L48N_M1DQ9_1

IO_L48P_HDC_M1DQ8_1IO_L47N_LDC_M1DQ1_1

IO_L47P_FWE_B_M1DQ0_1IO_L46N_FOE_B_M1DQ3_1IO_L46P_FCS_B_M1DQ2_1

IO_L45N_A0_M1LDQSN_1IO_L45P_A1_M1LDQS_1

IO_L44N_A2_M1DQ7_1IO_L44P_A3_M1DQ6_1

IO_L43N_GCLK4_M1DQ5_1IO_L43P_GCLK5_M1DQ4_1

IO_L42N_GCLK6_TRDY1_M1LDM_1IO_L42P_GCLK7_M1UDM_1

IO_L41N_GCLK8_M1CASN_1IO_L41P_GCLK9_IRDY1_M1RASN_1IO_L40N_GCLK10_M1A6_1IO_L40P_GCLK11_M1A5_1IO_L39N_M1ODT_1IO_L39P_M1A3_1IO_L38N_A4_M1CLKN_1IO_L38P_A5_M1CLK_1IO_L37N_A6_M1A1_1IO_L37P_A7_M1A0_1IO_L36N_A8_M1BA1_1IO_L36P_A9_M1BA0_1IO_L35N_A10_M1A2_1IO_L35P_A11_M1A7_1IO_L34N_A12_M1BA2_1IO_L34P_A13_M1WE_1IO_L33N_A14_M1A4_1IO_L33P_A15_M1A10_1IO_L32N_A16_M1A9_1IO_L32P_A17_M1A8_1IO_L31N_A18_M1A12_1IO_L31P_A19_M1CKE_1IO_L30N_A20_M1A11_1IO_L30P_A21_M1RESET_1IO_L29N_A22_M1A14_1IO_L29P_A23_M1A13_1IO_L1N_A24_VREF_1IO_L1P_A25_1

IO_L1P_HSWAPEN_0

VCCO

_0VC

CO_0

VCCO

_0VC

CO_0

VCCO

_0VC

CO_0

IO_L66N_SCP0_0IO_L66P_SCP1_0





IO_L50N_0IO_L50P_0

IO_L41N_0IO_L41P_0

IO_L39N_0IO_L39P_0




IO_L35N_GCLK16_0

IO_L35P_GCLK17_0


IO_L33N_0IO_L33P_0

IO_L11N_0IO_L11P_0

IO_L8N_VREF_0IO_L8P_0IO_L10N_0IO_L10P_0

IO_L6N_0IO_L6P_0

IO_L5N_0IO_L5P_0

IO_L4N_0IO_L4P_0

IO_L3N_0IO_L3P_0

IO_L2N_0IO_L2P_0

IO_L1N_VREF_0

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

22UF X1, 0.1UF X1222UF X1, 0.1UF X12


FPGA_2

6 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0.1UF

XC6SLX45-3CSG324I

0

0

0

0

0

4.7K

0

0

50MHZ33

XC6SLX45-3CSG324I

22UF

0.1UF22UF 0.1UF0.1UF 0.1UF

0.1UF

0.1UF

0.1UF0.1UF0.1UF0.1UF0.1UF

87832-1420-TB32

4.7K

DTSMW-64N-V

0

1K

22UF

4.7K

R71

R80

R81

R82

R83

R84

R153

R72

R78

C86C85

C66

C78 C84C83C87C82C80C77C63 C68C67C65C62C59C58 C74C72 C76 C81C54

C57 C61 C64 C70 C73

C60

C47

C69 C71

P10

C75C53

R69

S2

R87

R68Y3

R70

C55

U3

U3

FPGA_3V3

SCL

FPGA_RESET_OUT

SDA

TX_SPDIFTX_I2S0

TX_I2S1

FPGA_LRCLK_AP5

TX_MCLK

FPGA_TDO

FPGA_I2S3_AP4

TX_I2S3

FPGA_3V3

FPGA_I2S2_AP3

FPGA_1V2FPGA_3V3

FPGA_BUTTON_RESET

FPGA_TMS

FPGA_TCK

FPGA_TDO

FPGA_SCLK

FPGA_I2S1_AP2

FPGA_I2S0_AP1

FPGA_SPDIF_AP0

XTAL_CLK

FPGA_3V3

FPGA_TDI

FPGA_3V3

FPGA_TCKFPGA_TDIFPGA_TMS

FPGA_3V3

TX_I2S2

FPGA_BUTTON_RESET

FPGA_MCLKOUT

P1N2

F3

G6

E3

E4

H7D1

H6

K6

J7

H4

J6

G1

L7

G3

K4

E6

F1

H9H11

G7

P5P14

P10

M9

K7J12

G10

E9E5E14

B17

B1 M12

J8J10

K11

K9 L10

L8 M7

K5

1413121110987654321

4

3

2

1

4

3

2

1

B18 D16D15A17

R16

E12

F12

C12

D12

E11

F11

F10

G11F8G8F7E8E7V18V1U6U12

T16R9R4R18

R14R1N13

M6

M2

M17L9L11K8K10J9J4J15

J11H8H10

G5

G2

G17

G12E15D5D10C3C16B7B13

A18A1

R2M4

J5J2G4

E2

C2C1

F6F5

D3

D2

F4E1

H5

F2

H3

L5

K3

H2H1

J3J1

L4L3

K2K1

L2L1

M3M1

N1

P2

T2T1

U2U1

L6M5

P4P3

N4N3

SPAREPIN

SPAREPIN

DGND

DGND

DGND

DGND

N4

N3N1

N2DGND

NCNCNCNCNCNCNCNCNCNCNCNCNCNCVC

CINT

VCCI

NTVC

CINT

VCCI

NTVC

CINT

VCCI

NTVC

CINT

VCCI

NTVC

CINT

VCCI

NTVC

CINT

VCCA

UXVC

CAUX

VCCA

UXVC

CAUX

VCCA

UXVC

CAUX

VCCA

UXVC

CAUX

VCCA

UXVC

CAUX

VCCA

UXVC

CAUX

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SUSPEND

TDOTMSTDITCK

DGND

EOHGND

VCC

OUTPUT

DGND

VCCO

_3VC

CO_3

VCCO

_3VC

CO_3

VCCO

_3VC

CO_3


IO_L55N_M3A14_3IO_L55P_M3A13_3IO_L54N_M3A11_3

IO_L54P_M3RESET_3IO_L53N_M3A12_3IO_L53P_M3CKE_3

IO_L52N_M3A9_3IO_L52P_M3A8_3IO_L51N_M3A4_3

IO_L51P_M3A10_3IO_L50N_M3BA2_3IO_L50P_M3WE_3IO_L49N_M3A2_3IO_L49P_M3A7_3

IO_L48N_M3BA1_3IO_L48P_M3BA0_3

IO_L47N_M3A1_3IO_L47P_M3A0_3

IO_L46N_M3CLKN_3IO_L46P_M3CLK_3IO_L45N_M3ODT_3

IO_L45P_M3A3_3IO_L44N_GCLK20_M3A6_3IO_L44P_GCLK21_M3A5_3

IO_L43N_GCLK22_IRDY2_M3CASN_3IO_L43P_GCLK23_M3RASN_3

IO_L42N_GCLK24_M3LDM_3IO_L42P_GCLK25_TRDY2_M3UDM_3IO_L41N_GCLK26_M3DQ5_3IO_L41P_GCLK27_M3DQ4_3IO_L40N_M3DQ7_3IO_L40P_M3DQ6_3IO_L39N_M3LDQSN_3IO_L39P_M3LDQS_3IO_L38N_M3DQ3_3IO_L38P_M3DQ2_3IO_L37N_M3DQ1_3IO_L37P_M3DQ0_3IO_L36N_M3DQ9_3IO_L36P_M3DQ8_3IO_L35N_M3DQ11_3IO_L35P_M3DQ10_3IO_L34N_M3UDQSN_3IO_L34P_M3UDQS_3IO_L33N_M3DQ13_3IO_L33P_M3DQ12_3IO_L32N_M3DQ15_3IO_L32P_M3DQ14_3IO_L31N_VREF_3IO_L31P_3IO_L2N_3IO_L2P_3IO_L1N_VREF_3IO_L1P_3

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

ADV7511

PLACE NEAR U4

CAN BE PLACE ANYWHERE FEASIBLE

7 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

ADV7511WBSWZ

RCLAMP0524P.TCT

2K

0.1UF

TBD0402

DNI

DNITBD0402

DNI

2K

0.1UF

2K887

RCLAMP0524P.TCT

NC7SZ126M5X

KP-2012SGC220

RCLAMP0524P.TCT

22UF

10K

2K

22UF

22UF

22UF

10029449-001TLF

2K2K

22UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

TBD0402

D7

P12

C104

C105

U5C88R89

R90

C103

R85

R86

R88

R92

D6

D8

C89 C92

C97

P1

DS2R99

R95

R98

C91

R97

U4

C90 C101

C98

C93

C95

C188

C94

C99

C102

C96

GND_7 GND_8

GND_9 GND_10

TX_HSYNC

TX_CLK

SCL

TX_DDC_SCLTX_DDC_SDA

TX0+_OUT

HPD

TXC-_OUTTXC+_OUTTX0-_OUT

TX2+_OUT

TX1-_OUTTX1+_OUT

TX2-_OUTTX2+_OUT

TXC+_OUT

BRD_5V

BRD_VCC_3V3

TX_DDC_SCLTX_PD

TX_DE

ADV7511_PVDD_1V8

ADV7511_DVDD_3V3

BRD_5V

TX_DDC_SDA

TX_VSYNCTX_D0

ADV7511_DVDD_1V8TX_I2S3

NCNC

TX_D19

TX_I2S2

TX_SPDIF

TX_I2S0TX_MCLK

TX_LRCLKTX_SCLKTX_D23TX_D22TX_D21TX_D20

TX_D18TX_D17TX_D16TX_D15TX_D14TX_D13TX_D12TX_D11TX_D10TX_D9TX_D8TX_D7TX_D6TX_D5TX_D4TX_D3TX_D2TX_D1

HPD

TX1-_OUTTX1+_OUTTX2-_OUT

TX_DDC_SCL

HPD

TX_DDC_SCL

TX1-_OUT

HPD

SDA

TX0+_OUTTX0-_OUTTXC+_OUTTXC-_OUT

ADV7511_BGVDD_1V8

TX0+_OUT

TX0-_OUT

TX2+_OUT

ADV7511_AVDD_1V8

TX_I2S1

TX1+_OUT

ADV7511_PVDD_1V8 ADV7511_DVDD_3V3

TXC+_OUT

TXC-_OUT

TX2-_OUT

TX_DDC_SDA

ADV7511_DVDD_1V8

ADV7511_BGVDD_1V8ADV7511_AVDD_1V8

TX_DDC_SDA

TXC-_OUT

TX2+_OUTTX1-_OUTTX1+_OUTTX0-_OUTTX0+_OUT

TX2-_OUT

1

16

64

62

21

30

15 19 25 13

32

53

6160595857565554525049484746454443424140393837

33

34

63

1 11 31 51 29

5678

28

104

PAD

22

12

14

35

9

36

3

20

2423

2726

1817

2

3 8

1

2

4

5

10

9

7

6

3 8

1

2

4

5

10

9

7

3 8

1

2

4

5

10

9

7

6

123456789101112

141516171819

GND1GND2GND3GND4

2

3

1

4CA

13

6

5

DGND

DGND

DGNDDGND

DGNDDGND

DGND

DGND

PINSPARESPARE

PIN

DGND

DGND

YA

OEVCC

GND

DGND

PINSGND

DGND DGND

DGND

DGND

DGND

DGND

DGND

GND

GND

GND

DGND

DGND

DGND

PAD

HYSNCDE

D0D1D2D3D4D5D6D7D8

CLK

D9

DVDD

D10D11D12D13D14D15D16D17D18D19D20D21D22D23

SDA

SCL

DDCSDA

DDCSCL

CEC_CLK DVDD

CEC

DVDD

_3V

INT

TX2+TX2-

AVDD

TX1+TX1-

PD

TX0+TX0-

AVDD

TXC+TXC-

HPD

AVDD

R_EXT

BGVD

D

PVDD

DVDD

LRCLKSCLK

I2S3I2S2I2S1I2S0MCLK

SPDIF

VSYNC

DVDD

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

NX5032GA-24MHZ

USB

BF_1

......LEGEND.......1 3V33 SDA5 SCL7 RESET_GLOBAL

NOTE: REMOVE PIN 3 OF P9 FOR KEYING

8 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

8.2PF

24MEGHZ

10UF

3333

33330

3333

33

3333333333

33

33

3333

3333

33

3333

3333

3333

33

4.7K

TSM-105-01-T-SV

33

10K

SL 11 SMD 062 14 Z

SL 11 SMD 062 14 Z

10K

33

33

10K

0

10K

ADSP-BF527KBCZ-6A

ADSP-BF527KBCZ-6A

10K

2K

10K

DTSMW-64N-V

10K10K

33

33

33

33

0

33

33

330

8.2PF

33

3333

10K10K

0.50A

10K

1MEG

0

PGB1010603

47K

0.1UF

0.1UF

33

33

ADM6384YKS29D1Z

33

0

2K

33

PGB1010603

600OHMADSP-BF527KBCZ-6A

5.5V

PGB101060356579-0519

33

33

ADSP-BF527KBCZ-6A

33

33

33

33

DNI

DNI DNI

DNI

DNI

TBD0402

TBD0402 TBD0402

TBD0402

0.1UF

TBD0402

DNI

TBD0402

C109

Y1

RN11

R127

RN11

RN14

RN11

RN14

RN11RN12

RN12RN12

RN12

RN7RN7

RN9RN9RN9

RN8

RN9

RN10RN10RN10RN10

RN8RN8

U6

U6

U6

R102

R103

R94

R101R105

R106

R96

JP3

JP4

R108 R109

R112

R113R114R115

R116

R117

R118

R129

R130R131R132R133R134R135

R126

R111

C111

R104 R123

R91 R93

P3F1

C108

R120R122

C107

R110

CR1

CR2

U6

A2R100 R107

C124

S3

TP28

P9

P9

R196

P8

RN7

R136

CR3V1 E1

C110

RN8

RN7

RN14

RN13RN13RN13

RN14

RN13

R119

R128

R121 R124

R125

C106

A19A18

ABE1#ABE0#

A1A2A3A4A5

A9A10

A13A12

D7D8

D3

D11D10

D13

D15D14

D12

D9

JTAG_TDOJTAG_TDIJTAG_TRSTJTAG_TCKJTAG_TMS

RESET_GLOBALSCLSDA

BRD_VCC_3V3

JTAG_TRST

MCU_RST_DUT

BRD_VCC_3V3

BF_SPI_CS1_SSMCU_SPI_S_SCK

BMODE3

BRD_VCC_3V3

BMODE2

MCU_SPI_S_SDI

JTAG_TMS

USB_XTALINUSB_ID

JTAG_TDIJTAG_TCK

JTAG_TDO

BF_UART0_TX

BF_RESET

MCU_INT1

SRAS#

SMS#

SCAS#

SCKE

SWE#

BMODE0BMODE1BMODE2BMODE3

SA10

USB_XTALIN

CLKOUT

D0

D2

RESET#

SDASCL

BMODE0 BMODE1

MCU_RST_GLOBAL

RESET#

JTAG_EMU

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BF_BOOT_CS

BRD_VCC_3V3

MCU_SPI_S_SDO

BF_UART0_RX

JTAG_EMU

D1

USB_ID

D6D5D4

A8A7A6

F19

1

1 8

N19

N20L20

V19V20

72

6

M19K19

63

3

5

W5

4 Y6 65

65

4 5817

34

W20

2 7

Y4

4 53 6

5

W4

6

Y3W3Y2

W8

72

Y14

W62

85

W2

17

6

8

W1

Y7

3

W18

4

14

T2V2R1

T1

U2U1

F20E20

C20D20

E19H19

A19 A18

F1E1E2D1D2C1C2B1B2A2B3A3B5A5B6A6

R2P1P2N1N2M1M2L1L2K1K2J1J2H1H2G1

A7B7A8B8A9B9

B10B11

A12B12A13B13B14B15B16B17

G2F2A4B4

Y19

W11

J19

M20

Y10W10

Y9W9

C19A11K20J20

B19

B18

A14A15U19U20P20R19T19

G19

T20

H20

A10

1 2

1 2

12

5

SH2

1 2

1

2

2

1

2

1

2

A1A17A20B20H9

H10H11H12H13

J9 J10

J11

J12

J13 K9 K10

K11

K12

K13L9L10L11L12L13M9M10M11

M12

M13

N9N10

N11

N12

N13

Y1Y20

1324

1

2

3

4

1

2468101214

135791113

12345

Y8

12

63

1

43

SH12

V1

P19

87

Y5

3

Y18W781

Y11

W12Y12

12

4 5

Y15

Y13W13

2

W15

W147

43

8

1W17

W19

Y17

Y16W16

8

2

7

DGND

DGND

DGND

DGND

DGND

PINSSHLD

DGNDDGND

DGNDDGND

DGND

DGND

DGND

VROUT_EXT_WAKE1

XTALSWE_N

SRAS_NSMS_N

SCKESCAS_N

SA10RTXO

EXT_WAKE1CLKOUTCLKBUFAWE_NARE_NAOE_N

AMS3_NAMS2_NAMS1_NAMS0_N

ABE1_N_SDQM1ABE0_N_SDQM0

ADDR19ADDR18ADDR17ADDR16ADDR15ADDR14ADDR13ADDR12ADDR11ADDR10

ADDR9ADDR8ADDR7ADDR6ADDR5ADDR4ADDR3ADDR2ADDR1

VRSEL_VDDEXT

SS_PG_N

RTXI

RESET_N

NMI_N

CLKIN

BMODE3BMODE2BMODE1BMODE0

ARDY

DATA15DATA14DATA13DATA12DATA11DATA10DATA9DATA8DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0

PH15PH14PH13PH12PH11PH10

PH9PH8

PH7PH6PH5PH4PH3PH2PH1PH0

PG15PG14PG13PG12PG11PG10

PG9PG8PG7PG6PG5PG4PG3PG2PG1PG0

SDASCLPPI_FS1_TMR0PPI_CLK_TMRCLK

PF15PF14PF13PF12PF11PF10PF9PF8PF7PF6PF5PF4PF3PF2PF1PF0

DGND

DGND

DGND

DGNDN4

N3N1

N2

DGND

RESET* MR*VCCGND

DGND

GND

GND

GND

GND

DGND

DGND

DGND

TRST

USB_VBUSUSB_DPUSB_DMUSB_XO

EMUTDO

USB_VREFUSB_RSETUSB_IDUSB_XI

TMSTDITCK

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

UART

BF_2

9 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0.1UF

191-009-213L571

0.1UF

TBD0402

DNI

0.1UF

0.1UF

0.1UF0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF 0.1UF

0.1UF

0.1UF0.1UF

0

24LC64-I/SN

22UF

100K

4.7K

22UF22UF

MT48LC16M16A2P-6A

22UF

47

10KADM3202ARNZ

10K

M25P32-VMW6G

0

22UF 22UF

ADSP-BF527KBCZ-6A

0

10K

10K

10K

C122

P4

R138

C136

C152

C112

C146

C185

C135

C118 C157

C147

C126

C184 C164C162C155C153

C138C140C154C143C144

C169 C168C167C166C165C117 C116C115C114C113 C142 C141C139C137C134C132 C130C129C128C127

C150C149C148

C161C159C158

C121

R168R169

R140

JP5

R141

R139

R137

R171

C131

R170

R166

R143

R142

C123

C125C119

C120 A1

C151

U9

U8

U7

C145C160

C133

C163C156

U6

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

MCU_SPI_S_SDO

BF_VDDMEM

+2.5VVDDINT

BF_VDDEXT

BF_VDDMEM

BRD_VCC_3V3

BF_VDDEXT

SCLSDA

D1D2D3

D6D7

D11D12D13D14D15

D10D9D8

A3A2

SA10

A19

A12

A13A18

A8

A10A9

A5A6A7

A4

D0

ABE0#ABE1#

D4D5

BF_UART0_RX

BF_UART0_TX

VDDINT

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3 BRD_VCC_3V3

MCU_SPI_S_SDIMCU_SPI_S_SCKBF_SPI_CS1_SS

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

BF_VDDMEM

SCKECLKOUTSMS#SWE#SCAS#SRAS#

A1

+2.5V

BF_VDDMEM

5

123

6789

4

J7

A16

D19

G20

G10

21

16

6

2

7101411

9 812 13

15

5431

16

5246126544128

49439327141

18

40

1539

535150484745444213111087542

193837

17

2120

36352234333231302926252423

3

4

8

1

7

256

7

4

8

56321

L19

R20

P11

P10P9P8P7N8N7M8

M7L8

P14

P13

P12

N14

M14

L14

K14

J14

H14

G14

G13

G12

L7K8K7J8H8H7G11G9

G8

G7

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

V-

C1-

GND

T2OUT

R2OUTR1OUTT2INT1INC2-C2+

C1+

T1OUT

R1INR2IN

V+VCC

DGND

DGND

DQ15DQ14DQ13DQ12DQ11

VSSQ

DQ10DQ9

VDDQ

DQ8

VSSNC

DQMH

CLKCKE

A12A11

A9A8A7A6A5A4A3A2A1A0

A10

BA1BA0

CS_N

RAS_NCAS_NWE_N

DQML

VDD

DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

DQ0

W_N

DQ1VCC

HOLD_N

C

VSS

S_N

VSS

VCC

WP

A2A1A0

SCLSDA

DGND

DGND

DGND

DGNDDGND

VDDU

SB2

VDDU

SB1

VDDR

TC

VDDO

TP

VPPO

TP

VDDMEM

VDDINT1

VDDEXT

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

NI

NI

N1

POWER SECTION

NI

NI

CURRENT LIMITING RESISTORDS3 HAS INTEGRAL

O/P CURRENT SET TO 1.5A

10 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

3.3UH

SI2304DDS-T1-GE310UF

75K

15K

0.1UF

0.1UF1

1UF

1UF

1UF

1UF

10K

680PF

150UF

220PF 27PF

19.6K

60.4K

SI2304DDS-T1-GE3

3.6K

11.1K

2K

2K

15K 15K

22UF

4.3K

39PF560PF

1.5UH

10K

ADP2323ACPZ

9K

PJ-018H

39.2K

820PF

DNI

TBD0402

DNI

TBD0402

DNI

TBD0402

DNI

TBD0402

TBD0402

DNI

L1

Q4

R163

R161

DS3

R150

C179C178

C174

C172

U10

Q5

C4

R144

C170

R154

R148 R151

R149

R152

C171

C173

C175 C180C176

C182

C181

R155

R159

R160

L2

R187

R181

R188

P5

C183

R146

C177

R157

R158

R147

R145

R156

SW1

+2.2V

FB1

+12V

INT_5VEN1EN2

SW1

SW2

COMP1

INT_5V

INT_5V INT_5V

COMP2

SS1

PGOOD2PGOOD1

SW2

MODE FB2

MODE

COMP2DL1

COMP1

DL2

FB2

EN1 EN2

+12V

DL1DL2

SCFG

+12V

SS1SS2

FB1

SS2

+3.7V

INT_5V

SCFG

INT_5V

2

AC

2318

3110

19

2813

PAD

329

4

57

21

18

262714156

23011

24251617

3

2912

20

3

1

2

3

1

2

1

1

2

13

2

22

DGNDDGND

DGND

PGOOD2PGOOD1

EP

FB1

COMP1

SS1

TRK1

EN1

PVIN1

SW1

BST1 DL1

PGND

VDRV

DL2BST2

SW2

PVIN2

EN2

TRK2

SS2

COMP2

FB2MODE

RT

INTVCC

GND

SYNC

SCFG

DGND

DGND

DGND

DGND

DGNDDGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

BRD_3V3_TP

FPGA_3V3_TP

7511_DVDD_3V3_TP

1500MA CURRENT MAX

5V AND 3V3 PAGE

NC

MAX O/P CURRENT = 300MA

NC

3.3V TESTPOINT

DUT_DVDDIO_3V3_TP

300 OHMS @100MHZ 2 AMP FERRITE BEADS

11 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

ADP3339AKCZ-3.3-RL

10UF

0

10UF

ADP3339AKCZ-3.3-RL

ADP3367ARZ

10UF

10UF

10UF

0

0

1UF

1UF

10K

1UF

10UF

39

1UF

10UF

GND_2GND_1

TP5

P16

C192

R164

JP6

R189

R190

R191

C195

TP4

TP3

TP6

R165

U11JP7

P15C196

C189

A4

C190

C187

C194

A3

C186

TP2

C197

C193

TP1

C191

ADV7613_DVDDIO_3V3

+12V

ADV7613_TVDD_3V3

+3.7V

+3.7V

FPGA_3V3

BRD_VCC_3V3

ADV7511_DVDD_3V3

BRD_5V

1

2

1

1

1

5

6

2

73

8

4

1

21

21

1

21

4

23

1

4

23

1

1

1

DGNDDGND

DGND

DGND

GNDOUTINOUT

DGNDDGND

DGND

GNDOUTINOUT

DGND

DGND

DGNDDGND

DGND

DGND

SETLBOLBI

SHDN

GND

INDD

OUT

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

DUT_1V8_TP

ADV613_1V8 PAGE

12 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0.5

4.7UF

ADP1708ACPZ

10UF

10UF

10UF

10UF

4.7UF4.7UF

12K

24K

10K

10000PF

4.7UF

ADP1740ACPZ-1.8-R7

R197

U12

C198C199

C200

C201

TP8

C202

TP9

C204

TP11

C203

TP10

TP7

P20

P19

P18

JP11P17

JP9

JP10

R198

R199

JP8

R167

U21

C229

C228

BRD_VCC_3V3

ADV7613_CVDD_1V8

ADV7613_LTX_VDD_1V8

ADV7613_DVDD_1V8

ADV7613_PVDD_1V8

ADV7613_1.8V

+2.2V

FPGA_1V2

8

4

68 PAD

5

97

123

1516

11

1314

1

1

1

1

1

12

12

12

1 2

12

1 2

1 2

1 2

1

2

34

56

PAD

7

10

12

DGND

PADADJ

IN

GND1

SENSEOUT

EN

IN2 OUT2

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

NC

VOUT

SENSESS

GND

PG

EN

VIN

PAD

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

VDDINT = 1.2V

ADV7511 1V8 & BF SUPPLIES PAGE

SET BY R177 & R178

BRD_1V8_TP

13 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

ADP1706ARDZ-2.5-R7

10000PF

47UF

47UF

47UF47UF

4.7UF

12K

24K

0

4.7UF

0

0

10K

0

4.7UF

0

0

0

0

4.7UF

4.7UF10UF

10UF

10UF

10UF

ADP1708ACPZ

ADP1740ACPZ-1.8-R7

0.01UF4.7UF

20-313137

47UF

R176

C219R177

C216

C230

U17

C205C212

C206

R175

C217

C218

C210

C211

R172

R173

U18

C214

U19

R178

C215

R193

R192

R194

C220

C208

C207

R174

TP12

R195

C209

C213

MH01 MH03 MH04 MH05 MH06 MH07MH02

BRD_VCC_3V3

BRD_VCC_3V3

+2.5V

BF_VDDMEM

+2.2V

ADV7511_DVDD_1V8

ADV7511_AVDD_1V8

VDDINT

BRD_1V8

ADV7511_PVDD_1V8

BF_VDDEXT

ADV7511_BGVDD_1V8

4

68 PAD

5

97

123

1516

1011121314

1

2

34

56

PAD

7

8

8

1

2

34

56

PAD

7

1

1 1 1 1 1 11

DGND

DGND

DGND

PADADJ

IN

GND1

SENSEOUT

EN

IN2 OUT2

DGND

DGND

PADSS

IN

GND

SENSEOUT

EN

IN OUT

DGNDDGND

DGNDDGND

DGND

DGND

DGND

DGNDNC

VOUT

SENSESS

GND

PG

EN

VIN

PAD

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

GLOBAL_RESET_SW

TO TFM-110-02-S-D-WT

RESET PAGE, LVDS TX

MAKE THIS LINE FPGA RESET???

LVDS CONNECTORS TO BE SAME USED ON OLD EVAL BOARDS

NEED TO CHANGE LVDS CONN

ADV7613_RESET_SW

14 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

0.1UF

NC7SZ125M5X

NC7SZ11P6X

10000PF

4.7K

0.1UF

0.1UF

DTSMW-64N-V

NC7SZ11P6X

TFM-110-02-S-D-WT

DTSMW-64N-V

0

4.7K

4.7UF

0.1UF

4.7K

0

0

4.7UF

4.7K

PCA9539D,118

TFM-110-02-S-D-WT

R185

U15

R184

R179

R183 R186

C224

U14

R182

C226

C225

P6 P7

C227

S4

S5

C223

C221

C222

R180U20

U13

BRD_VCC_3V3

BRD_VCC_3V3

BRD_VCC_3V3

RESET_GLOBAL

BRD_VCC_3V3BRD_VCC_3V3

BF_RESET

BRD_VCC_3V3

MCU_RST_GLOBAL

FPGA_RESET_OUT

BRD_VCC_3V3

L1_1+L1_1-

L1_0-

L2_3+L2_3-

L2_0-

L2_2-

ADV7613_RESET

L2_2+

L2_C+L2_C-

L2_1+L2_1-

L2_0+

L1_3+L1_3-

L1_C+L1_C-

L1_2+L1_2-

BRD_VCC_3V3

MCU_RST_DUTRESET_GLOBAL

BRD_VCC_3V3

RESET_GLOBAL

SDASCL

L1_0+

54

4

13

3

2

1

4

9

201918171615141312111098765

321

2019181716151413121110

87654321

12

24

2322

3

20191817161514

1110987654

1

221

43

21

43

21

4

5

2

631

5

2

631

DGND

DGND

SPAREPIN

SPAREPIN

DGNDDGND

DGND

DGND

DGND

VDD

SDASCL

A0

IO1_7IO1_6IO1_5IO1_4IO1_3IO1_2IO1_1IO1_0

VSS

IO0_7IO0_6IO0_5IO0_4IO0_3IO0_2IO0_1IO0_0

RESET_N

AI

INT_N

N4N3N1

N2

N4N3N1

N2

DGND

DGND

C

VCC

YBA

GND

Y

OE_N

A

VCC

GND

DGND

DGND

DGND

DGND

C

VCC

YBA

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

15 15

<DESIGN_VIEW>


1:1

B02_039678

E OMORUYI

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

control code device function connector * see … · ltx_port2_2-ltx_port2_c-ltx_port2_3+...

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