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Control Design

Chapter 5. JPH.

Processor with DP and CU

Register FileRF

CONTROLUNIT

F1 F2

Multiplexers MUX2

Multiplexers MUX1

DatapathUnit

ControlSignals Instructions

Data

A := A + B

CU

F1 F2

DatapathUnit

ControlSignals Instructions

p q r s MUX1

A

B

t

A+B

RF

u v MUX2

w x y z

A B

A+B

Select p-t

Write ARead ARead B

Select u-w

Select v-x

AddOverflow

Finite State Machine

Wikipedia

GCD Procedure

GCD Procedure

Conditions Actions

XR > 0:

XR := 20; YR := 12;

XR > 0:

XR > 0:

XR > 0:

XR ≤ 0:

XR > YR:

XR ≤ YR:

XR ≤ YR:

XR ≤ YR:

XR := XR – YR = 8;

YR := 8; XR := 12;

YR := 4; XR := 8;

YR := 4; XR := 4;

Z := 4;

XR := XR – YR = 4;

XR := XR – YR = 4;

XR := XR – YR = 0;

20 12

8 12

12 8

4 8

8 4

4 4

0 4

GCD Hardware

Subtractor Comparators

Multiplexers MUX

Datapath Unit

Reset

Register XR Register YR

Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

Select XY

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

Select XY

Load XR

Load YR

GCD Control Unit

State

S0 (Begin)

Subtract Swap Select XY

0 0 1

Load XR

1

Load YR

1

InputsOutputs

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

Next States?

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

CU Inputs

XR > 0

XR >= YR

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

CU Inputs

XR > 0

XR >= YR

CU New State

Subtract

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

CU Inputs

XR > 0

XR >= YR

CU New State

Swap

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Begin

CU Inputs

XR > 0

XR >= YR

CU New State

Exit

GCD Control Unit

State

S0 (Begin)

0-

S3

10

S1

11

S2


0 0 1

Load XR

1

Load YR

1

Inputs

(XR > 0) (XR >= YR)Outputs

S1

S2

Swap

Subtract

S0

S1

S2

10

11

0XS3

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Swap

CU Outputs

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Swap

Swap

Load XR

Load YR

CU Outputs

GCD Control Unit

State

S0 (Begin)

0-

S3

10

S1

11

S2


0 0 1

Load XR

1

Load YR

1

Inputs


S1

S2

Swap

Subtract

S0

S1

S2

10

11

S1 (Swap) 0 1 0 1 1

S3

0X

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Swap

Subtract

CU Next States

Subtract

CU Inputs

XR > 0

XR >= YR

CU Inputs

XR > 0

XR >= YR

GCD Control Unit

State

S0 (Begin)

S1 (Swap)

0-

S3

S2

10

S1

S2

11

S2

S2


0

0

0

1

1

0

Load XR

1

1

Load YR

1

1

Inputs


S0

S1

S2

10

11S3

0X

XX

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Subtract

CU Outputs

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Subtract

CU Outputs

Subtract

Load XR

GCD Control Unit

State

S0 (Begin)

S1 (Swap)

0-

S3

S2

10

S1

S2

11

S2

S2


0

0

0

1

1

0

Load XR

1

1

Load YR

1

1

Inputs


S0

S1

S2

10

11S3

0X

XX

S2 (Subtract) 1 0 0 1 0

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Subtract

CU Next State?

Swap

Subtract

CU Inputs

XR > 0

XR >= YR

CU Inputs

XR > 0

XR >= YR

GCD Hardware


Multiplexers MUX

Datapath Unit

Reset


Z X Y

Subtract

Swap

Select XY

Load XR

Load YR

(XR ≥ YR)

(XR > 0)

ControlUnit

Subtract

CU Next State?

Swap

Exit

CU Inputs

XR > 0

XR >= YR

CU Inputs

XR > 0

XR >= YR

GCD Control Unit

State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

0-

S3

S2

S3

10

S1

S2

S1

11

S2

S2

S2


0

0

1

0

1

0

1

0

0

Load XR

1

1

1

Load YR

1

1

0

Inputs


S0

S1

S2

10

11S3

0X

XX

0X

10

Exit State?

GCD Control Unit – Truth Table

State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

S3 (End)

0-

S3

S2

S3

S3

10

S1

S2

S1

S3

11

S2

S2

S2

S3


0

0

1

0

0

1

0

0

1

0

0

0

Load XR

1

1

1

0

Load YR

1

1

0

0

Inputs


S0

S1

S2

10

11S3

0X

XX

0X

10

FSM

Control Unit Design● Hardwired Control

– Specific to the function of the processor (eg. GCD)

– CU design starts from the FSM

– Fast

– Classical Method

– One hot method

● Microprogrammed Control– Uses control memory – can be reprogrammed to suit

the function

– Software controlled

Hardwired Control Design

SequentialLogicCircuit

InstructionRegister

StatusSignals

ControlSignals

GCD Control Unit – Truth Table

State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

S3 (End)

0-

S3

S2

S3

S3

10

S1

S2

S1

S3

11

S2

S2

S2

S3


0

0

1

0

0

1

0

0

1

0

0

0

Load XR

1

1

1

0

Load YR

1

1

0

0

Inputs


S0

S1

S2

10

11S3

0X

XX

0X

10

FSM

GCD – Excitation TableXR > 0 Subtract Swap Select XY Load XR Load YRXR ≥ YR

0

0

0

0

1

1

1

1

1

1

1

1

d

d

d

d

0

0

0

0

1

1

1

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

1

0

1

1

1

0

1

1

1

0

1

1

0

0

1

1

0

0

1

1

0

0

S3

S0

S1

S2

S3

S0

S1

S2

S3

S0

S1

S2

S3

S3

S3

S2

S1

S2

S1

S3

S2

S2

S2

S3

Old State New State

CU Design – Classical Method

S0 = 0 0

S1 = 0 1

S2 = 1 0

S3 = 1 1

Assign a number for each State

● How many Flip flops are needed to realize an n state FSM?

● D0 and D1 are FF present state outputs.

● D0+ and D1

+ are FF next state outputs.

D0D1

GCD – Excitation TableXR > 0 Subtract Swap Select XY Load XR Load YRXR ≥ YR

0

0

0

0

1

1

1

1

1

1

1

1

d

d

d

d

0

0

0

0

1

1

1

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

1

0

1

1

1

0

1

1

1

0

1

1

0

0

1

1

0

0

1

1

0

0

S3

S3

S3

S2

S1

S2

S1

S3

S2

S2

S2

S3

New StateD1 D0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

GCD – Excitation TableXR > 0 D1 D0 D1 Subtract Swap Select XY

+Load XR Load YRXR ≥ YR

0

0

0

0

1

1

1

1

1

1

1

1

d

d

d

d

0

0

0

0

1

1

1

1

D0+

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

0

1

0

1

1

1

1

1

1

0

1

1

1

0

1

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

1

0

1

1

1

0

1

1

1

0

1

1

0

0

1

1

0

0

1

1

0

0

GCD – Classical Method

Subtract=D1⋅D̄ 0

Swap= D̄1⋅D 0

Select XY=D̄1⋅D̄ 0

Load XR=D̄0+ D̄1

Load YR=D̄ 1

What are the equations for each of the outputs in the excitation table?What are the equations for each of the outputs in the excitation table?

Subtract=D1⋅D̄ 0

Swap= D̄1⋅D 0

Select XY= D̄1⋅D̄ 0

Load XR=D0⋅D1

Subtract=D1⋅D̄0

Swap= D̄1⋅D 0

GCD – All NAND Classical Design

Select XY= D̄1⋅D̄ 0Load XR=D0⋅D1 Load YR=D̄ 1

CU Design – One Hot Method

S0 = 0 0 0 1

S1 = 0 0 1 0

S2 = 0 1 0 0

S3 = 1 0 0 0

Assign a one hot combinationfor each State

● n Flip flops are needed to realize an n state FSM

D0D1D2D3


State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

S3 (End)

0-

S3

S2

S3

S3

10

S1

S2

S1

S3

11

S2

S2

S2

S3


0

0

1

0

0

1

0

0

1

0

0

0

Load XR

1

1

1

0

Load YR

1

1

0

0

Inputs


D1+

D0+

D2+

D3+


State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

S3 (End)

0-

S3

S2

S3

S3

10

S1

S2

S1

S3

11

S2

S2

S2

S3


0

0

1

0

0

1

0

0

1

0

0

0

Load XR

1

1

1

0

Load YR

1

1

0

0

Inputs



State

S0 (Begin)

S1 (Swap)

S2 (Subtract)

S3 (End)

0-

S3

S2

S3

S3

10

S1

S2

S1

S3

11

S2

S2

S2

S3


0

0

1

0

0

1

0

0

1

0

0

0

Load XR

1

1

1

0

Load YR

1

1

0

0

Inputs


Subtract=D2

Swap=D1

Select XY=D 0

Load XR=D0+D1+D 2

Load YR=D 0+D1

All NAND One-Hot Design

Two's Complement Multiplier

Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS

InternalControlSignals

ExternalControlSignals

Comparator

7

COUNT7 ControlUnit

Multiplier FlowchartBegin

A := 0COUNT := 0

F := 0M := INBUS

Q := INBUS

Q(0) = 0?

A := A + MF := M(7) and Q(0) or F

A(7) := FA(6:0).Q := A.Q(7:1)

COUNT := COUNT + 1

COUNT7 = 1?

Q(0) = 0?

A := A – MQ(0) := 0

OUTBUS := Q

OUTBUS := A

End

S0

S1

S2

S3

S4

S5

S6

S7

S0

Yes

Yes

No

Yes

No

No

Cycle 0 Cycle 1 to 7 Cycle 8 Cycle 9

Multiplier Control Points

Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

S1

A := 0COUNT := 0

F := 0M := INBUS


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S2

Q := INBUS


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S3

A := A + MF := M(7) and Q(0) or F

c3 c4c2


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S4

c3 c4c2

A(7) := FA(6:0).Q := A.Q(7:1)

COUNT := COUNT + 1c0

c1

c11


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

c3 c4c2

c0

c1

c11

S5

A := A – MQ(0) := 0


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S5

c3 c4c2

c0

c1

c11

A := A – MQ(0) := 0

c5

c5


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S6

c3 c4c2

c0

c1

c11

c5

c5

OUTBUS := Q

c7


Count

BEGIN

END

CLOCK

...c0

c1

c10

A Q M

Parallel Adder

SignLogic

Q[0]M[7]

cin

F

OUTBUS

INBUS


c9

c10

c10


Comparator

c10

7

COUNT7 ControlUnit

c8

S7

c3 c4c2

c0

c1

c11

c5

c5

c7

OUTBUS := A

c6

Multiplier Control Signalsc0

c1

c2

c3

c4

c5

c6

c7

c8

c9

c10

c11

END

Set sign bit of A to F

Right-shift register-pair A.Q

Transfer adder output to A

Transfer A to left input of adder

Transfer M to right input of adder

Perform subtraction. Clear Q[0].

Transfer A to output bus.

Transfer Q to output bus.

Transfer word on input bus to Q

Transfer word on input bus to M

Clear A, COUNT, and F registers

Increment COUNT

Completion signal (CU idle)

Multiplier FlowchartBegin

A := 0COUNT := 0

F := 0M := INBUS

Q := INBUS

Q(0) = 0?

A := A + MF := M(7) and Q(0) or F

A(7) := FA(6:0).Q := A.Q(7:1)

COUNT := COUNT + 1

COUNT7 = 1?

Q(0) = 0?

A := A – MQ(0) := 0

OUTBUS := Q

OUTBUS := A

End

S0

S1

S2

S3

S4

S5

S6

S7

S0

Yes

Yes

No

Yes

No

No

c9, c10

c8

c2, c3, c4

c0, c1, c11

c2, c3,c4, c5

c7

c6

Cycle 0 Cycle 1 to 7 Cycle 8 Cycle 9

Multiplier Control Unit – State Table

S0

S1

S2

S3

S4

S5

S6

S7

S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0

State 000 001 010 011 100 101 110 111 c0 c1c2 c3 c4 c5

S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0

0 0 0 0 0 0

0 0 1 1 1 0

1 1 0 0 0 0

0 0 1 1 1 1

0 0 0 0 0 0

0 0 0 0 0 0

Inputs: BEGIN Q[0] Count7Inputs: BEGIN Q[0] Count7

S4 S4 S3 S3 S4 S4 S3 S3

S4 S4 S4 S4 S4 S4 S4 S4

S4 S6 S3 S5 S4 S6 S3 S5

S6 S6 S6 S6 S6 S6 S6 S6

S7 S7 S7 S7 S7 S7 S7S7

S0 S0 S0 S0 S0 S0 S0S0

D0=D 0⋅BEGIN +D7+

D1=D0⋅BEGIN

D 2=D 1

+

+

D3=D2⋅Q [0]+D4⋅Q [0 ]⋅COUNT7+

D 4=D2⋅D0+D3+D 4⋅Q [0]⋅COUNT7+

D5=D4⋅Q [0]⋅COUNT7+

0

c6

0

0

0

0

0

1

0

0 0 0 0 1

c7 c8 c9 c10 END

0 1 1 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 1 0

0 0 0 0 0

0 0 0 0 0

1 0 0 0 0

c11

0

0

1

0

0

0

0

0


S0

S1

S2

S3

S4

S5

S6

S7

S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 0

State 000 001 010 011 100 101 110 111 c0 c1c2 c3 c4 c5 c6

S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 1 1 1 0 0

1 1 0 0 0 0 0

0 0 1 1 1 1 0

0 0 0 0 0 0 1

0 0 0 0 0 0 0


S4 S4 S3 S3 S4 S4 S3 S3

S4 S4 S4 S4 S4 S4 S4 S4

S4 S6 S3 S5 S4 S6 S3 S5

S6 S6 S6 S6 S6 S6 S6 S6

S7 S7 S7 S7 S7 S7 S7S7

S0 S0 S0 S0 S0 S0 S0S0

D6=D 5+D4⋅Q [0]⋅COUNT7+

D7=D6+

0 0 0 0 1

c7 c8 c9 c10 END

0 1 1 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 1 0

0 0 0 0 0

0 0 0 0 0

1 0 0 0 0

c11

0

0

1

0

0

0

0

0


S0

S1

S2

S3

S4

S5

S6

S7

S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 0 0 0 0 0 1

State 000 001 010 011 100 101 110 111 c0 c1c2 c3 c4 c5 c6 c7 c8 c9 c10 END

S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0 0 0 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 1 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0 1 0

0 0 1 1 1 1 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0


S4 S4 S3 S3 S4 S4 S3 S3

S4 S4 S4 S4 S4 S4 S4 S4

S4 S6 S3 S5 S4 S6 S3 S5

S6 S6 S6 S6 S6 S6 S6 S6

S7 S7 S7 S7 S7 S7 S7S7

S0 S0 S0 S0 S0 S0 S0S0

c0=c1=c11=D 4

c2=c3=c4=D3+D5

c5=D5

c6=D6

c7=D7

c8=D2

c9=c10=D1

END=D0

c11

0

0

1

0

0

0

0

0

MultiplierCU –One HotDesign

Microprogrammed Control

● Hardwired control unit design – inflexible, difficult to verify.

● Microprogramming– Control Memory

– Microinstructions, Microprogram

– Microassembler

Microprogrammed Control Design

ControlMemory

μInstructionRegister

Decoder

AddressLogic

InstructionRegister

Microprogrammed Controller

CONTROLMEMORY

(CM)

μPCMUX

External address

External conditions

ConditionSelect

Increment

Microprogram Counter

Microinstruction Register μIR

Decoders

Control signals to DPU

Controlfields

BranchAddress

Condition Select

Microinstruction Format

Two's Complement MultiplicationA := 0, COUNT := 0, F := 0, M := INBUS;

Q := INBUS;

If Q[0] = 0 then go to RSHIFT:

A[7:0] := A[7:0] + M[7:0], F := (M[7] and Q[0]) or F;

A[7] = F, A[6:0].Q = A.Q[7:1], COUNT = COUNT + 1,if COUNT7 = 0 then go to TEST1;

if Q[0] = 0 then go to OUTPUT1;

A[7:0] := A[7:0] – M[7:0], Q[0] := 0;

OUTBUS := A;

OUTBUS := Q;

Halt;END:

OUTPUT2:

OUTPUT1:

SUBTRACT:

TEST2:

RSHIFT:

ADD:

TEST1:

INPUT:

BEGIN: c9, c10

c8

c2, c3, c4

c0, c1, c11

c2, c3, c4, c5

c6

c7

END

Binary Microprogram for 2's Complement Multiplication

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

00

00

01

00

10

01

00

00

00

11

0000

0000

0100

0000

0010

0111

0000

0000

0000

1001

Address in CM

Control fieldsCondition select

BranchAddress

0 0 0 0 0 0 0

c1 c2 c3 c4 c5 c6

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 1 1 1 0 0

1 1 0 0 0 0 0

0 0 1 1 1 1 0

0 0 0 0 0 0 1

0 0 0 0 0 0 0

0 0 0 0 1

c7 c8 c9 c10 END

0 1 1 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 1 0

0 0 0 0 0

0 0 0 0 0

1 0 0 0 0

c11

0

0

1

0

0

0

0

0

c0

0 0 0 0 0 0 0 0 0 0 0 00

0 0 0 0 0 0 0 0 0 0 0 00

Two's Complement MultiplierMicroprogrammed Control Unit

CONTROLMEMORY

(10 x 19 bits)

μPC

BEGIN

ConditionSelect

Increment

μIR

0

Q[0]

COUNT7

1

TimingLogic

Branch Address

Reset

{ci}, END

134

2

19

00

01

10

11

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