A Simple and Generalized Space Vector PWMControl of Cascaded H-Bridge Multilevel Inverters

'Kartick Chandra Jana 2Sujit Kumar Biswas Parasuram Thakura'Department of Electrical and Electronics Engineering, Birla Institute of Technology, Mesra, Ranchi, India

2Department of Electrical Engineering, Jadavpur University, Kolkata, Indiakartickjana(yahoo. com

Abstract - This paper presents an automatic switching modulation (SVM) seems most promising since it offers apattern generation for multilevel cascaded H-Bridge great flexibility in optimizing switching pattern design and it isinverters with equal dc voltage sources, based on the space- also well suited for digital implementation. The space vectorvector pulse width modulation (SVPWM) techniques. The modulation for more than three-level inverters is very complexproposed switching strategy generates a voltage vector with due to the high number of space vectors and redundantvery low harmonic distortion and reduced switching switching states. The total number of switching states (Ns) forfrequency. This new control method is an attractive general N level inverter is Ns = Np where P is number ofalternative to the classic multilevel pulse width modulation phases. The actual number of voltage space vectors calledtechniques considering the following aspects, mainly, active voltage vectors given by NV = N3 - (N-i)3 and theminimization of voltage and current total harmonic remaining switching states are redundant switching states.distortion (THD), extension of range of linear operation; 7=and least number of commutations. To solve the problem ofcomputational complexity in multilevel inverters due to thelarge number of space vectors and redundant switching S 3

states, a simple and general space vector PWM algorithm isproposed. Based on this algorithm, the location of the i 4

reference voltage vector can be easily determined and the Scalculation of dwell times becomes very simple. It is also nmentioned that this method requires lower memory spaces Fig. 1. Power circuit of single H-Bridge cellas there is no need of any look-up table. To verify thealgorithms, a seven-level cascaded H-bridge inverter drive For example, there are 343 switching states in a three phase,system was constructed and simulation results are present 7-level inverter, which correspond to 127 active voltagehere. vectors. N. Celanovic has proposed a fast SVM algorithm [7],

but the dwell time calculations seem complex due to the use ofKeywords: Multi-level inverter, SVPWM, redundant states, Euclidean vector space representation. In addition, the

Diode clamped inverter, THD, Cascaded H-Bridge inverter, selection of the switching states in the inverters of higher thanPWM. three levels seems not well documented. B.S. Suh proposed a

good PWM calculation method for three-level inverter [6], butI. INTRODUCTION it is difficult to apply it to higher level inverters. Sanmin Wei

and Bin Wu also proposed a good generalized algorithm but]j/[ULTiLEVEL power conversion has become large, small and medium switching state determinationIYLincreasingly popular in recent years due to techniques is not easy and well documented. In this paper, a

advantages of high power quality waveforms, low general space vector algorithm is proposed, which has uniqueelectromagnetic compatibility (EMC) concern, and low features. As space vector in m-n axis is decomposed in integerswitching losses. The research on the multilevel inverter has scale, which makes an angle of pi/3, it is easy to find outbeen receiving wide attention mainly due to its capability of coordinates of any space vectors. The unique features of thehigh voltage operation without switching devices connected in proposed algorithm are:series. In addition, with the increase of voltage levels, the . The algorithm is very simple, effective and easy toinverter output contain less harmonics and will eventually implement. The location of the reference voltage vector andapproach a desired sinusoidal waveform. Therefore, the the dwell times of the space vectors can be calculated verymultilevel inverters have been selected as a preferred power easily.converter topology for high voltage and high power . For a particular reference voltage it is easy to determine allapplications. Among all the switching algorithms proposed in the redundant switching states and automatically determinethe literature for multilevel converters, space vector

1-4244-0726-5/06/$20.OO '2006 IEEE 1281

the status of switching states whether it is large, small or * In the above explanation, each cascaded H-bridge with equalmedium. voltage is employed. However cells with different voltages

* More interesting is that to obtain minimum harmonicsidistortion proper switching pattern selection is very L L Kimportant. The proposed algorithm automatically generates _3that pattern which need not require any look-up table, hence SW $ C

pr

minimizing the memory requirement. J J I2

- The proposed algorithm is general and can be used in anyhigh-level cascaded H-bridge inverters with least Si Si k

modifications. 53 13 S3

II. CASCADED H-BRIDGE INVERTER S S2 _J LS2A. Working Principle

S<Ii IaX;1 5~~~~3 S=3 S ...3

Fig. 1 shows the single cell of multilevel-cascaded H- Bridgeconfiguration. The output of this cell will have three levels i252namely +V, 0 and -V. The switch position and the outputvoltage and the state of the H-Bridge are given in table I. using none single H-Bridge, a three level inverter can be realized. inverterThese H-Bridge cells can be connected in cascade to obtainmultilevel-cascaded H-Bridge inverter. The power circuit of can also be used. By proper selection of the voltage levels,seven-level cascaded H-Bridge inverter is shown in fig.2. If V some of the lower order harmonics can be eliminated.is the dc voltage of each H-Bridge cell, then a five level . Modular structure makes the power circuit design simple andinverter phase voltage will have five levels, namely +2V, + V, reliable. Under fault conditions, faulty cells can be bypassed0, -V and -2 V. Similarly, seven level inverter will have +3V, and still the inverter will function with reduced output+2 V, + V, 0, - V, -2 V and -3 V. A five-level cascaded H-Bridge voltage levels. Since the cells are identical, faulty unit can beinverter requires two H-Bridges. A seven-level cascaded H- replaced quickly and downtime of the inverter can beBridge inverter requires three H-Bridges. In general a N-level reduced; hence high reliability can be achieved [3].inverter requires (N-1)/2 H-Bridge cells in each phase and * Since the voltage across each cell is V volt, voltage upto N*Vphase voltage will have N levels. volts with large number of steps are available with lower

harmonics content and dvldt stress on switches are alsoTABLE I. SWITCH STATUS AND STATE OF H-BRIDGE decreased.

Sw1thstatus utput v61tae State * The main disadvantage of this topology is that each H-

SI andS0NLO-S OFF +1 Bridge cell requires an isolated dc source. The isolatedSt andSON S2 i S4 OFF sources are typically provided from transformer/rectifier

OR 0 0 arrangements.aSSD S4ON; SI an S3 OFF X_|___I

C. Pre-treatment ofthe Basic Vectors

B. Features ofCascaded H-Bridge Inverter A typical seven-level cascaded H-bridge inverter is shown inFig.2, where a separate dc power supply is used for each H-

Higher voltage levels can be synthesized using devices of Bridge. Its corresponding space voltage vector diagram islow voltage rating. If V is the dc voltage of each of the H- illustrated in Fig.3, in which the vectors for the 3, 5, and 7-Bridge cell, then each device will experience a off-state level inverters are also illustrated. For the 7-level inverter,voltage of V volts and a N-level cascaded H-Bridge can there are 216 small triangles and the vertex of each trianglesynthesize peak-to-peak voltage of (N* V) volts . Phase represents a space vector.voltage of an N-level cascaded H-Bridge will have N levels; The hexagonal vectors can be divided into six majorhence wave shape will be improved and will result in triangular sectors (I to VI). Only the first sector of theimproved THD Improved wave shape can be obtained even coordinate is used because the vectors located in the otherwith fundamental frequency switching and step modulation. sectors can be transformed to first sector by clockwise rotating

* Low switching frequency will result in reduced switching by an angle of k*(pi 3) k =(1,2,3,4,5 for sector 2 to 6). As allloss in the devices. The switching angle of each cell can be the sectors are identical, only details of sector I is given inselected to eliminate some ofthe lower order harmonics. Fig.4. Usually, a (M±+1)-level inverter is discussed here as

shown in Fig.4. By decomposing Vrej into m and n axis it is

1282

easy to obtain the m and n axis component of Vrej as Vrm and n *T + n2 *7T + n *7T = T (4)Vrn as given next: T 2 3 3 PWM

+ 2 3 = TPWM (5)Vrm = (2*M*Vref/3Vdc) sin (Tz//3- 0) (1) WhereTpwm isPWMtimeperiod.Vrn (2*M *Vref / 3Vdc) sin(0) (2)

The method demonstrated how simple it is to determine theWhere 0 is speed of rotating reference vector, triangle that reference voltage falls in and to calculate the dwell

sector | atimes. More importantly, the algorithm has another fewII n-Axis features:

6 a) It is a general algorithm, which can be used forinverters with any number of voltage levels up to seven levelS C sectorL$CtO

A E J|1 < 5X i4L e and eventually can extend beyond seven level with some

modification of inverter power circuit;rn-A li m4xis b) There are only two sets of equations for dwell time

77 . ) , iJcalculation. Compared with the Cartesian coordinate systemwhere there are many sets of different equations for the

secornA sectorBCalculation of the dwell time..4

7vic) The proposed algorithm considers over-modulation

6- X case also. It is easy to judge whether SVPWM is in over-secthr modulation region or not, simply by checking the following

_:8 I

inequality:Q9 '6 UF '2 _ 4 H_VF Yif ( Vrm ± Vrn) > MV it becomes over-modulation.

Fig. 3. Voltage vectors of 3,5 and 7-level voltage sourceinverters. A useful method to handle this situation is to multiply the

original vector say Vrm and Vrnby a factorM (Vrm + Vrn) andIII*PROPOSED ALGORITITh4 the consequent steps are same as discussed.

A. Determination ofLocation ofReference n-axis AVector. .~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

As the number of levels is increased, the number of triangleincreases in this way: NT= 6(N-1)2For example a 7-level inverter, total number of triangle is 216,mn {lqlbut the selection of triangle by the proposed method is very Vr 1,11*simple and generalized. Any space vector located in any sectorand in any triangle can be calculated easily from 0 and thevalue Vrm and Vrn explained below. Assuming Vref and 0 **should be such that it lies in the rectangular area specified byDEGF shown in Fig. 4. After calculating Vm and Vn, calculatethe lower rounded integer value (m and n) as shown below: Fig.4. Decomposition of Reference voltage in in-n axisSay, Vrm = 2.6&V,r= 1.85.

Assuming m= int (2.6) =2 &n = int (1.85)~ 1.GnrlRltoshpbtenSaeVcoThese m and n are defined by vector (m , n) in in-n axis. If(Vm C.Gnera Relathiongttsh btenSaeVco

Vrn) <= (m± 1) then Vref located in the left bottom triangle s

B. Dwelling Time Calculation represented by more than one switching state. For instance,space vector (1, 1) in Fig. 5. has five redundant switching

The dwelling time calculation for each switching state is very states composed [-1,-2,-3], [O,-1,-2], [l,O,-1],[2,l,O] andsimple and generalized. Suppose at any instant the Vref located [3,2,1], all of which produce an output voltage with the same

in the Triangle GEF shown in Fig.4. The corresponding three magnitude and phase angle. With the increase in the voltagenearetspce vector are (in1, i) (in2, n2) Aand(i3,3) levels, there exist more redundant switching states. It is

Acording to votgetm blnc equ ?7_2A1Tion it can be solv deiabl to fi.nd a gnea exreso whc decribe the X8Xthredwlligtm T1, ' and ]' trasa folrlos rPoellationhi bewensace vetorsm and thercepndin11~~~~~~~~~~~~~~3 swthin stte fray cacae llH-BriW-JfWEdgemltiee inverter.+ m2T 3T

* A; wv Xt1283_Xj

Space vectors in the 60coordinate system shown in Fig. 4 can problem. In this paper, the redundancy is employed tobe generally expressed by (m, n), where m = 1, 2,....., 2p, minimize the voltage harmonic distortion only.

and n = 1, 2..., 2p. The integer number p is defined by,p = (N - 1) 12, where N is the number of phase voltage

levels of the inverter, which is always an odd number for the 0.6

cascaded H-bridge inverter. .5 1 5The relationship between a space vector (m, n) and its 05 15

switching states for three phases [Sa, Sb, Sc] is obtained by a 0 1 24detailed study on all the possible states in a multilevel inverter.The results are given by 0,3 23

Sa = -p, -p+l,-p+2 . ' P (6)

S =Sa-S M (7) /\SC=Sb-n (8) 1,0 20 0 4, 5.0 6,0

For a given space vector (m, n) the number of switching statescan be obtained by Fig.5. Graphical Representation ofproposed Algorithm

N sw = N - (m + n) (9) A. Determinations ofMean, Small and LargeThese equations are the general expression of switching states Switching Statesand can be applied to any cascaded multi-level inverter up toseven levels. Any space vectors (m, n) in Fig. 5.can be classified into the

Alternatively for a given space vector (m, n), all of its following two categories:switching states can also be calculated by Category 1: even vector - the sum of its coordinates (m, n.) is

an even number;S =(m+n-p),(m+n-p+1), ...... ,p (10) If both m and n are even number or both is odd then thea corresponding switching state is mean state and this switching

Sb =(n-p),(n-p+1)...........(p-m) (11) states canbe expressed as:

Sc =(-p),(-p+l1)............(p-rm-n) (12) Sam ={(m+n-p)+p}/2=(m+n)/2 (13)sbm =j(n- p)+(p-m)j12 =(n-m)12 (14)

TABLE II: RELATIONSHIP BETWEEN SWITCHING ={(-p)+(p-m-n)}/2=-(i+n)/2 (15)STATES IN VARIOUS SECTORS SCM

Sector Switching states of Phase A,B and C Where S., Sbm and Scm are mean switching states for phaseSector Sa Sb Sc A, B, and C.

I Sa Sb ScII - Sb -Sc -Sa For an even vector, each component of its mean switchingIII SC Sa Sb state is an integer, and the state can be implemented. ForIV -Sa sab -Sc { instance, space vector (1,1) in Fig.5 has five states: [-1,-2,-3],

IVb-Sa -Sb -Sc [0, 1, 2], [1,0, I], [2,1,0] and [3,2,1]. It is a mean state and itsV Sb Sc Sa mean state is [1, 0, -1], which can be realized by the inverterVI -Sc -Sa - Sc with output voltages of, Sa 1, Sh= 0 and Sc= -1. However,

for an odd vector where (m + n) and (m - n) is an odd number,its mean state cannot be implemented since the inverter cannot

IV. SELECTION OF SWITCHING STATES produce half-level voltages. In this case, a small or largeswitching state can be used.

In the multilevel inverter, the redundant switching states Category 2: odd vector - the sum of its coordinates (m andincrease with the voltage level. For example, the 5, 7, and 9- n) is an odd number.level inverters have the redundant states of 4, 6 and 8, Case 1: Ifm is odd and n is even it should be large state, canrespectively for zero voltage vectors. In the diode clamped be expressed asmultilevel inverters, the redundant switching states can be S I(m+n+1)/2 (16)utilized to balance the voltage of capacitors in the dc link. Theacascaded H-Bridge inverter inherently does not have this =h=(n-m+1)! 2 (17)

Scl = -(m +n -1) /2 ~(18)

1284

Case 2: If m is even and n is odd it should be small states implement and also gives excellent harmonic performance.expressed as: Simulation results shown later illustrate the inverter phase

Sas = (m+n-1)/2 (19) voltage as well as line voltage which obviously contain muchless harmonics compared to other existing multi-level

Sbs = (n-m-1)/2 (20) techniques.Sc= (+1+ )/2 (21)Qns=(m+1+1)12 (21) C. Switching Sequence Design

stE±-t The switching sequence design has to meet a number ofrequirements such as:

a) Minimize the number of switching per sampling period,Fid the refererce vdltage Fref ard Angle 0 b) One voltage level change per commutation of switching

devices, andFirui the ectoofre:rencvoligec) Adoption of the above mentioned method. For example,

th er oflfeI rce v.l when the reference vector lies in triangles T1 and T2 of avecbr)a~o ~O particular rectangular area DEGF, shown in Fig. 5, switching

sequence for T1 and T2 are given in Fig.6, where D, E, F and GFindi cut VnmVm (mn& naxis proleciorO Of are the vertexes (space vectors) of the triangles DEF and EFG.

The number in each column in Fig.7 (a). represents theC alculate m =int( Vr* r134V-V switching states of a given space vector at F,D and E point and

TF,TD and TE are the dwelling time of those point respectivelyfor three-phases.

S elect the liangle for any Vref orits (ni,n)fin cut te thee vertexxes den Fa E E D FFF G E E

___________________no)_I_I_2__ I1 2I )IIFirnoutthliedweft.e I ..es(T T,T Tz y 4 4

1

soltvi voltage-brie balamre equatin Sb

Cakualate all tk- redurdaiut switkhuh states(Sa4,Ikb) for any space vItage v or (ni,] . S6

W.~~~~~~~~~~~~~~~ 2 2 2 2. ,2Dete nuetedesired switchirg state (iean, laTie arTI

small) ±. a.(r ,a. ani knc.eme fir-all gate pulses (a Y lxmgm'Tll()Vlinr

Select tkeswitdiir sequence whemi only]one voltage level charges per sartplh' Fig. 7. Switching Pattern for reference Voltage Vector V,

peiiod and ndni±rnn switzchng conurcutation Located in the Triangle DEF and Triangle EFG

V. SIMULATION RESULTS AND DISCUSSIONGet sequence of all gatE pules(Tax, Tbx; T4cx for tfinee phases The simulation results are presented. The proposed

algorithm has several attractive features. The output voltage isFig. 6. Flowchart of proposed algorithm compatible with load as different voltage ranges are obtained

by simply changing the modulation index (min). Fig.8 and Fig.9B. Selection ofSwitching States show the output phase voltage and IM stator cuff ent at

modulation index (mi) of 0.8. Fig. 10 shows the line voltageTo minimize the voltage harmonic distortion, the for in= 0.8. For equal dc voltage in the input, maximum

arrangement of switching states is as follows: output has of seven levels and wave shape is near sinusoidal.

AcrIn to th au fthe ers spc veto (i1 ,TeVTDo ievlaehs vau 5.7 00 ol,frI

(in2,~~~~~~n. an (in, n3) o,f,a...triangle..,the corsodn swthng 08FrmFg 10, it is clea tha exep fndmna oteIoereunansat,owhic is extremelys simpl an eas to ofT fite ccutL/=L LLLLLL LS _L'LL'_L' L; LLLL '1285 _ **

VI. CONCLUSIONS

..............A simple and general space vector PW M\ algorithm has beenfo | proposed in this paper The power circuit is designed to have

U11 S 1l1ll1 1 -|- | | | | | || modular structure. All the H-Bridge units are identical. Soreplacing the faulty units will be easy and quick. The proposedalgorithm substantially simplifies the calculation of spacevectors and their corresponding dwell times. Based on the

|.......... proposed algorithm, the generation of automatic switching................pattern for the cascaded H-Bridge multilevel inverters has been

developed. This algorithm features easy implementation andmore importantly, minimum harmonic content in the inverteroutput voltage and current of the Induction Motor Load. Themost important aspect of the proposed algorithm lies in its

Fig.8.OutputPhaseVoltageofSeven-levelinverterfor generality. This can be used in any high-level cascaded H-

modulatin*index mi) 0. bridge inverters. This algorithm is verified throughMATLAB/SIMULINK simulations.

INDEX:Type of Load: IMRating of Load: 5 HP, 460 V, 60 Hz, 1750 rpm

nL .Stator Resistance and Inductance: 0.01965 p.u and 0.0397 p.u.Rotor Resistance and Inductance: 0.0 1909 p.u and 0.0397 p.u.Mutual Inductance: 1.359 p.u.

liii / \ ,4 I rSampling time Ts=2e-6 sec, Switching frequency Fc=3960 lz.

.7............ REFERENCES

11| | [1] Lei Hu, Hongyan Wang, yan Deng and Xiagning "A simple SVPWM....-------.--------------------------------------------------------------------Algorithm---of.lMultilevelituinverter".nvertEEE.PowerIE oElectronicsnicspecialistst

conference, Achen, 2004.[2] Sanmin Wei and Bin Wu "A General Space Vector PWM control

*, ,, ,5,1 Algorithm for Multi-level inverters" IEEE 2003, pp 562-568.[3] M.L. Tolbert and F.Z. Peng, "Multi- Level converter for Large Electric

Fig.9.Outputlinedfor m 008 of seven- Drives, IEEE Trans. Indus. Applica., Vol 35, No.1,1999. pp 36-44.Fig.9. Output line current to IM load for mi 0.8 of seven- [4] N. Celanovic. And D.Boroyevich. "A Fast Space Vector Modulationlevel inverter Algorithm for Multi-level three Phase Converters." IEEE Trans on

Industry Applications. Vol.37.No. 2 2001. pp 637-641FFT wrhdo. 0 Er 12 alh Oe! b I h t [5] B.S. Suh, and D.S. Hyun, "A New N-Level High Voltage Inversion

System," IEEE Trans. On Industrial Electronics, Vol.44, No.1, 1997,

ppA107-115.[6] B.S. Suh, G. Sinha, M.D. Manjrekar, and T.A. Lipo, "Multilevel power

_~ F 9 4 i conversion-an overview of topologies and modulation strategies",

cm_ _ _ _ _ _ _ _ _ _ __. International Conference on Optimization of Electrical and Electronic

0 DA.2.M04 O.0 M 08 Equipment (OPTIM), Vol.2, 1998, ppAD11-AD24.TIrr5 M

Funniflrrla [t-Iz.-i THD-- &74% [7] N. Celanovic, and D. Boroyevich, "A fast space vector modulationB t | 1 algorithm for multilevel three phase converters," IEEE Trans on Industry

Applications, Vol.37, No.2, 2001, pp637-641.[8] D. A Rendusara, Cengelce, Prasad N. Enjeti, V. R. Stefanovic and J. W

Gray, " Analysis of common mode voltage- "nuetral shift" in medium15 I I | voltage PWM Adjustable speed drive system," IEEE Trans. On

Power Electronics, Vol.15,No.6,, ppll24-1133. Nov. 2000[9] Keith Corzine, "A New Cascaded Multi-level H-Bridge Drive"

a_010 EIJ so . 5u 1en IEEE Trans. On Power Electronics Vol. 17. No. 1 Jan 02.

Fig.10. Output Line Voltage of Seven Level Inverter andits FFT analysis for m1 = 0.8

1286