JOURNAL OF COMPUTER SCIENCE AND ENGINEERING, VOLUME 11, ISSUE 2, FEBRUARY 2012

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© 2012 JCSE

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Control Unit Design and simulation of an experimental RISC CPU

Ajay Anant Joshi, Siew Leong Lam and Yee Yong Chan

Abstract— An 8-bit RISC-CPU is designed at gate level using completely custom chip approach. CPU has an 8-bit integer unit

and 16-bit floating point unit. The circuits are optimized by using more efficient algorithms. The algorithm discussed in this paper

was applied for an 8-bit CPU design, however there is no reason that this couldn't be used for more powerful and serious CPU

development. This paper discusses the design of a Control Unit section of the said CPU with respect to algorithm and VHDL.

The project is implemented using VHDL and simulated using Altera MaxPlus II sim software which can map the design into

Altera CPLD.

Index Terms— CPU, simulation, algorithm, Floating point unit, CU, Control Unit, VHDL. .

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1 INTRODUCTION

his Paper focuses on the design and implementation of a Control Unit, which is a very important function-al block of an experimental CPU with 8-bit integer

unit and 16 bit Floating point unit. CPU has 4x16bit FPU registers, 16 bit data, address busses and 16-bit program counter. Data path is where most of the operations are done on by the processor's control unit. A Datapath is a system hardware that performs data processing operations [6, 7, 8, and 9]. There are seven functional units, out of which 3 for FPU. This paper dis-cusses the design of a Control Unit only. Logic of algo-rithm is discussed in detail and implementation block diagram along with the VHDL code and simulation re-sults. Reduced Instruction Set Computer (RISC) focuses on reducing the number and complexity of instructions in the machine [4, 5]. The design and methodology is in line with earlier work done [1,2 & 3] Focus is on im-proved and relevant design.

2 THE DESIGN

2.1 Brief

The circuit of the control unit and how it decodes the instruction to control the overall operation of the processor will be elaborated in the subsequent sections.

The block diagram in Fig. 1 shows the interconnection between each component inside the processor's control unit. In general, there are four main components. They are 16-bit program counter, 25-bit instruction register, wait state counter, interrupt flag and instruction decoder

unit. The functions and circuit of these components are elaborated in the following sections. Following sub-section discusses Components in detail.

2.2 Components

16-bit Program Counter :(Larger diagram on page 7)

Program counter stores the address of the next instruc-tion. The stored address is connected to an external in-struction memory to fetch the instruction at the beginnin-gof every cycle. As we can notice from the circuit, it ac-cepts 16-bit data, increment, LT and RT signal as input and the resulting address as the output. When PCI (In-crement PC) is '1', the address would be incremented by 1. This is normally done after an instruction has been

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Ajay A. Joshi is with the Department of Electrical & Computer Engineer-ing, University of the West Indies, St. Augustine Campus, Trinidad.

Siew Lam. Engineering project student at, Multimedia University, Jalan Multimedia, Cyberjaya, Malaysia.

Yee Chan Engineering project student at, Multimedia University, Jalan Multimedia, Cyberjaya, Malaysia.

Fig. 1 Control Unit Block diagram (Larger diagram on page 7)

T

Fig. 2. Program Counter.

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fetched from the memory On the other hand, when LT is '1' or when there is an interrupt request, current stored address will be saved into a temporary register. At the same time, an interrupt vector will be loaded into program counter so that the processor could fetch the next instruction from interrupt service routine. The 16-bit vector address is fixed at "FFFO". When return instruction is encountered, RT will be active.

Consequently, program counter will be loaded with the saved address.

Figures 2 & 3 show PC gate level design & transistor

count respectively. Figure 1 is also show on page .... for more clarity.

Delays: Delay (based on 0.18 micron): In calculating delay, we look at the critical path for in-

crementing the circuit and also critical path for loading. Critical path delay (for incrementing) = 5(25 +54) ps + (31 + 41 + 4l)ps = 508 ps Critical path delay (for loading) (18+41 +25)ps = 84 ps Delay (based on 0.5 micron): Critical path delay (for incrementing) =5(1.4 + 1.4)ns + (4.2 + 1.8 + l.8)ns =21.8ns. Critical path delay (for loading) =(1.0 + 1.8 + l.4)ns =4.2ns Program Counter VHDL Code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity program_counter is port ( CLK, LT, RT, PCI : in std_logic; D: in std_logic_vector(lS downto 0); O: out std_logic_vector(l5 downto 0)); end program_counter; architecture struc of program_counter is

signal temp: std_logic_vector(lS downto 0); begin process(CLK) begin if (CLK'event and CLK = '1') then ifRT = '1' then temp<= D; elsifPCI = '1' then temp<= temp+ "0000000000000001"; elsifLT = '1' then temp<= "1 1 1111 1 111110000"; else temp <= temp; end if; end if; end process; O<=temp; end struc; Simulation results :

In this simulation, the stored address is assumed to

be 5678 H This address ts restored when RT = '1'. And interrupt vector address FFF0 H is loaded when LT is '1'

Instruction Register Design As its name implies, this register stores instruction

fetched from external instruction memory. The register is 25-bit wide to accommodate the instruction format. When the load instruction (IL) signal is active, the next instruc-tion will be stored, replacing the executed instruction.

Figure on page 8 Shows the design of instruction regis-ter.

Delay (based on 0.18 micron): There is no gate before the input of each D flip-flop; hence, the delay caused by D flip-flop is be calculated, which is 116ps. Delay (based on 0.50 micron): The delay in this case is 6ns.

Instruction Register VHDL Code:

library ieee; use ieee.std_logic_1164.all; entity instruction_register is port ( D :in std_logic_vector(24 downto 0); CLK, IL: in std_logic; 0 : out std_logic_vector(24 downto 0)); end instruction_register; architecture behavioral of instruction_register is

Fig. 3. Transistor count for Program counter.

Fig. 4. Simulation. (shown on page 7 for more clarity)

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signal temp: std_logic_vector(24 downto 0); begin process(CLK) begin if (CLK'event and CLK = '1')then ifiL ='!'then temp<= D; else temp <= temp; end if; end if; end process; O<=temp; end behavioral;

Simulation results : From simulation results as seen from fig. 7 on page 8,

When IL signal is '1' during the positive edge clock pulse, the input is stored inside the register.

Wait state counter :

This section describes the design, delays VHDL code and simulation of a Wait state counter.

As known, the speed of external memory is slower than the processor in almost all cases. Therefore, during memory access, the processor has to wait for a few clock cycles before the data is read or write into the memory. Hence, a 3-bit wait state counter is designed to indicate the number of clock states when the processor is execut-ing memory instruction. In this project, we assume that 8 clock cycles is needed.

Figure 8 shows the gate level design of the WS counter.

It is observed that : (0.18micron) Critical path delay = (18 + 67)ps = 85ps (0.50micron) Critical path delay = (1.0 + 2.4)ns = 3.4ns

Figure 9 given below shows the transistor and delay de-tails.

Wait State counter VHDL Code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_Wlsigned.all; entity wait_state_counter is port ( CLK, LD, start :in std_logic; Z : out std_logic); end wait_state_counter; architecture struc ofwait_state counter is signal temp: std_logic_vector(2 downto 0); begin process(CLK) begin if (CLK'event and CLK = '1')then ifLD = '1' then temp<= "111"; elsif start= '1' then temp<= temp - 1; else temp <= temp; end if; end if; end process; Z <= (not temp(2)) and (not temp(!)) and (not temp(O)); end struc;

Wait State counter Simulation results :

Fig. 9. Wait State counter Transistors and delays

Fig. 8 Wait State counter

Fig. 10. Wait State counter simulation waveform

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LD =Load signal. When this signal is active, the counter will be loaded with value 7. Then, as the start signal be-comes active, the counter is decremented by 1 after each clock cycle. When the COWlter is '0', output Z (to indicate zero) is '1'.

Interrupt Flag : The interrupt flag will be set to '1' when there is an in-

terrupt request at the end each instruction cycle. Nested interrupt is not supported. Therefore, it will only accept interrupt request again when this flag is reset to '0'.

The gate level design is shown in the figure given be-low.

Transistor count and relative delays are shown below.

Interrupt Flag VHDL Code:

entity int_flag is port ( CLK, LT, RT: in std_logic; Q : out std_logic); end int_flag; architecture struc of int_flag is signal temp: std_logic; begin process(CLK) begin if (CLK'event and CLK = '1')then ifLT='l' then temp<='!'; elsifRT= '1' then temp<= '0'; else temp <= temp; end if; end if; end process; Q <=temp; end struc;

A very simple simulation is done on the behavioral code description of the interrupt flag. When an interrupt occurs or LT = '1 ', this flag will be set to '1'. On the hand, it will be reset when the processor finished servicing in-terrupt routine or RT = '1'.

Instruction Decoder Unit: This instruction decoder unit is similar to the decoder

unit that is found in the control unit of Floating-point Addition and Floating-point multiplication, except that now it decodes in-coming instruction and sends control signals to other functional units in datapath.

ASM chart: As a first step, ASM chart has to be defined. This chart

is important as it defmes the control signals to be generat-ed for each state in order to coordinate the sequence of operations. Figure 12 shows an ASM Chart.

Fig. 11. Gate level design of Interrupt Flag

Fig. 12. Interrupt Flag Simulation

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Next, a simplified ASM chart is drawn as shown in the figure 14, to define the transitions from one state to another. This is done by eliminating conditions that do not affect the transition to next state and also the condi-

tional boxes.

State table as shown in figure 14, is build based on the

simplified ASM chart which only concerns with the conditional signals that cause the change of state.

Boolean functions are given below

Circuit diagram of instruction decoder:

Circuit diagram is shown in the figure 16. This figure has been added on page 7 for more clarity.

2 CONCLUSION:

Control Unit design worked as per our expectations in sense that simulations and delays were in line with our design target. Simulation results were good and encouraged us to go ahead and refine the design if required to make the unit ready for implementing on CPLD.

Fig. 14. Simplified ASM Chart.

Fig. 13. ASM Chart

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REFERENCES

[1] A.A.Joshi, S.L.Lam, and Y.Y.Chan, “Algorithm & design of an efficient

floating point ADD/SUB unit for an experimental CPU”, International

Journal of Intelligent Information Technology Application, 2009, 2(6),

pg. 273-278

[2] A.A.Joshi, S.L.Lam, and Y.Y.Chan, “"Design & simulation of a Bar-

rel shifter for the 16-bit floating point unit of an experimental

CPU", Journal of Information and Communication Technolo-

gy,ISSN 2072-1471, Volume 2 [5] 2009.

[3] A.A.Joshi, S.L.Lam, and Y.Y.Chan, "Design of an Improved Multip-

lier Unit for an Experimental RISC CPU", Electrical Power Sys-

tems and Computers, Lecture notes in Electrical Engineering 99

Vol. 3, pp. 323–330. Springer-Verlag Berlin Heidelberg 2011,

ISBN 978-3-642-21746-3

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[5] V.P. Heuring, and H.F. Jordan, “Computer Systems De-

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V­141­V­144.International Symposium on Circuits and Systems

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D. Pnevmatikatos, G. Konstantoulakis, J.A. Sanchez­P., “De-sign and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high­speed net-work processors units”, Microprocessors and Microsystems 31, 2007, p 188–199.

[8] L. Dongjun, Y. Jingkun, L. Daguang, J. Chris, “Data-path verification with SystemC reference model”, ASICON 2005, 6th International Conference on ASIC, 2005, Proceedings, v 2, p 906­909.

[9] J. Hongtu, O. Viktor, “FPGA implementation of control-ler­datapath pair in custom image processor design”, IEEE International Symposium on Circuits and Systems, Pro-ceedings v 5, p V­141­V­144.

Ajay A. Joshi Ph.D, D.F.T., is currently with The Department of Electrical & Computer engineering, University of the West Indies, St. Augustine, Trinidad. Earlier has been Head of Technology at the IBM advanced training center in Nasik, India. and Member of the Faculty at Multimedia University, Malaysia. He is an Associate editor of Re-search Journal of Science, Technology and Engineering, Maxwell Scientific, UK, Chair of Computer and Communications group, IEEE Trinidad and Tobago chapter & Tech Consultant to Den Helder Inc., New Jersey, USA. He is a Principal Investigator of NVIDIA Cuda Teaching Center at University of the West Indies. Research interests are Advanced Computer Architecture, Digital Logic design & High Performance Computing

S. L. Lam B.Eng Multimedia University, Cyberjaya, Malaysia. Siew is an excellent design engineer of Digital Circuits and has been a project student of A.A.Joshi Y. Y. Chan B.Eng Multimedia University, Cyberjaya, Malaysia. Yee is an excellent digital design engineer and has been a project stu-dent of A.A.Joshi

Illustrations:

Fig. 15 State table

Fig. 16. Instruction register design. (Larger diagram

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Program counter logic diagram

Program Counter simulation

Instruction Decoder circuit

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Block diagram of Control Unit

Instruction Register

Instruction Register Simulation