copyddd-snake final report

8/2/2019 Copyddd-Snake Final Report

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Ha Noi University of Science and Technology

School of Electronics and Telecommunication

Report

Project name :Building PONG GAME on DE1

hardware foundation of Altera

Guiding lecturer : Phm Ngc Nam.

Members : ng c TnT3

Nguyn Minh cT3

ng Minh cT4

H Minh cT11 - 20070840

Nguyn Mnh tT2


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Content

1 Thankful expression ......................................................................................................2 Overview .......................................................................................................................

2.1 Purpose .....................................................................................................................2.2 Basic foundation ......................................................................................................2.3 Project requirement ..................................................................................................

2.3.1 Functional requirement .....................................................................................2.3.2 Non-functional requirement ..............................................................................

2.4 Particular works .......................................................................................................2.5 Achivement ..............................................................................................................

3 Used technology ............................................................................................................3.1 DE1 Kit Hardware ......................................................................................................3.2 Quartus II Sofware ...................................................................................................

4 Block diagram of the system .........................................................................................4.1 Keyboard ..................................................................................................................4.2 Display .....................................................................................................................4.3 ROM .........................................................................................................................4.4 Processing unit .........................................................................................................

5 PS2 Keyboard ................................................................................................................5 Block for receiving PS2 data ....................................................................................

5.1.1 Giao tip vt l cng PS2 ..................................................................................5.1.2 Khi nhn d liu PS2 ......................................................................................

5.2 Mch giao tip vi PS2 Keyboard ...........................................................................5.2.1 Tng quan v m ha bn phm ........................................................................


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5.2.2 Mch giao tip PS2 keyboard ...........................................................................6 VGA ...............................................................................................................................

6.1 Graphic.......................................................................................................................6.1.1 Introduction .......................................................................................................6.1.2 VGA Gate ..........................................................................................................

6.2 iu hin vio .................................................................................................6.2.1 Mh ng VG ..........................................................................................6.2.2 Mh to pix ...................................................................................................

6.3 VGA text ..................................................................................................................6.3.1 Gii thiu...........................................................................................................6.3.2 To txt..............................................................................................................6.3.3 Font ROM .........................................................................................................6.3.4 Mh to txt n .........................................................................................6.3.5 T Font.....................................................................................................

7 C c xy dng game ..............................................................................................7.1 Xy dng mn hnh new game ................................................................................

7.1.1 Layer nn ...........................................................................................................7.1.2 Text layer ...........................................................................................................

7.2 Xy dng mn hi hnh ........................................................................................7.2.1 Text....................................................................................................................7.2.2 Header ...............................................................................................................7.2.3 B tng ..........................................................................................................7.2.4 Bng mi ...........................................................................................................7.2.5 Rn ....................................................................................................................

7.3 Khi no kt th tr hi? ........................................................................................


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7.4 Xy dng phn kt th tr hi ..............................................................................7.4.1 Mn hnh tnh im ...........................................................................................7.4.2 Mn u im v tn ngi hi .......................................................................

8 Kt lun ..........................................................................................................................9 Cc ti liu tham kho ...................................................................................................


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1 Thankful expressionWe would like to give thankful voice to lecturer Nam who guided and helped

through the implementation process.

2 Overview2.1 Purpose

- Designing PONG GAME based on DE1 kit.- Holding knowledge of DE1 hardware.- Expanding programming capacity with C language.

2.2

Basic foundation- Basic knowledge on FPGA and C language.- Experience for reading and seeking English or Vietnamese documents.

2.3 System requirement2.3.1 Functional requirement

- Its sign for 2 pyrs.- Friendly interface and easy to play, using PS2 keyboard to play and VGA monitor

to display game objects and score.

- Game has three level : Easy, Medium, Hard. The speed of the game would beraised according to each level.

- One player can select the levels in the list to play.- If one person win 3 set, the person will be winner. Each set has 11 scores.- The players can pause the game any tim y prssing- A piece of music starts game.

2.3.2 Non-functional requirement- System is built on DE1 kit- The system works at frequency of 50MHz.


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2.4 Particular work..

2.5 AchievementThe game is basically completed with the friendly interface and not complex to play.

Handling ball reflection is quite well.

2.6 ShortcomingSomtims, strting gm is sti ow n .

3 Used technology3.1 Hardware3.1.1 DE1 KitDE1 board is a development tool has many features, the board allow the user to

implement from simple circuits to complex projects. Particularly, the following hardware

is provided on the DE1 board :

tr Cyon II 2C20 FPG vi

tr Sri Configurtion vi EPCS4

US str (on or) for progrmming n usr PI ontrol; both JTAG and Active

Serial (AS) programming modes are supported

512-Kbyte SRAM

8-Mbyte SDRAM

4-Mbyte Flash memory

SD Cr sot

4 pushutton swiths


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10 togg swiths

10 r usr LEDs

8 rn usr LEDs

50-MHz oscillator, 27-MHz oscillator and 24-MHz oscillator for clock sources

24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks

VG DC (4-bit resistor network) with VGA-out connector

RS-232 transceiver and 9-pin connector

PS/2 mous/yoard connector

Two 40-pin Expansion Headers with resistor protection

Powr y ithr 7.5V DC ptr or US


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Figure 3.1.1 Kit DE1

3.2 C languageC is a popular language used for many embedded systems. We use the language to

programme the NIOS II on the SoPC system.

4 Block Diagram

PONG MAIN

KEYBORAD VGA MONITER

IC CODEC

KEYBOARD

CONTROLLER

PONG CORE

VGA CONTROLLER

AUDIO COTROLLER

Figure 4. Block Diagram


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There four key parts in our project : VGA controller, PS2 controller, Audio controller and

Pong main with input : PS2 keyboard, and output : VGA display, speaker. Data from

keyboard to control balls and paddlers and the score calculation would be processed by

the Pong main.

5 PS2 KeyboardTo control the direction of movement of the slider up and down, enter the level to

start playing, pause the game or to save the name if the player scores high ... we have

to use akeyboard.

Currently the market has two types of keyboard is usb port keyboard and keyboard

port ps2.Trong pong game made by the group selected the ps2 keyboard to use. We

will turn to find out about this type of keyboard as well as design mass necessary to

be able to receive data sent from the keyboard correctly.

5.1 Data Blocks received PS25.1.1 Physical Interfaces PS2 port

Figure 5.1 Port PS2

Start Bit

(1 bit)

Data Bits

(8 bits)

Odd Parity Bit

(1 bit)

Stop Bit

(1 bit)

Figure 5.2 Description of a data block

A PS2 port has four pins: data ps2d pin, clock pin ps2c

and two pins are the source VCC and ground pin which

power is provided by the host VCC.

The data from the host keyboard to be transmitted over

a serial data pin standard UART. The process begins

with data transfer a start bit, 8 data bits, 1 parity bit and

1 stop bit


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Clock of the keyboard is transmitted through the pin ps2c frequency range from 10kHz

to 16.7 Khz, ps2d signal must be stable for at least 5us front and back up and down

slopes of the signal ps2c. We can see this by describing the drawing:

Hnh 5.3

5.1.2 PS2 receiving data blocksOrder to collect data rather than a sampling design will use a detector circuit of the signal

slopes down ps2c reference point. The input circuit includes receiving signals from ps2c

ps2d and keyboard, the host clock signal, a system reset signal and a signal for receiving

data from the keyboard. The output of the circuit will be the 8 bit data signal and a signal

rx_done_tick. This signal is high at every clock cycle.

We have received the block diagram of the circuit:

KEYBOARD

Filter & Falling

Edge ps2c

ps2_rx

ps2c

ps2d

Falling edge

rst

clk

rx_en

dout (7 downto 0)

rx_done_tick

clk

Figure 5.4 Block diagram of the circuit to receive data


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ASM receives block diagram of the data:

Rx_en=1 andFail_edge=1

b>1)

n1)

Fail_edge=1

n


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- The circuit communicating with PS2 KeyboardIn this section we'll learn how to encode keyboard design and a circuit for decoding the

commands sent from the keyboard to the Host.

5.1.3 Overview of the keyboard encoderA keyboard is a matrix of keys. It embeds a microcontroller to regulate the operation of

the keyboard. There are three modes of operation of the keys can occur are:

- When you press a key, then make the key code is transmitted.- When we hold a large enough down time of about 0.5 s, the code will begin to make a

repeat with a cycle speed of 100 ms identified.

- When you release the keys of the keyboard, the break code will be transmitted.The figure below shows the code of the keys make the keyboard:

Figure 5.6 Keyboard

For the keyboard usually make its code size is 1 byte longer to extend the key size is from

2 to 4 byte for byte. PS2 keyboard will begin serialization code depending on the

operation of the keyboard. For example, you press and release the first key A make code

is sent to then break its code:

1C F0 1C

For example key expansion up button:

E0 75 F0 E0 75


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If you press a key long enough then release the make code will be sent several times:

1C 1C 1C .. F0 1C

If multiple keys are pressed simultaneously, the code is sent in turn make code and break

code of two keys. For example, you press two keys simultaneously, the Shift and A COE

will be sent to:

12 1C F0 1C F0 12

5.1.4 PS2 keyboard interface circuitPS2 keyboard interface circuits work to filter the main component obtained in scan code

obtained after the operation, press and release the key. At the same time generate a signalto a controller can recognize what is key expansion (usually for the purpose of movement

of the slider, select level players) what are often key (used to store players named in the

case of high results, pause or start the game)

There are two ways to record the main component in the scan code from the press release

the key operation is started and start make code break code. In pong game that made the

group has chosen to start group will make code more accurately because the command

will be executed immediately after being imported to avoid delay to the key if we are

using to catch break code.

Block diagram of the circuit with a PS2 keyboard interface:

PS2_rx

ps2c

ps2d

ps2c

ps2d

clk

FSM to

get make

code

dout

done_tick

FIFO

wr

w_data r_data

rdgot_tick

Key_code

got_key

Figure 5.7


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Spotlight in this circuit is the signal got_key. After the circuit receives data sent from the

PS2 keyboard and output is a signal dout is done_tick signal. Output signal will be sent to

an FSM circuit to determine the main components of the code that we need to collect to

serve our purposes. Got_tick positive signal high when the circuit will determine the

composition of FSM code to read, and write into the code for this in the Control Unit Fifo

waiting for treatment.

Chart FSM to start make code:

waitgot_key = 0

Check key

done_tick = 1

done_tick = 0

got_key = 0

loop

brk_key = 1

brk_flag = 1

Check flaggot_key = 0

brk_key = 0

Clear flag

brk_flag = 1

Read key

brk_flag = 0

brk_flag = 0

got_key = 1

ext_key = 1

Figure 5.8

FSM is designed to break code scan code instead of all keys pressed including extended

keys. The advantage is that can get the right key when a key is pressed but the change is

more complex circuits. This reading is E0 FSM will skip this code; Upon receiving F0 F0


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will ignore and bypass the code and immediately following its receipt. Thus, complete

the task FSM received scan code.

FSM do the job as follows:

- At first signal and brk_flag got_key by 0.- When you receive a code from the receiver, it will have to check the extended

code E0 or not, if it will ignore (got_key get this value => we get scan code

- E0 next skip.- F0 next brk_flag flags ignored and set to 1.- The value of the last 75, the flag brk_flag check for a value => ignore and delete

this flag to 0.


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6 VGA6.1 Graphics6.1.1 Introduction

- VGA stands for "video graphics array", is a graphics standard introduced in late1980 from the same type computer IBM PS / 2. In the following sections, we will discuss

the interface 640 x 480 resolution with 8 basic colors of the screen CRT (cathode ray

tube).

- Below is a combination of color from the 3-bit VGA:red (R) Green (G) Blue (B) Color

0 0 0 black

0 0 1 Blue

0 1 0 Green

0 1 1 Cyan

1 0 0 red

1 0 1 Magenta

1 1 0 Gold

1 1 1 White

6.1.2 VGA Port- VGA port has five positive signals include sync signal horizontally and vertically,

and v_sync h_sync and 3 for the third picture signal red, green, blue.

- The picture is an analog signal, and video controller using a DAC converter toconvert the digital signal level analog audio output desired. If a picture signal N-bit test

signal may be converted to a similar level 2N.

- In the discussion, we use color picture signal output 3bit so we'll get 2 ^ 3 = 8basic colors as listed in the table .6.2 Video controllers- A controller that creates the image sync signal and the output pixel data.Chart as follows:


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VGA_sync

Pixel generation

circuit

h_sync

v_sync

video_on

pixel_x

pixel_y

External

data/controlrgb

VGA

monitor

clock

Figure 6.1: Block diagram of the VGA controller

- Chart include: Synchronization circuit, denoted VGA_sync. Create pixel circuit "Pixel circuit generation."

- Circuit VGA_sync creates synchronization signal and time signal.Signal h_syncand v_sync VGA port is connected to control the horizontal scanning mode and the

vertical of controllers.Pixel_x and pixel_y is the output of the decoded signal from the

buffer inside. The two signals to determine the location of the current pixel.

VGA_synccung circuit generates a signal to determine video_on when do activate or

disable signal displayed on the screen.

- Circuit 3 pixel generation circuit generates picture signal rgb. Samples werecorresponding to the coordinates of the current pixel and the signal data and external

controls.

- Circuit VGA synchronization- This circuit generates the synchronization signal h_sync horizontal and vertical

synchronization v_sync. Of which:

h_sync: indicate the time required for scanning a row. v_sync: indicate the time required for scanning the entire screen.

-

In the discussion we use the screen resolution is 640x480 pixels with a speed of25MHz, which means that the process 1s 25M pixel screen.

- Monitor the area include black members in the area around the screen and see therectangle in the middle. The coordinate axes and the positive direction of the axis as

shown below:


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borderVisible area

x

y

O

h_video_on

h_sync

0 639 655 751 799

Left

border

display

Right

border

retrace

Left

border

Figure 6.2: Diagram of horizontal scan time

6.2.1.1Sync signal horizontallyDiagrams-time scanning sync signal horizontally as shown 2. A signature h_sync signal

is divided into four areas:

Display area: is where the pixel is displayed on the screen. Area scan backwards: is where the electron beam volte-face towards the left

side.

Area boundary must:is the black area on the right, in the region this picturemessaging is disabled is not displayed.

The sea son: the black area is the same as the left and right border regions,in the region this competition the picture signal of breath is not displayed.


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6.2.1.2sync signal in the vertical- Map-time scanning sync signal vertically as follows:

v_video_on

v_sync0

479 489 491524

Top

border

display

Bottom

border

retrace

Top

border

Figure 6.3: Diagrams of the time signal scanned vertically.

- In which: Display area: is where the pixel is displayed on the screen. Area scan backwards: is where the electron beam volte-face towards the left

side.

Border area on: is the black area above, in this region the picture messagingis disabled is not displayed.

border below: black area is the same as the area below and above the

boundary, in the region this competition the picture signal of breath is not displayed.

6.2.1.3Speed pixel- Call p is the number of pixels in a horizontal row, l be positive in a horizontal

screen and s is the number of displays in the 1 s test speed by pixel p * l * s.

- Note: order to be not blinking screen test s must be greater than or equal to 24.- With a screen resolution 640x480 and displays the number of 1s is 60 images / s

test p = 800 pixels / line, l = 525 line / screen, s = 60 screens / second tape speed

800x525x60 pix 25M pix / s.

6.2.2 Create pixel circuit- Circuit generates a signal to create pixel color 3 - bit rgb to VGA port. Control

signals and data indicate that external content to be displayed on the screen, and pixel_y

pixel_x indicate your current pixel coordinates. There three types of pixel circuits

created:


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Map type bit - mapped. Map style tile - mapped. Map object model - mapped.

- In the chart type bit - mapped, data displayed on the screen is stored in a memorycell. Each pixel is stored directly in memory that forms words memory (memory word)

and signal pixel_x, pixel_y create memory cell address. A micro processor constantly

updated graphical screen and write data to memory cells. A receiver for continuous readfrom the memory and transfers data to RGB. Chart bit - mapped commonly used to create

color. Disadvantage when using this diagram is a waste of space.

- To reduce memory requirements, people use chart style tile - mapped. In thediagram this model, we group a set of bits to form a tile (square tiles) and to treat each

tile as a bit. Chart is usually used to create text.

- Finally, the object model diagram - mapped is often used to create the objects. Inthe preserve, we trade on a combination of three ways to generate a complete screen.

6.2.2.1Diagrams object model - mapped.- Block diagram:

Object 1

Generation circuit

Object 2

Generation circuit

Object 3

Generation circuit

rgb

mux

Data/control

Video_on

pixel_x

pixel_yrgb

Figure 6.4: Block diagram of the circuit object - mapped.


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- Block diagram including circuit creates the objects, a mux to select the objectsdisplayed. Circuits perform the following functions:

Hold down the coordinates of the object coordinates and comparing thiswith the current position and that pixel_x pixel_y provided.

Hold down the coordinates of the object coordinates and comparing thiswith the current position and that pixel_x pixel_y provided.

Only the color of the object signal.- Set mux check the signal on and identify information would be transmitted to the

output signal rgb.

6.2.2.2Diagrams style bit - mappedIn this type of diagram, each pixel memory cells should constitute a drawback of this

method is very religious memory. This approach does not require additional circuitry to

switch the signal pixel_ x and pixel_y memory locations but much wasted memory.

6.2.2.3Diagrams style tile - mapped- Diagrams for this model is used to create text and will be discussed in Section 2.

6.3 VGA text6.3.1 Introduction

- Diagrams style tile - mapped is used to create text and other characters. Each tile isconsidered as a super-pixel. Method build the characters are generally regarded as the tile

and create a pixel circuit design using this method.

6.3.2 Create text- When applying this method, each character is treated as a tile, the value of a ma

tilebieu performances of a particular sample. We use the ASCII code 7 - bit characters.

- Form of the tiles that make up your text font character sets. There are many kindsof fonts, but in the capacity of our discuss fontchu in size 8x16 (8 columns and 16

rows).


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00000000

00000000

00010000

00111000

01101100

11000110

11000110

11111110

11000110

11000110

11000110

11000110

00000000

00000000

00000000

00000000

Figure 6.5: Model of characters and font characters

- Other characters include numbers, letters and flowers business letters, symbols,and many special graphics characters.

- For screen resolution 640 x480, when using tile in size 8 x16, each horizontal rowand each tile 80 is not just hang vertically just not enough 30 tile. Meanwhile we can see

the screen resolution is 80 x 30.

6.3.3 Font ROM- To make that ASCII characters, we use font ROM. Suppose we made 128 first

character of the ASCII table is the size of 211 x 8 ROM. Among them, 7 the

highest weighted bit of 11 bit address used to identify characters, four weighted

smallest bit is used to identify the row in a form of words. Figure 5 is a ROM

address and content of the letter A.

- How do the following:constant ADDR_WIDTH: integer :=ll;constant DATA_WIDTH: integer:=8;

signal addr_reg: std_logic_vector (ADDR_WIDTH -1 downto 0);

type rom_type is array (0 to 2**ADDR_WIDTH-l)

-- ROM definition

constant RUM: rom_type :=


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-- code x00 (blank space)

00000000, -- 0

00000000, -- 1

00000000, -- 2

00000000, -- 3

00000000, -- 400000000, -- 5

00000000, -- 6

00000000, -- 7

00000000, -- 8

00000000, -- 9

00000000, -- a

00000000, -- b

00000000, -- c

00000000, -- d

00000000, -- e

00000000, -- f

...

begin

-- addr register to infer block RAM

process (clk)begin

if (clkevent and clk = 1) then addr-reg


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- Under this method, the screen is considered as a resolution of 80x30 tiles, each tileis a box the size of 8x16. First, pixel_x and pixel_y will indicate the location coordinates

of the current tile.The circuit used to create character coordinates in conjunction with the

data signal / control from the outside to create the value of tlie corresponding ASCII

code. Next, this will make ASCII 7 bits of the address of the font ROM and the location

of the sample in question. Combined with the lower 4 bits of the y coordinates to form

the full address of the font ROM. The output of the ROM font corresponding to a row ofan 8 bit samples, and the third bit is the smallest weight of x coordinates indicate the

position of the pixel.

6.3.5 The rate of Font- Trong s iu ti mpp hng t th iu hnh h th

pix. Chng hn, hng t th m rng t font h th 8x16 n font hth 16x32. th hin ng vi ny, hng t h n h phi t

pix 1 it v i it trng s nh nht pixx v pixy.

7 Cc bc xy dng gameS FSM ca game:


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Start

Play

Game over

Enter name

Enter = 1

Enter = 0

Fail = 1

Bigger = 1

Fail = 0

Bigger =0

Enter = 1

Reset

Hnh 7.1. FSM ca game

S ASM ca game:


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Level


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SNAKE GAME

Difficulty:

Level 1

Level 2

Level 3

Level 4

Level 5

Hnh 7.3 Start screen

Box mu trng hin thv ng c chn hin ti. Dng phm mi tn n xung trn

n phm di chuyn v tr ca box.

V thit k, c th chia m hnh new game lm 2 phn nh 2 yr: yr nn cha

background mu xanh v box mu trng , top layer cha text.

Background &

Select_box

Start text

0

1s

RGB

RGB

Text_on

Start_RGB

1-5 counterena

key

Hnh 7.4 S khi mn hnh new game


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7.1.1 Layer nnCha nn xanh v select_box mu trng:

SNAKE GAME

Difficulty:

Level 1

Level 2

Level 3

Level 4

Level 5

Hnh 7.5 Start screen - background

Box mu trng c hin thnh i tng hnh ch nht, v tr ca n l mt

trong 5 v trc nh trc tng ng vi 5 v tr ca cc level. N xut hin u

ty thuc vo m v ngi hi mun chn. x iu ny, ta s dng mt bin

position x nh t ca select_box. Khi ngi hi nhnphm mi tn n hoc

xung sm tng hoc gim gi tr ca bin position ny dn n thy i v tr ca

select_box. Bin position ny ng c s dng cho phn hi hnh nh thm su

vo x nh t di chuyn ca ch rn.


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Position = 1

Position = 1

Position = 2

Position = 3

Position = 4

Position = 5

Hnh 7.6 Ta box thay i theo bin Position

T nh ca select_box s ph thuc vo gi tr ca bin level ny.

Phn vic tip theo l cho hin th select_box mu trng ny ln trn nn mu xnh nh

mt i tng hnh ch nht thng thng.

7.1.2 Text layerLayer cha text ca mn hnh new game s c dng:


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SNAKE GAME

Difficulty:

Level 1

Level 2

Level 3

Level 4

Level 5

Hnh 7.7 Start screen - text layer

Vic xy dng layer text ny khng c g phc tp, hon ton da trn kin thc v vic

hin th text ln mn hnh VGA. Ch t ca cc m v so ho ng vi cc v

tr tng ng ca select_box.

7.2 Xy dng mn chi chnhMn hnh hi hnh ng:


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SCORE: 13SPEED: 3

Hnh 7.8 Mn hnh chi chnh

N bao gm cc phn chnh:

-

Text hin th level hin ti c tr hi v m im t c c ngi hi.- Header mu trng l khu vc hin th text.- B tng gia mn hnh.- Rn.- Mi.


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Key board

Snake_Game

graph

Step_tick

move

Snake_size

Snake_posit

Ball_posit

Ball_feed

Snake_fail

RGB

Speed_counter

Snake drive

randomread

=Score_tickSnake

counterena

Score

counterena

Level & score

text

score

level

RGB

0

1

Play_R

Text on

ena

Postion

Postion

Hnh 7.9 S khi mn chi chnh

7.2.1 TextVic hin thtxt v t lm top-yr bit phn trc. y hng t si vo vic

m so hin th level v score c ngi hi.

Level & score

text

RGB

Text on

score

level

Hnh 7.10S khi hin thtext mn chi chnh


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SCORE: 13SPEED: 3

Hnh 7.11 Layer text ca phn chi chnh

im c ngi hi u tho iu d liu inry 14 it. hin thim s ny,

trc tin ta chuyn v dng BCD 16 bit thng qua b chuyn i BIN_2_BCD. C 4 bit

ca tn hiu CD ny tng ng vi 1 ch s c im s:

Bin2BCD16bit BCD14bit Binary

00001000110010

0000010101110010

572

2750

Binary

BCD

Hnh 7.12


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a ch ca mt ch s trong ROM bng gi tr ca ch s ng thm 48. T vic

hin thc thc hin nh thng.

Hon ton tng ti vi vic hin th level.

7.2.2 HeaderVng header mu trng c to ra bng cch s dng thut to r i tng hnh ch

nht thng thng.

7.2.3 Bc tng to ra b tng ho vn t n s dng ROM to i tng khng phi

hnh ch nht.

Su hi n nhng v tr mun hin th b tng, ta ch vic cho hin bng cch load

ROM c tng.

1 1 1 1 0

1 1 1 0 1

1 1 0 1 1

1 0 1 1 10 0 1 1 1 1

0

0

0

0

1 1 1 1 0

1 1 1 0 1

1 1 0 1 1

1 0 1 1 1

0 0 1 1 1 1

0

0

0

0

1 1 1 1 0

1 1 1 0 1

1 1 0 1 1

1 0 1 1 1

0 0 1 1 1 1

0

0

0

0

Tng

Hnh 7.13 ROM tng


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7.2.4 Bng miVic hin th bng hon ton ging vi vic hin th b tng. Sau mi ln rn n c

bng mi s cn bng mi mi xut hin v xut hin mt v tr ngu nhin. to ra

t ngu nhin ny, ta s dng 2 bm vi cc gi tr ln nht ng vi 2 t lnnht ca 2 chiu mn hnh. 2 bm ny sm quay vng lin tc. Khi rn n mi s

sinh ra mt tn hiu yu cu sinh bng mi. Khi t s ly 2 gi tr ca 2 bm lm

t cho bng mi mi sinh ra. 2 gi tr ny ph thuc vo thi gian gia cc ln n

mi lin tip ca rn. V v khong thi gian ny l ngu nhin nn 2 gi tr t ny

ng ngu nhin.

Snake drive

randomread

=Score_tick

ena

Ball feed

0 1 2 3 N-1 0 1

0 1 2 3 M-2 M-1 0

Ball_X

Ball_Y

Read

Hnh 7.14 B sinh ta ngu nhin

Nu nh ng mi mi sinh ra c t nm trong phn thn ng c hin th ca rn

th mt qu bng mi s phi sinh r thay th.


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HeadBall

New ball

Hnh 7.15 Bng nm trong thn rn

trnh vic qu bng mi sinh nm trong b tng, ta chn to ca bng ngay t

trong bm sinh t ngu nhin cho bng.

7.2.5 RnVic hin th tng t ca rn ng hon ton ging vi m vi b tng, load ROM

cho tng t mt. C iu ch rn c chiu i thy i.

Chiu di ca ch rn xm nh mt tham su vo t b tnh chiu di rn m

ta s xt sau ny. Ch rn oi nh mt mng nhiu phn t, mi phn tng vi

mt t ca rn. Trong mi phn t c cha t nh v t tri ca mi t tng

ng ca rn. Ch nhng t no c ch s nhhn hiu di rn mi c hin th:


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u 1 2 L-1 L N

L: Chiu i rn

N: Chiu i rn ti rn

hin th Khng hin th

Hnh 7.16 Hin th rn

Ta cn mt mng mt chiu c chiu i tng ng cha tn hiu cho bit t tng

ng c c bt hay khng:

u 1 2 L-1 LN

hin th Khng hin th

1 1 1 1 0 00Snak_on

Hnh 7.17 Hin th rn

Khi khi VGA qut mn hnh theo pixel_x v pixel_y, ta s kim tra xem t hin ti

c thu t rn no khng. Gi s t ng qut nm trong mt t rn no , t s

kim tra tn hiu snon tng ng. Nu n bng 1 ta s load ROM v hin tht rn

, ngc li th khng cho hin tht rn .

Ty thuc vo ROM c t rn m pix c hin th hay khng. Nu gi tr

ROM tng ng 1 th pix sc gn gi tr RGB ca ch rn. Nu 0 th

pix mng mu nn. Do , ti mi t rn ta cn mt tn hiu x nh pixel hin

ti c bt hay khng. => Ta cn mt mng 1 chiu c cng chiu di vi ch rn

cha tn hiu bt pixel cho c ch rn:


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1 1 0

1 1 1

1 1 1

Pixel_x

Pixel_y

t th i

Sna_on(i) =1'

Pixel_x

Pixel_y

Sna_on(i) =0'

Hnh 7.18 ROM v bt tng pixel cho t rn

Nh hnh trn, t c khi no c tn hiu Sna_on thi no ng 1 th s xut ra gi

tr RGB ca ch rn. m iu ny, ta or tt c cc bit ca tn hiu sna_on li vi nhau

to ra tn hiu snake_on. => bt c khi no snake_on bng 1 th ho xut gi tr RGB

ca ch rn ra cng VGA:

Sna_on 0 Sna_on 1 Sna_on 2 Sna_on 3 Sna_on n-3

Snake_on OR OR OR OR

Sna_on n-2 Sna_on n-1

OR OR

Hnh 7.19

iu khin rn di chuyn:


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Mt h h n gin iu khin rn di chuyn t h vi iu khin u ca

rn. Tt c t rn cn li s tng i tho u rn bng cch gn t nh v tri

c t ng tr ho t ng sau:

Left0

Top0 Top1 Top2 Top3 Top4 Top5

Left1 Left2 Left3 Left4 Left5

Head

Hnh 7.20 Di chuyn rn

Ta s dng mt tn hiu (step_tick)thng o hi no th ch t ca

t. mi khi tn hiu step_tick 1th t c u rn v t li c

cp nht . Do , hu a n cng cao th t di chuyn ca rn cng thp. iu

chnh t di chuyn ca rn, ta dng mt bountr sinh ra tn hiu

step_tick. Gi tr cao nht ca bm ph thuc vo level c ngi hi. Lv

cng cao th gi tr cao nht ca bm cng thp => chu k ca tn hiu step_tick

cng thp => rn di chuyn cng nhanh:

Counter

clk

level Step_tick

clk

Step_tick

Hnh 7.21 B sinh tn hiu di chuyn

iu khin u rn:


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Snake driveena

Co-ordinate of snake_head

Hnh 7.22 Khi iu khin u rn

u rn iu khin bi 4 phm mi tn trn n phm. Khi nhn c tn hiu i

hng tn phm u rn s di chuyn theo chiu m mi tn h. trnh tnh

trng nhn vophm mi tn hngc li vi hng di chuyn ca rn dn n u ca

ch rn chui vo thn ca n ta cn mt bin cha chiu ng i huyn ca ch rn

x l nhn phm bm. Do rn 4 hng di chuyn trn mn hnh nn ta dng mt bin

nh phn 2 bit m ha chiu di chuyn ca rn:

direc di chuyn t tri sang phi.

direc di chuyn t phi sang tri.

direc di chuyn t trn xung i.

direc di chuyn ti ln trn.


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01 00

10

11

Hnh 7.23 Hng trn mn hnh

Khi nhn mt phm bm t bn phm- v d l "01110100" ( phm di chuyn sang phi)-

ta s kim tra phm g. Trong trng hp ny t phm mi tn sng phi. Tip

theo kim tr hng ng i huyn ca rn l chiu no. Nu 01 phi sang tri

ngc chiu mi tn th shng ho php u ca rn di chuyn sang phi m tip tc

di chuyn sang tri.

Hng ng i huyn

Hng hng th i

Hng th r

Hnh 7.24 iu hng u rn

Khi iu khin u rn:


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7.3 Khi no kt thc tr chi?Tr hi t th hi m u ca rn m vo tng ho m vo hnh phn thn ca

chnh n.

Vi x nh rn m u v tng c thc hin n gin bng cch kim tra xem ta

u ca rn c nm trong vng ca b tng hay khng.

Vic kim tra xem con rn c tn hnh n hy hngngc thc hin tng t

bng cch kim tra t u rn c trng vi t c t c bt ca con rn

hay khng.

Hnh 7.25 u rn nm trong thn

Do vic kim tra rn m vo tng v tm hnh n c thc hin ring r, sinh ra

hai tn hiu ring r nn s cn kt hp li bng php or.

7.4 Xy dng phn kt thc tr chi7.4.1 Mn hnh tnh imSau khi rn m vo tng hoc tm vo hnh n, tr hi t thc v s hin ra mn

hnh tnh im:


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SCORE: 120

Top 5:

Player1: 560

Player2: 440

Player3: 360

Player4: 210

Player5: 100

Hnh 7.26 Mn hnh tnh im tr chi

Trn mn hnh s hin th sim c ngi hi hin ti. ng thi hin thtn v im

stng ng c 5 ngi c sim cao nht tr . im v tn c 5 ngi c

u trong 1 mng 5 phn t:

Score sreen

score

Name

array

Score

array

RGB

Hnh 7.27 Khi hin thim ngi chi


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Vic hin thtxt, im s ging nh phn hin thim v v trong mn hi hnh.

7.4.2 Mn lu im v tn ngi chiMn hnh tn im ch hin th trong 3s. Sau 3s, nu im s c ngi hi hin ti cao

hn ngi im s thp nht trong top5 th tn v im s ca ngi hi hin ti s

c u i vo trong top5, hn hnh u tn sc hin th:

ENTER YOUR NAME:

LONG_

Hnh 7.28 mn hnh lu tn

Mn hnh gm 2 phn : layer text v background cha text_box mu trng. Vn hin

th ging cc phn n tr y v h n gin.

Ta xt vn nhp tn t bn phm v x u trtn ng im s vo mng.

u tn ngi hi c nhp t bn phm ta s dng mng 7 phn t, mi phnt 1 a ch ca 1 ch ci trong font_ROM. Mi hi 1 phm c nhn, scan code

c phm c chuyn ln host v chuyn thnh m SCII tng ng thng qua b

chuyn i SCAN2ASCII.


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Group 5-K52 Page 45

Key board

2 ASCII

Hnh 7.29 Chuyn Scan code sang m ASCII

T, m SCII u vo trong mng. Khi hin th ch vi c gi tra ch ROM t

trong mng v load k ttng ng.

Khi nhn c phm backspace, mch s xa phn ttr v gi tr0 ( a ch ca

khong trng trong ROM). Khi nhn phm enter, mng cha tn sc chn vo trong

mng 2 chiu cha tn c 5 ngi hi im s cao nht.


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Group 5-K52 Page 46

Player 1: 500

Player 2: 400

Player 3: 300

Player4:200

Player 5: 100

Present player: 250

Hnh 7.30 Lu im sngi chi

8 Kt lunSau mt thng h lm vi, hng ti hon thnh sn gm trn it DE1. Thng qu

ti hng ti hc hi thm rt nhiu thut trong lp trnh VHDL ng nh nhng

kinh nghim qu bu trong vic pht trin ng dng trn FPGA. M gm hon

thnh nhng vn cn rt nhiu vic phi m hon thin gm nh hin thnh dng

SDRAM, audio cho game. Hy vng su ti ny, nhm i su s tip tc pht trin

game hon thin hn na.

9 Cc ti liu tham kho- FPGA Prototyping VHDL Examples - Xilinx Spartan-3 version . PONG P.CHU


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