copyright 2001, agrawal & bushnelllecture 3b: testability analysis1 vlsi testing lecture 3b:...
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Copyright 2001, Agrawal & Bushnell Lecture 3b: Testability Analysis 1
VLSI Testing
Lecture 3b: Testability Analysis
VLSI Testing
Lecture 3b: Testability Analysis
Definition Controllability and observability SCOAP measures
Combinational circuits Sequential circuits
Summary
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What are Testability Measures?
What are Testability Measures?
Approximate measures of: Difficulty of setting internal circuit lines to 0 or 1
from primary inputs. Difficulty of observing internal circuit lines at
primary outputs. Applications:
Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware.
Guidance for algorithms computing test patterns – avoid using hard-to-control lines.
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Testability AnalysisTestability Analysis
Determines testability measures Involves Circuit Topological analysis, but no test vectors (static analysis) and no search algorithm. Linear computational complexity
Otherwise, is pointless – might as well use automatic test-pattern generation and calculate:
Exact fault coverage Exact test vectors
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SCOAP MeasuresSCOAP Measures SCOAP – Sandia Controllability and Observability Analysis
Program Combinational measures:
CC0 – Difficulty of setting circuit line to logic 0 CC1 – Difficulty of setting circuit line to logic 1 CO – Difficulty of observing a circuit line
Sequential measures – analogous: SC0 SC1 SO
Ref.: L. H. Goldstein, “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. CAS, vol. CAS-26, no. 9. pp. 685 – 693, Sep. 1979.
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Range of SCOAP MeasuresRange of SCOAP Measures
Controllabilities – 1 (easiest) to infinity (hardest) Observabilities – 0 (easiest) to infinity (hardest) Combinational measures:
Roughly proportional to number of circuit lines that must be set to control or observe given line.
Sequential measures: Roughly proportional to number of times flip-flops
must be clocked to control or observe given line.
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Combinational ControllabilityCombinational Controllability
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Controllability Formulas
(Continued)
Controllability Formulas
(Continued)
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Combinational ObservabilityCombinational ObservabilityTo observe a gate input: Observe output and make other input
values non-controlling.
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Observability Formulas(Continued)
Observability Formulas(Continued)
Fanout stem: Observe through branch with best observability.
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Comb. ControllabilityComb. ControllabilityCircled numbers give level number. (CC0, CC1)
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Copyright 2001, Agrawal & Bushnell Lecture 3b: Testability Analysis 11
Controllability Through Level 2
Controllability Through Level 2
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Final Combinational Controllability
Final Combinational Controllability
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Combinational Observability for Level
1
Combinational Observability for Level
1Number in square box is level from primary outputs (POs).
(CC0, CC1) CO
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Combinational Observabilities for Level 2
Combinational Observabilities for Level 2
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Final Combinational Observabilities
Final Combinational Observabilities
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Sequential Measures (Comparison)
Sequential Measures (Comparison)
Combinational
Increment CC0, CC1, CO whenever you pass through
a gate, either forward or backward.
Sequential
Increment SC0, SC1, SO only when you pass through
a flip-flop, either forward or backward.
Both
Must iterate on feedback loops until controllabilities
stabilize.
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Copyright 2001, Agrawal & Bushnell Lecture 3b: Testability Analysis 17
D Flip-Flop EquationsD Flip-Flop Equations Assume a synchronous RESET line. CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0
(RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0
(RESET) + 1 CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C),
CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0
(RESET) SO (D) is analogous
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D Flip-Flop Clock and ResetD Flip-Flop Clock and Reset CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C) SO (RESET) is analogous Three ways to observe the clock line:
1. Set Q to 1 and clock in a 0 from D2. Set the flip-flop and then reset it3. Reset the flip-flop and clock in a 1 from D
CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C), CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)] SO (C) is analogous
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Testability ComputationTestability Computation1. For all PIs, CC0 = CC1 = 1 and SC0 = SC1 = 0
2. For all other nodes, CC0 = CC1 = SC0 = SC1 = ∞3. Go from PIs to POs, using CC and SC equations to get
controllabilities -- Iterate on loops until SC stabilizes -- convergence is guaranteed.
4. Set CO = SO = 0 for POs, ∞ for all other lines.
5. Work from POs to PIs, Use CO, SO, and controllabilities to get observabilities.
6. Fanout stem (CO, SO) = min branch (CO, SO)
7. If a CC or SC (CO or SO) is ∞ , that node is uncontrollable (unobservable).
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Sequential Example Initialization
Sequential Example Initialization
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After 1 IterationAfter 1 Iteration
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After 2 IterationsAfter 2 Iterations
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After 3 IterationsAfter 3 Iterations
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Stable Sequential Measures
Stable Sequential Measures
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Final Sequential Observabilities
Final Sequential Observabilities
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SummarySummary
Testability measures are approximate measures of: Difficulty of setting circuit lines to 0 or 1 Difficulty of observing internal circuit lines
Applications: Analysis of difficulty of testing internal circuit parts
Redesign circuit hardware or add special test hardware where measures show poor controllability or observability.
Guidance for algorithms computing test patterns – avoid using hard-to-control lines