copyright agrawal, 2009elec5270-001/6270-001 spr 09, lecture 61 elec 5270/6270 spring 2009 low-power...

Copyright Agrawal, 2009Copyright Agrawal, 2009 ELEC5270-001/6270-001 Spr 09, Lecture 6ELEC5270-001/6270-001 Spr 09, Lecture 6 11

ELEC 5270/6270 Spring 2009ELEC 5270/6270 Spring 2009Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

Power Analysis and Process VariationPower Analysis and Process Variation

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html

Process Variation in Nanoscale DevicesProcess Variation in Nanoscale Devices Nanoscale device have dimensions smaller than 100 Nanoscale device have dimensions smaller than 100

nm, typically, 65nm, 45nm, 32nm, 22nm, etc.nm, typically, 65nm, 45nm, 32nm, 22nm, etc. As geometries become closer to molecular dimensions, As geometries become closer to molecular dimensions,

percentage random variation in parameters become percentage random variation in parameters become large.large.

Affected physical parameters: transistor width (W) and Affected physical parameters: transistor width (W) and length (L), interconnect width and spacing, doping level.length (L), interconnect width and spacing, doping level.

Affected electrical characteristics: on and off resistances Affected electrical characteristics: on and off resistances of transistors, threshold voltage and leakage current, of transistors, threshold voltage and leakage current, capacitances.capacitances.

Major influence on gate delays, Major influence on gate delays, ±20%, or more.±20%, or more.


Dynamic Power and Process VariationDynamic Power and Process Variation

Dynamic power increases with glitch Dynamic power increases with glitch transitions, which are functions of gate transitions, which are functions of gate delays.delays.

Process variation can influence delays in a Process variation can influence delays in a circuit, especially in nanoscale technologies.circuit, especially in nanoscale technologies.

Monte Carlo simulation used to address the Monte Carlo simulation used to address the variation is time consuming and expensive.variation is time consuming and expensive.

Bounded delay models are usually Bounded delay models are usually considered to address process variations in considered to address process variations in logic level simulation and timing analysis.logic level simulation and timing analysis.


ReferencesReferences Simulation:Simulation:

S. Chakraborty and D. L. Dill, “More Accurate Polynomial-Time Min-S. Chakraborty and D. L. Dill, “More Accurate Polynomial-Time Min-Max Timing Simulation,” Max Timing Simulation,” Proc. 3Proc. 3rdrd International Symp. Advanced International Symp. Advanced Research in Asynchronous Cir. and Syst.Research in Asynchronous Cir. and Syst., Apr. 1997, pp. 112-123., Apr. 1997, pp. 112-123.

J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, “System Simulation With MIDAS,” “System Simulation With MIDAS,” AT&T Tech. JAT&T Tech. J., vol. 70, no. 1, pp. ., vol. 70, no. 1, pp. 36–51, Jan. 1991.36–51, Jan. 1991.

S. Bose, H. Grimes, and V. D. Agrawal, “Delay Fault Simulation With S. Bose, H. Grimes, and V. D. Agrawal, “Delay Fault Simulation With Bounded Gate Delay Model,” Bounded Gate Delay Model,” Proc. International Test ConfProc. International Test Conf., 2007, pp. ., 2007, pp. 23–28.23–28.

Timing anlysis:Timing anlysis: S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-Max Timing Analysis S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-Max Timing Analysis

and an Application to Asynchronous Circuits,” and an Application to Asynchronous Circuits,” Proc. IEEE, Proc. IEEE, vol. 87, no. vol. 87, no. 2, pp. 332–346, Feb. 1999.2, pp. 332–346, Feb. 1999.

Delay fault testing:Delay fault testing: H. Grimes, H. Grimes, Reconvergent Fanout Analysis of Bounded Gate Delay Reconvergent Fanout Analysis of Bounded Gate Delay

FaultsFaults, Master’s thesis, Auburn University, Dept. of ECE, Aug. 2008. , Master’s thesis, Auburn University, Dept. of ECE, Aug. 2008. Copyright Agrawal, 2009Copyright Agrawal, 2009 ELEC5270-001/6270-001 Spr 09, Lecture 6ELEC5270-001/6270-001 Spr 09, Lecture 6 44

Problem StatementProblem Statement

Given a set of vectors (random or Given a set of vectors (random or functional), determine the range of functional), determine the range of dynamic power consumption for dynamic power consumption for specified bounds on delay variation.specified bounds on delay variation.


Power Analysis MethodsPower Analysis MethodsMonte Carlo simulation:Monte Carlo simulation:

R. Burch, F. Najm, P. Yang, and T. Trick, R. Burch, F. Najm, P. Yang, and T. Trick, “McPOWER: A Monte Carlo Approach to Power “McPOWER: A Monte Carlo Approach to Power Estimation,” Estimation,” Proc. IEEE/ACM International Proc. IEEE/ACM International Conference on Computer-Aided DesignConference on Computer-Aided Design, pp. 90–, pp. 90–97, Nov 1992.97, Nov 1992.

Bounded-delay analysis:Bounded-delay analysis:J. D. Alexander, J. D. Alexander, Simulation Based Power Simulation Based Power

Estimation for Digital CMOS TechnologiesEstimation for Digital CMOS Technologies, , Master’s thesis, Auburn University, Dept. of ECE, Master’s thesis, Auburn University, Dept. of ECE, Dec. 2008.Dec. 2008.


C880: Monte Carlo SimulationC880: Monte Carlo Simulation


Min Power (mW)

Max Power (mW)

CPU Time (secs)

1.42 11.59 262.7

0

10000

20000

30000

40000

50000

60000

70000

80000

Power (mW)

Fre

qu

en

cy

1000 Random Vectors, 1000 Sample Circuits± 20% random delay variation

Bounded Delay ModelBounded Delay Model

Model delay uncertainties by assigning Model delay uncertainties by assigning each gate a lower and an upper bound on each gate a lower and an upper bound on delay, also known as delay, also known as min-max min-max delay.delay.

The bounds can be obtained by adding The bounds can be obtained by adding specified process-related variation to the specified process-related variation to the nominal gate delay for the technology.nominal gate delay for the technology.

In this model, intervals of signal In this model, intervals of signal uncertainties are defined at the output of uncertainties are defined at the output of each gate.each gate.


Ambiguity Delay IntervalsAmbiguity Delay Intervals


• EA is the earliest arrival time• LS is the latest stabilization time• IV is the initial signal value• FV is the final signal value

IV FV

LSEA

IV FV

EA LS

mindel, maxdel

EAdv LSdv

EAsv=-∞ LSsv=∞

EAsv LSsv

EAdv=-∞ LSdv=∞

?

Sensitizing and Driving Values Sensitizing and Driving Values Relative to Gate a Signal Feeds IntoRelative to Gate a Signal Feeds Into


mindel, maxdel

EAdv LSdv

EAsv=-∞ LSsv=∞

EAsv LSsv

EAdv=-∞ LSdv=∞

?

Earliest possible terminationof sensitization value

Definite termination ofsensitization value

Sensitizingvalue (sv)

Driving value (dv)

Propagating Ambiguity Intervals Propagating Ambiguity Intervals through Gatesthrough Gates


The ambiguity interval (EA,LS) for a gate output is determined from the ambiguity intervals of input signals, their pre-transition and post-transition steady-state values, and the min-max gate delays.

(mindel, maxdel)

Summarize Input SignalsSummarize Input SignalsTo evaluate the output of a gate, we To evaluate the output of a gate, we

analyze inputs analyze inputs ii::


Use Inertial Delay of GateUse Inertial Delay of Gate

Ambiguity interval at gate output:Ambiguity interval at gate output:

where the inertial delay of the gate is where the inertial delay of the gate is bounded as (bounded as (mindelmindel, , maxdelmaxdel). ).


Finding Number of TransitionsFinding Number of Transitions


2

1,3

3 14

5 8 10 12

(mindel, maxdel)

7 10 12 14

5 17

EA LS

3 14

EA LS

[0,4]

[0,2] 6 17

EA LS

[mintran,maxtran]

where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

Estimating Estimating maxtranmaxtran Nd: First upper bound is the largest number of transitions Nd: First upper bound is the largest number of transitions

that can be accommodated in the ambiguity interval that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output given by the gate delay bounds and the (IV, FV) output values.values.

N: Second upper bound is the sum of the input N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further transitions as the output cannot exceed that. Further modify it as modify it as

N = N – k N = N – k

where k = 0, 1, or 2 for a 2-input gate and is determined where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs.by the ambiguity regions and (IV, FV) values of inputs.

The maximum number of transitions is lower of the two The maximum number of transitions is lower of the two upper bounds:upper bounds:

maxtran = maxtran = minmin (Nd, N) (Nd, N) Copyright Agrawal, 2009Copyright Agrawal, 2009 ELEC5270-001/6270-001 Spr 09, Lecture 6ELEC5270-001/6270-001 Spr 09, Lecture 6 1515

Effect of Gate Inertial DelayEffect of Gate Inertial Delay


D

W

D << W

D < W

D ≈ W

D > W

First Upper Bound, NdFirst Upper Bound, Nd

Nd = 1 + Nd = 1 + (LS – EA)/mindel (LS – EA)/mindel └└ ┘┘


1

mindel, maxdel

EA LS

mindel

Examples of Examples of maxtran maxtran ((k k = 0)= 0)


Nd = ∞

N = 8

maxtran=min (Nd, N) = 8

Nd = 6

N = 8

maxtran=min (Nd, N) = 6

Example: Example: maxtranmaxtran With Non-Zero With Non-Zero kk


EAsv = - ∞

EAdv

LSdv = ∞

LSsv

EAsv = - ∞ LSdv = ∞

EAdv LSsv

EA LS

[n1 = 6]

[n2 = 4]

[n1 + n2 – k = 8 ] ,

where k = 2

[ 6 ]

[ 4 ]

[ 6 + 4 – 2 = 8 ]

Estimating Estimating mintranmintran Ns: First lower bound is based on steady state values, IV Ns: First lower bound is based on steady state values, IV FV, FV,

If 0 If 0 0 or 1 0 or 11, then Ns = 0 1, then Ns = 0

If 0 If 0 1 or 11 or 1 0, then Ns = 1 0, then Ns = 1

In case of split ambiguity intervals, separate Ns is obtained for In case of split ambiguity intervals, separate Ns is obtained for

each interval and then all are added upeach interval and then all are added up

Ndet: Second lower bound is the minimum number of transitions Ndet: Second lower bound is the minimum number of transitions

permitted by the maximum inertial delay of the gate (maxdel).permitted by the maximum inertial delay of the gate (maxdel).

The minimum number of transitions is the higher of the two lower The minimum number of transitions is the higher of the two lower

bounds:bounds:

mintranmintran = = max max (Ns, Ndet) (Ns, Ndet)


Example: Example: mintranmintran

There will always be a hazard in the output There will always be a hazard in the output as long asas long as

(EA(EAsvsv – LS – LSdvdv) ) ≥≥ maxdelmaxdel Thus in this case the Thus in this case the mintran mintran is not 0 as per is not 0 as per

the steady state condition, but is 2.the steady state condition, but is 2.


d

EAsv = - ∞

EAdv LSsv = ∞

LSdv

EAdv = - ∞ LSdv = ∞EAsv LSsv

EA LS

(mindel, maxdel)

Multiple Ambiguity IntervalsMultiple Ambiguity Intervals• Multiple ambiguity intervals are waveform containing Multiple ambiguity intervals are waveform containing

intermittent regions of deterministic signal states.intermittent regions of deterministic signal states.

• We arrange the (EA, LS) values at the gate inputs in order We arrange the (EA, LS) values at the gate inputs in order

of their temporal occurrences.of their temporal occurrences.

• If an (LS) value occurs before an (EA) value, then multiple If an (LS) value occurs before an (EA) value, then multiple

ambiguity are separated by a deterministic value.ambiguity are separated by a deterministic value.

• We propagate the split ambiguity intervals to the output on We propagate the split ambiguity intervals to the output on

the condition that the deterministic interval is longer than the condition that the deterministic interval is longer than

the gate inertial delay.the gate inertial delay.


ExampleExample


d1,d2

EA1+ d1 LS3 + d2

d1,d2

EA1 LS1

EA2 LS2

EA3 LS3

EA1 LS1

EA2 LS2

EA3 LS3

EA1+ d1 EA3 + d1

LS3 + d2LS2 + d2

Without ordering input ambiguity intervals.

Ordering of input ambiguity intervals.

Simulation MethodologySimulation Methodology

maxdel, mindel maxdel, mindel = = nominal delay ± nominal delay ± ΔΔ%% Three linear-time passes for each input vector:Three linear-time passes for each input vector:

First pass: zero delay simulation to determine initial First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals.and final values, IV and FV, for all signals.

Second pass: determines earliest arrival (EA) and Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and latest stabilization (LS) from IV, FV values and bounded gate delaysbounded gate delays..

Third pass: determines upper and lower bounds, Third pass: determines upper and lower bounds, maxtranmaxtran and and mintran, mintran, for all gates from the above for all gates from the above information.information.


Effect of Gate Delay DistributionEffect of Gate Delay Distribution Experiment conducted to see if the distribution of Experiment conducted to see if the distribution of

gate delays has an effect on power distribution.gate delays has an effect on power distribution. For uniform distribution: Gate delays were For uniform distribution: Gate delays were

randomly sampled from uniform distribution [a, b], randomly sampled from uniform distribution [a, b], where a = nominal delay – where a = nominal delay – ΔΔ% and b = nominal % and b = nominal delay + delay + ΔΔ% This distribution has a variance % This distribution has a variance σσ22 = = (b – a)(b – a)22/12 = /12 = ΔΔ22(nom. delay)(nom. delay)22/30,000./30,000.

For normal distribution: Gate delays were For normal distribution: Gate delays were randomly sampled from a Gaussian density with randomly sampled from a Gaussian density with mean = nom. delay, and variance mean = nom. delay, and variance σσ22 as above. as above.


Monte Carlo ExperimentMonte Carlo Experiment


A standard gate node delay of 100 ps was A standard gate node delay of 100 ps was taken. A wire load delay model was followed taken. A wire load delay model was followed with each nominal gate delay being a function of with each nominal gate delay being a function of its fan-out.its fan-out.

The power distribution is for 1000 random The power distribution is for 1000 random vectors with a vector period of 10000 ps.vectors with a vector period of 10000 ps.

For each vector pair 1000 sample circuits were For each vector pair 1000 sample circuits were simulated. simulated.


Normal Distribution

Uniform Distribution

Experimental Result (Maximum Power)Experimental Result (Maximum Power) Monte Carlo Simulation vs. Min-Max analysis for circuit Monte Carlo Simulation vs. Min-Max analysis for circuit

C880. 100 sample circuits with C880. 100 sample circuits with ++ 20 % variation were 20 % variation were simulated for each vector pair (100 random vectors).simulated for each vector pair (100 random vectors).


R2 is coefficient of determination, equals 1.0 for ideal fit.

Result…(Minimum Power)Result…(Minimum Power)



Results…(Average Power)Results…(Average Power)

R2 = 0.9527

0

1

2

3

4

5

6

7

8

9

10

0 2 4 6 8 10

MIN - MAX mean power (mW)

Mo

nte

Car

lo a

vera

ge

po

wer

(m

W)


Copyright Agrawal, 2009Copyright Agrawal, 2009 3030ELEC5270-001/6270-001 Spr 09, Lecture 6ELEC5270-001/6270-001 Spr 09, Lecture 6

C880: Monte Carlo vs. Bounded C880: Monte Carlo vs. Bounded Delay AnalysisDelay Analysis


Monte Carlo Simulation Bounded Delay Analysis

Min Power (mW)

Max Power (mW)

CPU Time (secs)

Min Power (mW)

Max Power (mW)

CPU Time (secs)

1.42 11.59 262.7 1.35 11.89 0.3

0

10000

20000

30000

40000

50000

60000

70000

80000

Power (mW)

Fre

qu

en

cy

1000 Random Vectors, 1000 Sample Circuits

Power Estimation ResultPower Estimation Result Circuits implemented using TSMC025 2.5V CMOS library , with standard Circuits implemented using TSMC025 2.5V CMOS library , with standard

size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulation was run on a obtained by assuming ± 20 % variation. The simulation was run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM.UNIX operating system using a Intel Duo Core processor with 2 GB RAM.


ConclusionConclusion Bounded delay model allows power Bounded delay model allows power

estimation method with consideration of estimation method with consideration of

uncertainties in delays.uncertainties in delays.

Analysis has a linear time complexity in Analysis has a linear time complexity in

number of gates and is an efficient alternative number of gates and is an efficient alternative

to the Monte Carlo analysis.to the Monte Carlo analysis.


Future RefinementsFuture Refinements Consider process dependent variations in leakage and in Consider process dependent variations in leakage and in

node capacitances. node capacitances. Use statistical methods to determine distributions of average Use statistical methods to determine distributions of average

and peak power consuming circuits. See following and peak power consuming circuits. See following references:references: V. Bartkute and L. Sakalauskas, “Three Parameter Estimation of the Weibull V. Bartkute and L. Sakalauskas, “Three Parameter Estimation of the Weibull

Distribution by Order Statistics,” in C. H. Skiadas, editor, Distribution by Order Statistics,” in C. H. Skiadas, editor, Recent Advances in Recent Advances in Stochastic Modeling and Data AnalysisStochastic Modeling and Data Analysis, pp. 91–100, World Scientific, 2007., pp. 91–100, World Scientific, 2007.

Q. Qiu, Q. Wu, and M. Pedram, “Maximum power estimation using the Q. Qiu, Q. Wu, and M. Pedram, “Maximum power estimation using the limiting distributions of extreme order statistics,” in Proc. Design Automation limiting distributions of extreme order statistics,” in Proc. Design Automation Conference, June 1998, pp. 684–689.Conference, June 1998, pp. 684–689.

Q.Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in VLSI Q.Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics,” IEEE Circuits Using the Limiting Distributions of Extreme Order Statistics,” IEEE transactions on Computer Aided Design of Integrated Circuits and Systems, transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, p. 942.vol. 20, no. 8, p. 942.


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