i

Copyright

by

Zhihong Huang

2006

ii

The Dissertation Committee for Zhihong Huang Certifies that this is the

approved version of the following dissertation:

Germanium Photodetector Integrated with

Silicon-based Optical Receivers

Committee:

Joe C. Campbell, Supervisor

Sanjay K. Banerjee

Paul S. Ho

Archie L. Holms, Jr.

Jack C. Lee

iii

Germanium Photodetector Integrated with

Silicon-based Optical Receivers

by

Zhihong Huang, B.S.; M.S.

Dissertation

Presented to the Faculty of the Graduate School of

The University of Texas at Austin

in Partial Fulfillment

of the Requirements

for the Degree of

Doctor of Philosophy

The University of Texas at Austin

December, 2006

iv

Dedicated

To my parents

Xianli Huang, Shujie Ye

and my brother

Zhiyan Huang

v

Acknowledgements

I would like to thank Dr. Joe Campbell for giving me the opportunity to

join his research group. His diligent working attitude, stringent research

methods, and the positive and collaborative working environment in the group

taught so much from research to life. I also want to thank Dr. Sanjay Banerjee,

Dr. Paul Hole, Dr. Jack Lee and Dr. Archie Holmes, for being my committee

members, and their support in my Ph.D. study.

Thank you to my groupmates and my friends at MER, including

Jungwoo Oh, Xiaowei Li, Shuling Wang Xiangyi Guo, Mingguo Liu, Ariane

Beck, Ning Duan, Gauri Carve, Ning Kong, Lijuan Zhang, Xin Wang, Yujie

Liu, Liang Wang, Jun Liu, Lanlan Gu, Li Lin, Fei Li, Xuguang Wang, and

Yongqiang Jiang, Michal Oye, Sachin Joshi, Brenda Francis for your friendship

and providing me such a friendly and collaborative working environment,

making my graduate life enjoyable. I also want to thank staffs at MER, Jean

Toll, Carol Assadourian for your sincerely help and assistance during my

graduate study.

I really want to appreciate for Hao Chen, Yan Pei, Li Wang, Linlin

Wang, Feng Zhu and Leigh Huchison for your sincere friendship, genuine

caring, and earnest advice and help. I feel so lucky to have friends like you, it is

your sincere friendship brought warmth, peace and gratefulness to my life.

vi

Linlin Wang, Peng Lv, Yi Hong, Yu Lu, Jodi Heatly, and Kim Polk, thank you

for being such wondering roommates, I enjoyed sharing my life with you.

Finally, I want to deeply appreciate for my parents, Shujie Ye, Xianli

Huang, my brother Zhiyan Huang for your unconditional love, infinite caring,

and endless support. I won’t finish my study without your support, it is your

love made me feel the love, peace and happiness in heaven. God bless you!

vii

Germanium Photodetector Integrated with

Silicon-based Optical Receivers

Publication No._____________

Zhihong Huang, Ph.D.

The University of Texas at Austin, 2006

Supervisor: Joe C. Campbell

With the development of fiber optics communication systems and optical

interconnects, there is an increased demand for low-cost, high-speed, high-

sensitivity optical receivers. Previously, our group has demonstrated Si

photodiodes integrated with CMOS preamplifier circuits. In order to extend the

operating wavelength to 1300nm, Ge photodetectors integrated with Si has been

studied for Si based optical receivers in this work. Ge has the advantage of

compatability with much of Si process technology, as well as the high mobility

and large absorption coefficient at 1300 nm.

viii

The key challenge for Ge photodetector integrated with Si is the growth

of high quality Ge layer on Si. In this work, a successful Ge growth technique

has been developed by using a UHV-CVD system. The preliminary integration

of Ge photodetector with Si CMOS circuits has also been demonstrated.

To further improve the device performance, a SiGe buffer layer

technique has been investigated to reduce the dark current of the photodetector.

Directly growing Ge on Si generates many dislocations which increase dark

current. By using the SiGe buffer layers, many threading dislocations can be

“trapped” at the heterojunction interface, thereby reducing the dislocation

density in the Ge layer and the photodetector dark current. A backside-

illuminated photodetector has been fabricated with the dark current as low as 12

mA/cm2 at 1 V reverse bias, as well as the responsivity of 0.57 A/W and the

bandwidth of 8.7 GHz. To improve the speed of these devices, another device

with thinner SiGe buffer layers were demonstrated and achieved 21.5 GHz

bandwidth at 1.31μm, resulting in a record high efficiency-bandwidth product of

12.9 GHz.

ix

Table of Contents

List of Tables ........................................................................................................ xii

List of Figures ...................................................................................................... xiii

Chapter 1

Introduction.............................................................................................................1

1.1. Motivation.....................................................................................1

1.2. Introduction...................................................................................2

1.3. Literature review...........................................................................9

1.4. Thesis organization .....................................................................22

Chapter 2

UHV-CVD growth and Ge photodetector fabrication and characterization ..........................................................................................24

2.1. Overview.....................................................................................24

2.2. UHVCVD system and Ge material growth ................................24

2.3. Device fabrication process..........................................................29

2.4. Device characterization...............................................................32

2.5. Conclusion ..................................................................................36

Chapter 3

Growth and Characterization of Ge Epitaxial Layers ....................................37

3.1. Overview.....................................................................................37

3.2. Literature review of the fundamental epitaxial growth mechanism ..................................................................................37

3.3. Experiment..................................................................................43

3.4. Results and discussion ................................................................44

3.5. Material and device characteristics for Ge grown at 400ºC and 700ºC....................................................................................52

x

3.6. Conclusion ..................................................................................59

Chapter 4

Effectiveness of SiGe layer in reducing dark current ....................................60

4.1. Overview.....................................................................................60

4.2. Literature review of dislocation theory and its correlation to dark current .................................................................................60

4.3. Experiments ................................................................................68

4.4. Material Characterization............................................................71

4.5. Device Characterization and discussion .....................................74

Chapter 5

High performance Ge Photodetector on Si .....................................................79

5.1. Overview.....................................................................................79

5.2. Ultra low dark current PD...........................................................80

5.3. The advantages of backside illumination....................................89

5.4. Ultra high speed photodetectors..................................................90

5.5. Comparison of the Ge-on-Si photodiodes ..................................98

5.6. Conclusion ................................................................................100

Chapter 6

Planar Interdigitated Ge Photodiode on Si....................................................102

6.1. Overview...................................................................................102

6.2. Planar p-i-n photodiode structure and fabrication ....................102

6.3. Interdigitated Ge photodiode characteristics ............................106

6.4. High responsivity planar photodiodes with thick Ge layers .....111

6.5. Conclusion ................................................................................113

xi

Chapter 7

Summary and future work: Process integration of Ge-on-Si with Si MOSFETs ..................................................................................................114

7.1. Summary ...................................................................................114

7.2. Future work...............................................................................115

Appendix: Publications............................................................................124

Bibliography........................................................................................................126

Vita……………………………………………………………………………..142

xii

List of Tables

Table 2.1: Comparison of the planer and the vertical Ge photodiodes:.................28

Table 4.1. Summary of growth condition for samples A, B, C and D...................70

Table 5.1. Summary of structures for samples A, B, and B2. ...............................79

Table 6.1: Comparison of the planar and the vertical Ge photodiodes:...............113

xiii

List of Figures

Fig. 1.1: Absorption coefficient of Ge and InGaAs............................................5

Fig. 1.2: Absorption coefficient of SiGe with 0, 20, 50, 75, and 100%

Ge fraction............................................................................................6

Fig. 1.3: Energy-band structures of (a) Si and (b) Ge. .......................................8

Fig. 1.4: Schematic cross-section of completed Si-based optical

receiver...............................................................................................21

Fig. 1.5: Schematic diagram of monolithically integrated Si-optical

receiver...............................................................................................21

Fig. 2.1: UHV-CVD growth system used for this work...................................28

Fig. 2.2: Schematic cross-sectional view of the Ge photodiodes. ....................29

Fig. 2.3: Experimental apparatus used to measure photodiode

quantum efficiency.............................................................................33

Fig. 2.4: Experimental setup used to measure the frequency response. ...........34

Fig. 2.5: Experimental setup used to measure the impedance of the

photodiodes. .......................................................................................35

Fig. 3.1: A schematic illustration of the three equilibrium growth

modes: (a) Frank-van de Merwe (layer-by-layer), (b)

Volmer-Weber (Cluster), and (c) Stranski-Krastanov (layer-

cluster)................................................................................................39

Fig. 3.2: a) AFM surface morphology of samples grown at 400ºC

12mTorr for (a) 1 hour, (b) 2.5 hours, (c) 7 hours, and (d) 12

hours...................................................................................................47

xiv

Fig. 3.3: (a) Ge grown on Si for 1 hour at 600ºC, (b) 650ºC (c) 700ºC

(d) 750ºC; (e) Ge surface roughness versus growth

temperature.........................................................................................49

Fig. 3.4: Ge grown at 700 ºC in (a) 3 mTorr, (b) 6 mTorr, and (c) 12

mTorr. ................................................................................................50

Fig. 3.5: Square pits on Ge grown at (a) 550 ºC, (b) 600 ºC, (c) 700

ºC, and (d) 750 ºC. .............................................................................52

Fig. 3.6: (a) Cross section TEM picture for 0.7-μm-thick Ge film

grown at 400 ºC, and (b) 0.92-μm-thick Ge grown at 700

ºC........................................................................................................54

Fig. 3.7: Photodiode current-voltage characteristics for Ge grown at

400ºC and 700ºC. ...............................................................................55

Fig. 3.8: Capacitance density versus voltage curve for a Ge-on-Si

device. Inset: Extracted depletion width at different voltages

from C-V curves.................................................................................57

Fig. 3.9: Localized energy levels due to structural defects . ............................57

Fig. 3.11: Photodiode responsivities for Ge grown at 400 ºC and 700

ºC........................................................................................................58

Fig. 4.1: Illustration of misfit dislocation (AB) and threading

dislocation (BC) geometry at a GexSi1-x/Si interface. ........................64

Fig. 4.2: Film structure and growth conditions of sample B. ...........................70

Fig. 4.3: (a) AFM surface morphology of sample A; (b) Si0.50Ge0.50

surface of sample B before annealing, (c) the Si0.50Ge0.50

xv

surface of sample B after 750 ºC 15 minute anneal, (d)

surface of Si0.40Ge0.60 buffer in sample B after 750 ºC 15

minute anneal, and (e) sample B Ge surface morphology. ................73

Fig. 4.4: TEM micrographs of (a) sample A, (b) sample B..............................74

Fig. 4.5: Current density versus voltage characteristics for sample A

and sample B. .....................................................................................75

Fig. 4.6: Current density verus voltage characteristics for sample C

and sample D......................................................................................76

Fig. 5.1: (a) Secondary ion mass spectroscopy of the Ge epitaxial

film with 1-μm-thick SiGe buffer layers; (b) Cross sectional

schematic of the Ge on Si photodiode structure.................................82

Fig. 5.2: a) I-V characteristics of Ge mesa diodes of different

diameters. Dark circle and solid line: 24 μm; dark square on

solid line: 48 μm; dark triangle on solid line: 100 μm. b)

dark current versus area at 1 V and 2 V reverse bias; circle

on solid line: measured data; square on dash dotted line: fit

from bulk leakage/area and surface leakage/diameter;

triangle on dashed line: fit to square of the diameter. At –1

V, the bulk current density is 12 mA/cm2, the surface

current density is 0.318 μA/cm; and at –2 V, the bulk

current density is 28 mA/cm2, the surface current density is

0.7 μA/cm...........................................................................................84

xvi

Fig. 5.3: Responsivity for backside illumination and frontside

illumination. .......................................................................................85

Fig. 5.4: (a) Capacitance voltage characteristics, (b) extracted

depletion width versus voltage for sample B. ....................................87

Fig. 5.5: (a): RF response for 24-μm-diameter devices at different

biases. .................................................................................................88

Fig. 5.6: Cross sectional TEM micrograph of the sample with two

thin SiGe buffer layers (sample B2). .................................................92

Fig. 5.7: Current versus voltage characteristics of 20-, 40-, and 100-

μm-diameter Ge mesa diodes.............................................................93

Fig. 5.8: Capacitance density - voltage curve on sample B2. Inset:

Extracted depletion width at different voltages from C-V

curves. ................................................................................................94

Fig. 5.9: Responsivity for backside illuminated devices on sample

B2, with and without a SiO2 anti-reflective coating. .........................95

Fig. 5.10: (a) RF response at 1.31 μm for 20-μm-diameter and 40-

μm-diameter devices at 10 V and 5 V reverse bias,

respectively. (b) RF response at 1.55 μm for 20-μm-

diameter and 40-μm-diameter devices at 10 V and 5 V

reverse bias, respectively. (c) RF response verses reverse

bias at 1.31 μm for 20-μm-diameter devices. ....................................98

Fig. 5.11: Responsivity of sample A, sample B and sample B2.......................99

xvii

Fig. 5.12: RF response at 1.31μm for a 20-μm-diameter device in

sample A (no SiGe buffer layer) and sample B2 (thin SiGe

buffer layers) at 3 reverse bias, and in sample B (thick SiGe

buffer layers) at 10V reverse bias. ...................................................100

Fig. 6.1: Planar Ge photodiodes with interdigitated p+- and n+-fingers

fabricated on Ge-on-Si substrate. (a) Top view and (b)

Cross-sectional view ........................................................................105

Fig. 6.2: Completed interdigitated PIN photodetector ...................................106

Fig. 6.3: Current versus voltage characteristics of the planner

interdigitated device in 51x64 μm2 area. .........................................108

Fig. 6.4: Responsivity of p-i-n photodiodes with 1μm finger width

and 5μm finger spacing....................................................................108

Fig. 6.5: RF response of the photodiode with 1μm finger width and

2μm finger spacing...........................................................................110

Fig. 6.6: Raster scanned photoresponse for a planner p-i-n

interdigitated device at (a) 1V and (b) 5V reverse bias. ..................111

Fig. 6.7: Responsivity of the photodiode fabricated on the 2.6-μm-

thick Ge film for the planar structure with 1 μm finger width

and 5 μm finger spacing, and for the vertical structure. ..................113

Fig. 7.1: (a) I-V characteristics of 50-μm-diameter photodiodes

fabricated on selective area growth. (b) Responsivity of the

photodiode experienced the same process with Si MOSFET. .........118

xviii

Fig. 7.2: (a) Id-Vg and (b) Id-Vd characteristics of the MOSFETs in

the demonstrated chip. .....................................................................119

Fig. 7.3: (a) Etch pits on a 50-μm-diameter selective- area- growth

mesa. (b) Blue line: I-V characteristics of 50-μm-diameter

photodiodes fabricated on selective area growth; red line: I-

V characteristics of a 40-μm-diameter device fabricated on

full-surface Ge without selective area growth. ................................121

Fig. 7.4: Schematics cross-sectional view of Ge photodiode

integrated with Si MOSFET. ...........................................................123

1

Chapter 1

Introduction

1.1. Motivation

Fiber-to-the-home access networks, chip-to-chip interconnects, and on-

chip optical interconnects have gained widespread interest owing to the inherent

advantages of large bandwidth, high noise immunity, and reduced power

dissipation and crosstalk of optical communication systems. As complementary

metal oxide semiconductor (CMOS) transistors scale down and approach their

scaling limits in the next two generations, optical interconnects may emerge as

an alternative to electrical interconnects. Monolithically integrated high-speed,

low-cost, high-efficiency optical receivers on silicon chips are key components

for this application owing to their advantages of low-cost manufacturability and

easy mass production with silicon (Si) integrated circuit (IC) fabrication

technology.

Silicon-compatible photodetectors are important optical component for

optical receivers. Previously, Si photodetectors monolithically integrated with

existing Si ICs have been demonstrated at 850 nm. Recently, several research

efforts have focused on photodetectors operating at 1.3 and 1.55μm, in order to

extend to the optical communication wavelengths. This dissertation will present

2

research on germanium (Ge) photodetectors on Si operating at 1.3 and 1.55μm

for optical receiver applications.

1.2. Introduction

1.2.1. Long-wavelength Si-based optical receivers and

photodetectors

In an optical communication link, the information that exists in electrical

form, modulates an optical signal in a transmitter and the optical signal

propagates through an optical fiber before arriving at a receiver. At the receiver,

the signal is converted from the optical format into the electrical domain by a

photodetector, and is then amplified and demultiplexed.

The receiver circuits can be made using Si bipolar or MOSFET circuit

architecture. Si bipolar-based receivers have the advantage of higher transistor

transconductance and operating speed [1]. On the other hand, Si CMOS-based

receivers offer low power dissipation and compatibility with ubiquitous CMOS

manufacturing technology for both analog and digital applications [2][3].

Previously, most Si-based optical receivers operated at 850 nm. However,

receivers working at a wavelength of 1.3 μm can take advantage of the

technology base developed for optical transmission systems. Recently, in order

to extend the operating wavelength to 1300 nm, Ge photodetectors have been

3

monolithically integrated with Si [4]. Ge photodiodes have the advantages of

integratibility with Si, high absorption coefficient, and high mobility.

Two of the most important characteristics of receivers are sensitivity and

speed, which largely depend on the performance of the integrated

photodetectors. A high performance photodiode must provide high quantum

efficiency, low leakage current and high speed at a bias voltage compatible with

Si CMOS.

The external quantum efficiency, η, for a photodetector is a measure of

how many electron hole pairs are created and collected per incident photon. The

external quantum efficiency can be expressed as:

)1)(1( dext eR αη −−−=

where R is the reflectivity of the material, α is the absorption coefficient of the

absorption region of the photodiode, and d is the absorption length. For normal

incidence, the absorption length is usually ~1 - 2 μm which requires the

absorption coefficient be 104 cm-1 to achieve high quantum efficiency.

The dark current of a photodetector is the current, which is generated in

the absence of optical excitation. This is determined to a great extent by the

device structures, and the material quality. Usually, dark current is high for

materials with narrow bandgap and high intrinsic carrier concentration. For a

lattice-mismatched material system, the large density of dislocations may be the

dominant contribution to the dark current. This will be discussed in detail in

4

chapter 3. In an optical receiver system, the dark current of the photodiode

contributes to the noise of the receiver.

The speed of a photodetector measures how fast the photodetector

responds to a modulated optical input. In an optical receiver, the speed of the

photodetector is an important factor. For example, a 10 Gbit/s optical network

generally requires the photodetector to have a bandwidth greater than 6 GHz.

The speed is determined by both RC and the transit-time components of the

bandwidth. For normal-incidence photodiodes there is a trade off between the

speed and the quantum efficiency. In order to achieve high quantum efficiency,

a thick absorption region in the photodetector is desired, but this increases the

distance the generated carriers must traverse and limits device speed. This

problem can be reduced when the active region has a high absorption coefficient

so that high quantum efficiency can be obtained with less absorption thickness.

Other approaches to circumvent the quantum efficiency/bandwidth tradeoff are

resonant cavity enhance (RCE) photodiodes or waveguide photodetectors [5][6].

1.2.2. Selection of material for photodetectors

As stated above Si photodetectors have been widely used in 850 nm

optical receivers, however, the bandgap of Si (1.12 eV) limits the operating

wavelength to < 1.1μm. Both InxGa1-xAs and Ge have high absorption at 1.3 μm

which makes them suitable for the long wavelength photodiodes. Figure 1.1

5

shows the optical absorption coefficient of germanium and In0.53Ga0.47As as a

function of wavelength. However, InxGa1-xAs as a III-V material is difficult to

grow epitaxially on Si due to the large lattice mismatch and the cross

contamination between the III-V materials and Si. Ge, a group IV material,

avoids the cross contamination problem. Recently, Ge and Si1-xGex alloys have

been utilized in high performance Si-based integrated circuits. At the same time,

they have narrower bandgap and higher absorption coefficient than Si. Figure

1.2 shows the absorption coefficient for Ge fractions of 0, 20, 50, 75, and 100 %

in SiGe [7].

In0.

53G

a 0.47

As

1 05

1 0

1 04

1 02

1 03

1 0 -1

1 0 3

1

1 0 2

1 0

Ligh

t Pen

etra

tion

Dep

th (μ

m)

Abs

orpt

ion

Coe

ffic

ient

(cm

-1)

W av e le n g th (μ m )0 .4 0 .6 0 .8 1 .0 1 .2 1 .4 1 .6 1 .8

3 2 0 .5 1 0 .7P h o to n E n e rg y (e V)

S i

G a A s

G eIn

0.53

Ga 0.

47 A

s1 05

1 0

1 04

1 02

1 03

1 0 -1

1 0 3

1

1 0 2

1 0

Ligh

t Pen

etra

tion

Dep

th (μ

m)

Abs

orpt

ion

Coe

ffic

ient

(cm

-1)

W av e le n g th (μ m )0 .4 0 .6 0 .8 1 .0 1 .2 1 .4 1 .6 1 .8

3 2 0 .5 1 0 .7P h o to n E n e rg y (e V)

S i

G a A s

G e

Fig. 1.1: Absorption coefficient of Ge and InGaAs.

6

Fig. 1.2: Absorption coefficient of SiGe with 0, 20, 50, 75, and 100% Ge

fraction.

It is worth noting that the origin of the high absorption coefficient of Ge

is its specific band structure. Figures 1.3(a) and 3(b) show the band structure of

Si and Ge, respectively. Both Si and Ge are indirect band gap material, the edge

of the Si conduction band is close to the X-valley, and the edge of the Ge

conduction band is at the L-valley. The fundamental absorption mechanism is

that electrons are excited from the valence band to the conduction band through

photon absorption. Generally, direct band-to-band excitation has higher

transition probability than indirect absorption due to momentum conservation

[8]. The primary difference between the Si and Ge band structures is that the Ge

conduction band has a Γ -valley minimum (0.8 eV) close to the valence band

7

edge and thus has a much higher transition probability for direct transitions.

Most Ge absorption comes from this direct band-to-band transition, which

results in an absorption cutoff energy of ~0.8 eV, corresponding to ~1.6 μm.

This direct transition process occurs at short wavelength absorption due to its Γ-

valleys (3.4 eV, 4.2 eV) are far from the valence band edge. In the near IR, the

optical absorption in Si requires electrons at the valence band edge to be excited

to the X-valley (lowest energy). This requires a photon, an electron and a

phonon, thus, in order to conserve momentum. This “three body process”

generally has lower transition probability and lower absorption coefficient.

(a)

8

Fig. 1.3: Energy-band structures of (a) Si and (b) Ge [9].

In addition to the fact that Ge has high absorption coefficient at 1.3 μm,

it also has higher carrier mobility than Si for both electrons (3x) and holes (4x).

The hole mobility of Ge is even higher than that of GaAs. For electronic

applications, SiGe technology has been used in high-volume and large-scale

manufacturing of heterojunction bipolar transistors (HBTs) and SiGe-HBT-

BiCMOS circuits. The dopant thermal activation energies are much lower than

those in silicon, which is advantageous for the formation of shallow junctions.

From the discussion above, it is clear that Ge is an attractive candidate

for monolithic integration with Si-based optical receivers. However, due to the

large lattice mismatch between Ge and Si, the key challenge of fabricating Ge

(b)

9

photodetectors on Si is the high dislocation density formed during epitaxial

growth.

1.3. Literature review

Despite the potential advantages afforded by Ge devices, the growth

techniques and material quality of Ge on Si have limited the performance and

potential for integration with Si integrated circuits (ICs). In this section, a

literature review of epitaxial growth of Ge on Si and the performance of Ge

photodiodes and associated optical receivers is presented.

1.3.1. Ge on Si epitaxial growth

Various techniques have been pursued to achieve a relaxed Ge layer on

Si with low defect density. Ge layers grown by ultrahigh vacuum chemical

vapor deposition (UHV-CVD) or molecular beam epitaxy (MBE) have

demonstrated significant reduction in the threading dislocation density. The

related material studies can be categorized by the Ge growth techniques used in

improving the material quality.

Ge growth with graded SiGe buffer layers

10

The use of a compositionally graded SiGe buffer region is an effective

technique in reducing the dislocation density. This approach usually grades the

Ge concentration 10 % per 1 μm, which results in a thick 10 μm buffer if the Ge

content varies from 0 % to 100 %. The slow compositional grading of the

epilayer circumvents high strain conditions, which minimizes dislocation

nucleation and filters the threading dislocations.

This technique was first utilized in the GeSi/Si system by E. A.

Fitzgerald et al. in 1990. They grew fully-relaxed compositionally graded

GexSi1-x layers on Si substrate at 900 oC using molecular beam epitaxy (MBE)

and rapid thermal chemical vapor deposition (RTCVD) techniques [10]. The

high temperature growth ensured the complete relaxation of the graded SiGe

buffer. The final strain-relaxed Si1-xGex layers grown on these graded layers

showed low density of threading-dislocations, 4 x 105 cm-2 and 3 x 106 cm-2 for

x = 0.23 and x = 0.50, respectively.

In 1998, M. T. Currie et al. also studied the graded SiGe structures using

this technique in combination with an intermediate chemical mechanical

polishing (CMP) step at the Si0.5Ge0.5 layer [11]. The CMP step liberated

dislocations and created the necessity to nucleate new dislocations.

Surfactant assisted Ge growth

Surfactant meditation is another effective technique to improve material

11

quality during epitaxial growth. It involves the adsorption of a small amount of

certain elements onto the Si substrate during Ge growth [12][13]. The effect of

adsorbed atomic hydrogen on the evolution of Ge films grown on Si substrates

by solid source MBE was reported by A. Sakai et al. in 1993 [14]. A hot

tungsten filament was used to dissociate molecular hydrogen. The H flux was

supplied separately from the Ge flux which allowed control of the H

concentration on the surface without any variation in the other growth

parameters. It was observed by cross-sectional high resolution transmission

electron microscopy (HRTEM) that H adsorbed on the growth front played a

role in suppressing island formation of Ge. This phenomenon can be explained

as a kinetic effect by which the H surfactant reduces the diffusion length of Ge

adatoms during growth. Extensive studies have also been done for Ge growth on

Si substrates using As, Sb, Te, and Bi as surfactants [15][16][17][18][19][20]. In

general, Ge growth proceeds by the Stranski-Krastanov (SK) growth mode in

which a layer by layer mode is followed by three-dimensional islanding. With a

surfactant, island formation is strongly suppressed, resulting in the layer-by-

layer mode throughout. It was reported that the introduction of a monolayer of a

surfactant completely changed the growth mode from island growth to 2-D layer

growth (Frank van der Merwe growth mode) with a continuous and smooth Ge

film on Si (111) [21]. The surfactant was not incorporated but segregated and

floated on the growing Ge film which caused surface free energy reduction by

12

the saturation of the dangling bonds. This reduction of activation energies

enhanced the diffusion and the mobility of Ge.

Surfactant mediation technique can also be used in combination with the

graded SiGe buffer layer techniques. J. L. Liu et al. reported high-quality Ge

grown on Si using 4-μm-thick compositionally-graded SiGe buffer layers with

Sb surfactant-mediation in a solid-source MBE system [22][23]. The surfactant-

mediated Ge had a threading dislocation density of 5.4 x 105 cm-2 and

photodiodes fabricated on this material achieved 0.15 mA/cm2 dark current at 1

V reverse bias. They showed that with the presence of a surfactant facilitated

dislocation glide with lower activation energy in the graded layers. They also

showed that the threading dislocation densities of the samples with Sb

surfactant-mediated graded buffers were less than those by other methods when

the grading rate was about 50% per 1 μm or less. As the grading rate increases,

the threading dislocation density increased for both Sb-mediated samples and

those samples without Sb-mediation.

Two step Ge growth in the UHVCVD system

The two step growth technique of epitaxially growing Ge on Si has

attracted wide interest for Ge epitaxial growth. This method was first developed

for GaAs growth on Si by Fan et al. in 1986 [24]. It was utilized in the Ge/Si

sytem by Luan et al. in a UHVCVD growth reactor in 1999. This method

13

employed a 50-nm-thick, low-temperature Ge buffer layer grown at 350 ºC,

followed by a high temperature (~600 ºC) Ge layer [25]. In-situ cyclic

annealing was performed subsequent to the epitaxial growth to further reduce

the dislocation density in the Ge layer. The low temperature Ge buffer layer

facilitated stress relief in the first few hundred angstroms and the overlying Ge

layer exhibited significant reduction in the density of dislocations. Furthermore,

cyclic annealing enhanced the migration of threading dislocations to further

reduce the number of dislocations. The threading dislocation density was

measured to be 2 x 107 cm-2. By epitaxially growing Ge in a selective area, the

threading dislocation density was measured to be 2.3 x 106 cm-2.

Halbwax et al. also studied this technique, particularly the effect of

thermal annealing and the utility of a low temperature Ge buffer layer in

reducing the threading dislocation density [26][27]. They reported that (1) a two

hour anneal at 750 ºC can achieve the same quality Ge film as a ten cycle

anneal between 780 ºC and 900 ºC and (2) the low-temperature buffer layer

has to be thicker than 27 nm to effectively reduce the threading dislocation

density in the Ge layer.

Thin SiGe buffer layer

Recently, a method of utilizing two thin SiGe layers as an intermediate

buffer region prior to the growth of Ge in a UHV-CVD system has been

14

reported by Luo et al. [28][29]. In this method, two compositions of Si1-xGex

buffer layers were incorporated prior to the growth of the 1 μm top Ge layer.

The interfaces between Si1-xGex/Si1-yGey and Si1-yGey/Ge were known to

effectively terminate the upward-propagation of dislocations, for y minus x ~

0.05 to 0.1. Most of the threading dislocations appear to be blocked and

confined in the underlying interfaces. For example, for Si0.1Ge0.9 and Si0.05Ge0.95

buffer layers, the threading dislocation density was 3 x 106 cm-2. This is due to

the fact that by adjusting the SiGe compositions, when the stress field around a

heterojunction interface is strong enough, the dislocations can be bent and

propagated parallel to the interface, thus reducing the threading dislocation

density in Ge. The stress field can be altered by adjusting the composition of the

SiGe buffer layer. Surface roughening caused by the non-uniform stress field

can block the dislocations as well [30].

1.3.2. Progress of Ge photodetectors

Ge photodiodes with graded SiGe buffer layer

Various Ge photodetectors have been fabricated and studied using Ge

grown by the epitaxial growth techniques described above. One earlier attempt

was done by Luryi et al. in early 1980s, where an 1800-Å-thick step-graded

SiGe buffer layer was employed between the top Ge film and the underlying Si

15

substrate. The Ge p-i-n photodiodes fabricated from this material showed an

external quantum efficiency of 40 % at 1.45 μm, when measured in a short-

circuit configuration [31].

Samavedam et al. fabricated improved p-n Ge photodiodes in 1998,

using a thick graded SiGe buffer with an intermediate CMP step in which the

growth was interrupted when the SiGe composition reached 50% of Ge,

afterward, other SiGe layers with Ge composition higher than 50% were graded

grown on the polished wafer [32]. The SiGe buffer layer thickness was ~>10

μm. The Ge layers were in situ doped with PH3 and B2H6 to form the n and p

layers with doping concentration of 1.1x1018/cm3 and 1.3x1018/cm3,

respectively. The leakage current was 0.2 mA/cm2 under a reverse bias of 1 V,

and the quantum efficiency was 12.6% at1.3 µm wavelength.

Oh et al. studied interdigitated Ge-on-Si photodetectors fabricated with a

1-μm-thick Ge epitaxial layer grown on a Si substrate using a 10-μm-thick

graded SiGe buffer layer [33]. A growth rate of 45 Å/s was achieved using low-

energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had

a threading dislocation density of 105 cm-2 and a rms surface roughness of 3.28

nm. The 3-dB bandwidth and the external quantum efficiency were measured on

a photodetector having 1 μm finger width and 2 μm spacing with a 25 μm x 25

μm active area. At a wavelength of 1.3μm, the bandwidth was 2.2, 3.5, and 3.8

GHz at bias voltages of 1, 3, and 5 V, respectively. The dark current was 3.2 and

16

5.0 μA at 3 and 5 V, respectively. This photodetector exhibited an external

quantum efficiency of 49% at a wavelength of 1.3 μm.

The graded SiGe buffer layers achieve good Ge quality for photodetector

applications. However, this method is not suitable for monolithic integration

with Si CMOS owning to the large thickness of the buffer region.

Ge photodiodes on materials grown in MBE system

Ge photodetectors have been fabricated from Ge grown by MBE. In

2002, Buca et al. reported metal-germanium-metal (MSM) photodetectors [34].

The MSMs were fabricated on 270-nm-thick Ge epitaxial layers. Interdigitated

Cr metal top electrodes with 1.5 - 5 µm spacing and identical finger width

formed Schottky contacts to the Ge film. These photodiodes exhibited a

response time of 12.5 ps full width at half maximum at both 1300 and 1500 nm

wavelength. The overall external quantum efficiency was 13 % at 1320 nm and

7.5 % at 1500 nm.

Jutzi et al. reported a Ge p-i-n photodiode fabricated in Ge grown by

MBE system in 2004. A 50-nm-thick Si buffer layer was first deposited

followed by a 300 nm boron doped p+ Ge layer. A 300-nm-thick Ge intrinsic

layer was then grown at 300 ºC in the MBE system with a doping concentration

of 1016 cm-3. The n+ layer was grown by depositing a 200-nm-thick Sb-doped

Ge. Finally, a 25-nm strained Si cap layer with Sb doping was used for the top

17

ohmic contact layer. P-i-n photodiodes fabricated on this material exhibited 39

GHz bandwidth, and 16% and 2.8% quantum efficiency at 1.31 and 1.55μm,

respectively [35].

Ge photodetectors fabricated on Ge grown by the two-step technique

Recently, Ge-on-Si photodiodes fabricated on Ge grown by the two step

growth technique achieved excellent performance. As described above, this

approach utilizes a low-temperature Ge buffer followed by a high-temperature

Ge film and cyclic annealing in an ultra high vacuum/ chemical vapor deposition

(UHV-CVD) system.

In 1998, Colace et al. reported MSM photodetectors fabricated on ~1-μm

–thick, relaxed Ge layers grown by this technique [36]. The detector showed

good responsivity at normal incidence at both 1.3 μm and 1.55 μm, with a

maximum responsivity of 0.24 A/W at 1.3 μm under a 1 V bias. A response time

of about 2 ns was measured. The dark current exhibited a superlinear

dependence on the applied bias.

In 2002, Fama et al., reported a p-i-n photodiode on a highly doped Si

substrate [37 ]. The photodiode had a top n-type contact, the intrinsic layer was

epitaxial Ge, and the bottom p-type contact was the Si substrate with resistivity

of 0.008 Ωcm. To form the top n contact, phosphorous was implanted at 30 keV

at a dose of 4x1015 cm2 forming a 200-nm-thick n-type region. The p-type

18

substrate was chosen in order to get the most favorable band alignment for the

collection of the photogenerated carriers. The p-i-n photodetectors achieved a

responsivity of 0.89 and 0.75 A/W at 1.31 and 1.55 μm, dark currents as low as

1.2 µA respectively and a temporal response <200 ps at 1.31 μm.

In 2004, Dehlinger et al. reported planer p-i-n interdigitated photodiodes

fabricated on Ge-on-SOI [38]. The Ge layer was grown directly on an ultra-thin

SOI substrate using the two step growth technique in a UHV-CVD system.

Planar interdigitated photodiodes with finger spacing of 0.6 μm achieved a 3-dB

bandwidth of 29 GHz at -4V, with a peak quantum efficiency of 46% at 850 nm,

and 3.4% at 1.31 μm.

In 2005, J. Liu et al. reported a 0.25% tensile strained Ge p-i-n

photodetector on Si substrate using the two step growth technique with cyclic

annealing in an UHV-CVD system [39]. Following a 60-nm-thick Ge layer

grown at 335 °C, a 2.35μm Ge epitaxial film was grown at 700 °C. The tensile

strain in the Ge film extended the band edge of the Ge film from 1550 to 1623

nm, enabling effective photon detection at the 1550 nm. The responsivities of

the device at 1310, 1550, and 1620 nm were 600, 520, and 100mA/W at 0 V

bias. The absorption coefficient of 0.25% tensile strained Ge near 1550 nm has

been estimated to be nearly an order of magnitude higher than bulk Ge.

In 2005, Dosunmu et al. reported resonate-cavity-enhanced Ge Schottky

photodetectors on a silicon-on-insulator substrate. The basic structure consists of

19

a Ge layer heteroepitaxially grown on a double-side polished silicon-on-

insulator (SOI) substrate. The ion-cut SOI substrate provided back-illuminated

reflectivity (55%) around the 1550 nm wavelength range. A p-i-n structure was

formed through the two step growth technique followed by the cyclic annealing.

The current-voltage response from a 10 μm diameter Ge detector revealed a dark

current of 380 nA at 5V reverse bias, quantum efficiency of 59% at 1.55 μm,

and a bandwidth of 12.1 GHz [40].

1.3.3. Optical receivers progress

In this section, research on Si-based optical receivers is reviewed.

Previously, monolithically-integrated all Si optical receivers consisting of a

silicon p-i-n photodiode and a MOSFET transimpedance preamplifier (TIA)

circuit have been developed at the University of Texas at Austin

[41],[42],[43],[44],[45],[46],[47],[48], [49],[50],[51],[52]. The development

involves several generations of photodiodes and circuits. The first generation

used a Si NMOS preamplifier circuit and demonstrated a receiver with

sensitivities of -9.3 dBm, -26 dBm, and -32 dBm for 1 Gbit/s, 300 Mbit/s and

155Mbit/s at bit error rate (BER) of 10-9. The Si planar pin photodiode in the

receiver showed an external quantum efficiency of 74% at 870 nm and a dark

current of 1.3 pA at 5 V. The speed was limited by the long absorption length

for the photodetector and the TIA circuit. In order to improve the speed of the

20

NMOS preamplifier, a SiGe HBT preamplifier was proposed. A resonant-

cavity-enhanced (RCE) photodiode was also fabricated and it achieved higher

speed [45].

The second generation optical receiver used SOI substrate for the

photodiodes and NMOS preamplifier circuits, the speed of the photodiodes was

improved. P-i-n photodiodes achieved 3.4 GHz bandwidth and 24% quantum

efficiency at 840 nm when biased at -3 V. The dark current was measured to be

less than 25 pA at -5 V and the capacitance was 265 fF [49].

Following this project, the third generation all-Si optical receivers were

built using 1300 nm CMOS process technology in collaboration with Motorola.

A Si p-i-n photodetector with a Si CMOS preamplifier on SOI were integrated

[50]. The processing was carried out in one of Motorola’s 8-inch pilot lines and

was totally compatible with their CMOS process. The detector achieved error-

free detection up to 8 Gb/s. Figure 1.4 shows a schematic diagram of the

monolithically integrated Si-optical receiver.

As the project proceeds into the fourth generation, an optical receiver

that will operate at 1.3 and 1.55 µm optical communication wavelength is under

investigation. Figure 1.5 shows a schematic of the optical receiver with Si

MOSFETs and Ge photodiodes integrated on Si substrate. As the first step in the

project, Ge photodetectors integrated with Si substrate were first studied by Oh

[33][53]. The work described in this dissertation continues the study of Ge

21

photodiodes on Si. After achieving the desired photodiode performance, it is

anticipated that the project will move toward monolithic integration.

Si pre-amplifier

Si Photodetector

Si pre-amplifier

Si Photodetector

Fig. 1.4: Schematic cross-section of completed Si-based optical receiver.

n- -Si substrate

Si pre-amplifier

p-wellSiO2

n+ n+p+n+p+

Ge p-i-n photodiode

Ge epitaxial layer

i

n- -Si substrate

Si pre-amplifier

p-wellSiO2

n+ n+p+n+p+

Ge p-i-n photodiode

Ge epitaxial layer

n- -Si substrate

Si pre-amplifier

p-wellSiO2

n+ n+p+n+p+

Ge p-i-n photodiode

Ge epitaxial layer

i

Fig. 1.5: Schematic diagram of monolithically integrated Si-optical receiver.

22

In addition to the research conducted at UT Austin, other Si-based

optical receivers have achieved good results. Jutzi et al. reported a

monolithically integrated optical receiver fabricated in a 0.18 μm silicon CMOS

technology [54]. The receiver featured a spatially modulated photodetector to

suppress slow diffusion tails and the receiver circuit comprised a TIA, a limiting

amplifier, and an output buffer. At 2 Gb/s and an incident wavelength of 850nm,

the receiver achieved a sensitivity of 8 dBm at a bit-error rate of 109.

In 2005, Schares et al. reported a 17 Gb/s low power optical receiver

using a Ge-on-SOI lateral p-i-n photodiode using a 0.13 μm CMOS IC [55]. A

10x10μm2 Ge photodiode with 0.7 μm finger width was wire bonded to the

input pads of the CMOS IC. The photodiode had 23GHz bandwidth at -2 V bias

with low dark current and 52% external quantum efficiency at 850 nm. The TIA

was a modified common-gate circuit that incorporates multi-metal-level

interdigitated ac coupling capacitors as well as photodiode bias resistors. At 12.5

Gb/s, the receiver achieved sensitivity of -10.3 dBm at BER of 10-12 with -1.8 V

bias. Clearly open eyes were observed up to 17 Gb/s.

1.4. Thesis organization

In this thesis, in order to integrate low dark current, high responsivity,

high speed Ge photodetectors on Si substrate, Ge and SiGe material growth

techniques, Ge photodiode fabrication and characterization techniques, and

23

methods of reducing the dark current of photodiodes using thin SiGe buffer

layers have been investigated. Chapter 2 presents the Ge growth, device

fabrication and characterization techniques used in the research. Chapter 3

investigates the Ge growth techniques in the UHV/CVD system to optimize the

Ge growth conditions such as temperature, chamber pressure and growth time.

Chapter 4 investigates the effectiveness of SiGe buffer layers in reducing the

dark current in Ge-on-Si photodiodes. Different SiGe buffer layer thicknesses,

compositions have been used. A method of optimizing the SiGe buffer layers

has been developed. Chapter 5 discusses high-speed, low-dark-current, high-

responsivity Ge-on-Si photodiodes with thin SiGe buffer layers. Chapter 6

introduces planar p-i-n photodiodes fabricated on Ge with SiGe buffer layers.

Finally, Chapter 7 summarizes the research and introduces future work for the

monolithically integrated Si optical receivers.

24

Chapter 2

UHV-CVD growth and Ge photodetector fabrication and characterization

2.1. Overview

This chapter discusses the epitaxial growth, fabrication, and

characterization techniques used in the research of Ge photodetectors integrated

with Si. An ultra-high-vacuum-chemical-vapor-deposition (UHV-CVD) system

is first discussed for the Ge epitaxial growth. This is followed by a detailed

description of the fabrication procedures for Ge photodiodes. Finally, the

current-voltage, capacitance-voltage, quantum efficiency and speed

measurement setups for the electrical and optical characterization of the Ge

photodiodes are described.

2.2. UHVCVD system and Ge material growth

Chemical vapor deposition (CVD) is one of the most widely employed

film growth methods in VLSI technology. In a conventional Si CVD system,

silicon oxidizes instantaneously upon exposure to room ambient [56]. The native

oxide that grows on the Si surface is removed by in situ high temperature

desorption in H2 ambient [57]. In addition, performing Si epitaxy at high

25

temperature (~1000 ºC) served to compensate for the presence of significant

levels of system contamination, especially residual water vapor and oxygen in

the chamber [ 58 ]. However, the evolution of Si technology to smaller

dimensions and sharper junctions requires a lower thermal budget. Research has

shown that in order to obtain good epitaxy at temperatures significantly lower

than 700 ºC, the partial pressure of H2O has to be at the 10-8 Torr level

(ultrahigh-vacuum level). Similar requirements are found for the oxygen partial

pressure.

UHV-CVD was developed in the early 90’s for low temperature SiGe

epitaxial growth as an integral part of research on high-speed heterojunction

bipolar transistors and high-mobility, two-dimensional-hole-gas structures

[59][60]. In the UHVCVD system, the base pressure is <10-9 Torr to reduce the

amount of water and oxygen in the chamber before and during the epitaxial

growth. This makes it possible to grow high quality metstable SiGe films at low

temperature. In addition, in order to remove the native SiO2 on the epi-ready Si

wafer, rather than using high temperature oxide desorption for surface

preparation, the silicon surface is prepared by hydrogen passivation. An adlayer

of hydrogen-silicon bond is formed in the process of etching Si in HF and was

shown to reduce the reactivity of the silicon surface with respect to oxidants

such as oxygen and water by 13 orders of magnitude [59].

26

In this work, a cold-wall UHV-CVD deposition system was used for the

epitaxial Ge growth. Fig. 2.1 shows the cold-wall UHV-CVD deposition system

at the Microelectronics Research Center at the University of Texas at Austin.

The system consists of a load-lock chamber and a main chamber. The load-lock

chamber was used to prevent the main chamber from being exposed to the

atmosphere during wafer loading. Preceding the epitaxial growth, the wafers

were cleaned in piranha solution (H2SO4:H2O2 = 2:1) for 10 minutes to remove

organic contamination and then etched in HF (HF:H2O = 1:20) solution for 40s

to remove the native oxide. Simultaneously, a nitrogen box was mounted on the

loadlock door to prevent the cross contamination during wafer loading. After

loading the wafer into the loadlock chamber, a sorption pump was connected in

parallel with the turbo pump to quickly pump-down of the load lock chamber to

200mTorr. A turbo pump and a mechanical pump were then used to bring the

load lock chamber to a pressure of below 1x10-7 Torr. An 8 inch gate valve

accomplished isolation of the load-lock chamber from the growth chamber.

The main chamber was pumped to a base pressure of 5x10-10 Torr using a

Balzers turbomolecular pump which was backed by a dual-stage Alcatel

mechanical pump with a rated foreline pressure of 10-4 Torr. The initial high

vacuum obtained in the main chamber was due to the high temperature baking

of the system. Most water vapor and residue gas partial pressure were < 10-12

Torr after the bake out. During growth, the Si wafer was heated by a substrate

27

heater attached to the top of the main chamber. The heater consisted of five

quartz-halogen lamps enclosed in a molybdenum box. The lamps were powered

by a single-phase 120 V SCR, which was manipulated by a temperature

controller. The substrate was held with its backside facing the lamps and was

supported by three quartz pins. Two pyrometers were used to monitor the

temperature at the center and edge of the wafer. This heater arrangement did not

allow rapid variation in deposition temperature. However, the growth rates were

not always reproducible because of the open-loop control. Ultra-high purity

gases were brought to the growth chamber through 316 L stainless steel lines

from gas cylinders. The gas lines from the cylinder were connected to mass flow

controllers (MFC) that can control the gas flow to within 2 percent of its full-

scale value. Table 1 lists the gases used in this work as well as their

concentrations and the maximum flow rate values of the MFCs. The flow rate

readings for the MFCs are given in standard cubic centimeter per minute (sccm).

No dopant was used for the Ge epitaxy in this research due to film nucleation.

The detailed Ge epitaxial growth techniques will be discussed in chapter 3 - 4.

28

Fig. 2.1: UHV-CVD growth system used for this work.

Table 2.1: Comparison of the planer and the vertical Ge photodiodes:

Gas Concentration Maximum flow (sccm)

Si2H6 100% 20

GeH4 40% in Ar 38

29

2.3. Device fabrication process

In this section, the fabrication processes for both front-illuminated and

backside-illuminated photodiodes are discussed. A schematic cross-sectional

view of the Ge photodiodes is shown in Fig. 2.2. The substrate was chosen to be

highly-doped Si, which can serve as a contact layer to form an ohmic contact.

For photodiode applications, a Ge layer more than 1-μm-thick was needed for

absorption. For the basic electrical and optical measurements, the devices were

fabricated simply by mesa etch, passivation, metallization, backside polishing

and anti-reflection (AR) coating.

Fig. 2.2: Schematic cross-sectional view of the Ge photodiodes.

2.3.1. Mesa-etch

The photodiode fabrication started with the definition of a mesa structure

by reactive ion etching (RIE). The wafer was first cleaned by rinsing it in

n+- Si substrate

Ge buffer

Ge

n-contact

30

acetone, methanol, de-ionized water (DI) and blowing it dry with nitrogen. This

was the most frequently used cleaning step in the fabrication process, and it was

done prior to every photolithography step. After the cleaning, the mesa structure

was defined by patterning of AZ5214 photoresist as etching mask. The

photoresist was spun on the wafer at the speed of 4000 rpm for 40 seconds, then

the wafer was soft-baked at 90 ºC for 5 minutes, resulting in 1.4-μm-thickness.

After being carefully aligned to the mask on a Karl-Suss contact aligner, the

wafer was exposed 45 seconds under g-line UV light. The development took

about 30 - 40 seconds in AZ726 solution.

After patterning, the p-mesa was etched by reactive ion etching (RIE)

with BCl3 and SiCl4 gas at a power of 100 W and a pressure of 50 mTorr. The

etching rate for Ge and SiGe was significantly faster than Si. The Ge etch rage is

approximately 80 nm/minute. RIE usually defined a vertical etching profile and

did not undercut like wet etching. It is also worth noting that during the RIE

etching, the photoresist mask is also etched at ~50nm/mintue. When etching a

thick Ge structure, two layers of photoresist were applied to obtain a photoresist

mask of 3-μm-thickness, which can effectively protect the mesa for a

45minutes-RIE-etch.

2.3.2. Passivation

After etching the mesa and solvent removal of the photoresist, in order to

31

reduce the high dark current due to leakage along the mesa sidewall, a

passivation layer was deposited. A standard passivation was performed using

plasma- enhance-chemical-vapor-deposition (PECVD) of 1000 Å of silicon

dioxide. Before the wafer was loaded into the PECVD chamber, the wafer had

to be carefully cleaned using BOE. This ensured that the sidewall of the mesa

was clean. For a front-illuminated device, the SiO2 passivation layer also served

as a top AR coating, hence a thickness of 2100 Å was used usually deposited.

2.3.3. p and n Metallization

The contact patterns were defined by a second photolithography step. To

ensure low ohmic contact resistance, an Al (1200 Å) layer was deposited as both

the n- and p-contacts on the Ge by e-beam evaporation. Afterwards, the wafer

was immersed in acetone for lift-off. Sometimes an ultrasonic bath was needed

for a clean lift-off. Then the wafer was rapid thermal annealed at 400 ºC for

1minute. In most cases, good ohmic contact can be achieved without thermal

annealing because it was easy to form ohmic contacts to the highly doped Si

substrate and the low-bandgap Ge. The formation of frontside illuminated

photodiodes was finished at this step.

2.3.4. Backside polish and AR coating

32

For backside illuminated devices the substrate side of the wafer was

polished. This permits light illuminating from the backside of the wafer.

Double-side polished Si wafers can also be used to solve this problem. Then

2200 Å SiO2 was deposited on the backside of the wafer as an AR coating. This

thickness of the SiO2 was carefully chosen so that an 88% transmittance was

achieved for backside-illumination. After this step, the fabrication of Ge

photodiodes was finished.

2.4. Device characterization

2.4.1. Current-voltage and capacitance-voltage measurements

The current-voltage (IV) characteristics of the photodetectors were

measured using a HP4156 semiconductor parameter analyzer. The transfer

length method (TLM) was used to analyze the specific contact resistance and the

sheet resistance. The capacitance-voltage (CV) was measured with an HP

4275A LCR meter. From the measured capacitance, the depletion width and the

doping profile of the device can be estimated.

2.4.2. Quantum Efficiency measurement

The quantum efficiency was characterized by illuminating with 1.3 μm

laser light and measuring photocurrent. The quantum efficiency can be

33

calculated using the photo current divided by the incident optical power which

was measured with a power meter, using the equation:

)1)(1( d

o

phext eR

hPqI α−−−=ν

=η (1)

In order to study the optical response of the device across the whole

spectrum, a broad band quantum efficiency setup was used. A tungsten-

halogen lamp filtered by a grating spectrometer provided a tunable optical input.

The optical input was transmitted through a chopper to introduce a frequency-

dependent signal, and the chopper frequency was set at ~200 Hz. The device

position was adjusted to achieve the maximum photoresponse. The electrical

output of the device was measured using a SR 850 lock-in amplifier tuned to the

frequency of the chopper. The entire measurement process was then repeated

with a calibrated photodiode to extrapolate the quantum efficiency of the

photodiode. A schematic of this apparatus is depicted in Fig. 2.3.

Light Source (Tungsten-Halogen)

Grating -Spectrometer(Spex 500M)

Computer

Lock-in Amplifier (Stanford Research

Model 510)

Mirror

Chopper

Microscopeobjective

DUTLight Source

(Tungsten-Halogen)

Grating -Spectrometer(Spex 500M)

Computer

Lock-in Amplifier (Stanford Research

Model 510)

Mirror

Chopper

Microscopeobjective

DUT

Fig. 2.3: Experimental apparatus used to measure photodiode quantum

efficiency [61].

34

2.4.3. Speed measurement

The frequency response of the Ge photodetectors was determined using a

HP 8703A Lightwave Component Analyzer (LCA). The LCA provided a

combination of calibrated 20 GHz lightwave and microwave measurement

capabilities, for the optical, electrical, and electro-optical measurements. The

bandwidth was measured in the frequency domain. The optical source in the

LCA is a 1.3 μm distributed feedback laser with a typical spectral width of less

than 50 MHz and a peak-to-peak modulated optical out power of 130 μW. The

frequency of modulation was swept over a bandwidth range from 130 MHz to

20 GHz and the photodetectors were biased on-wafer using microwave probes.

Figure 2.4 shows the frequency response measurement apparatus.

DC Bias

Optical Fiber

ElectricalCableDUT

Bias-T

Pin

Iout

1.3 μm DFB LaserModulation Frequency(130 MHz ~ 20 GHz)

Optical InElectrical Out

Lightwave Component

Analyzer (HP8703A)

DC Bias

Optical Fiber

ElectricalCableDUT

Bias-T

Pin

Iout

1.3 μm DFB LaserModulation Frequency(130 MHz ~ 20 GHz)

Optical InElectrical Out

Lightwave Component

Analyzer (HP8703A)

Fig. 2.4: Experimental setup used to measure the frequency response.

35

2.4.4. Impedance measurement

The impedance of the photodiodes is also measured by the HP 8703A LCA

in the reflection mode. A microwave cable, a high-speed bias tee, and a high

speed microwave probe were connected as shown in Fig. 2.5. The measurement

calibration was conducted by the standard open, short, and 50 Ω impedance.

After the calibration, the photodiodes were biased through the microwave probe.

The LCA measured the reflection coefficient of the photodiode at a bias. The

impedance of the device can be read from the Smith chart and be stored on the

computer controller. From the measured impedance results, the RC-limited

bandwidth can be estimated.

Fig. 2.5: Experimental setup used to measure the impedance of the

photodiodes.

DC Bias

ElectricalCable DUT

Bias-T

Iin Iout Impedance Feedback

NetworkAnalyzer (HP8703A)

36

2.5. Conclusion

The Ge material growth and Ge photodiode fabrication and

characterization process have been presented in this chapter. The UHVCVD

growth system and its low temperature growth capabilities have been described.

The fabrication process including mesa etching, passivation, metallization, and

backside polishing and AR coating has been presented. Finally, the

measurement setups for the photodiode electrical and optical characterization

have been discussed.

37

Chapter 3

Growth and Characterization of Ge Epitaxial Layers

3.1. Overview

This chapter discusses the epitaxial growth of Ge on Si. A literature

review of the general growth mechanisms is first introduced. This is followed by

a discussion of Ge epitaxial growth on Si at different temperatures and pressures

in a UHV-CVD system. Then, material characteristics of Ge grown at 400 ºC (a

low temperature) and 700 ºC (a high temperature) are compared. Photodiodes

fabricated on these materials are also characterized in terms of I-V, C-V, and

responsivity.

3.2. Literature review of the fundamental epitaxial growth mechanism

In this section, the fundamental epitaxial growth mechanisms are

reviewed. This begins with the discussion of equilibrium growth modes which

only consider the ideal growth conditions in the absence of reaction and

interdiffusion. Then the epitaxial growth kinetic processes are introduced

considering growth kinetics and thermodynamics, and three kinetic growth

modes are introduced. These mechanisms can be applied to any growth system.

38

Finally, the mechanisms of growing Ge on Si substrate are specifically

discussed.

3.2.1. Equilibrium growth

Theoretically, equilibrium epitaxial growth modes are determined by the

free energy of the substrate surface (σs), the interface free energy (σi), and the

surface free energy of the heteroepitaxial layer (σf). In reality, no growth can

occur at equilibrium; film growth always experiences kinetics and

thermodynamics. However, it is useful to consider this ideal limit for the

fundamental material analysis [62]. Under equilibrium conditions, the crystalline

growth can be classified into three basic modes, depicted schematically in Fig.

3.1. The Frank-Van der Merwe (layer-by-layer growth), Volmer-Weber

(islanding growth), and Stranski-Krastanov (layer-by-layer growth followed by

islanding growth) [63]. The inequality σs > σf + σi sets the condition for the

epitaxial film to wet the substrate representing the layer-by-by growth [64]. The

opposite extreme (σs < σf + σi) obtains islanding growth. In the intermediate

case, the adlayer initially wets the substrate, but because of lattice mismatch, as

the layer thickness increases, strain energy contributes to σi, to the point at

which the film no longer wets the substrate. Subsequently, islands and misfit

39

dislocations are formed to relieve strain. The thickness beyond which the onset

of misfit dislocation is favorable is the critical thickness. Besides misfit

dislocation formation, roughening of the growth front is another strain relaxation

mechanism.

Fig. 3.1: A schematic illustration of the three equilibrium growth modes: (a)

Frank-van de Merwe (layer-by-layer), (b) Volmer-Weber (Cluster), and (c)

Stranski-Krastanov (layer-cluster) [62].

40

3.2.2. Kinetic growth

In reality, film growth cannot occur under equilibrium condition. In most

cases, especially in a vapor deposition system, growth occurs by supersaturation,

in which the 2-D vapor pressure is higher than that at equilibrium and the kinetic

process can greatly affect the growth morphology. Growth thermodynamics and

kinetics can be partially controlled by substrate temperature and chamber

pressure. Under kinetic growth conditions far from equilibrium, even in a

homogenous epitaxial growth, two-dimensional (2-D) islands and 3-D clusters

can form to relax the system back toward equilibrium. The lateral

accommodation kinetics determine the growth shape of the islands and a variety

of growth-front morphologies can be obtained depending on which kinetic

process is rate limiting [65]. Three kinetic growth modes are observed: layer-by-

layer growth, kinetically rough growth, and step flow growth [62].

(1) Layer-by-layer growth: If the growth rate is low or the substrate

temperature is sufficiently high to accommodate adatoms diffusion, layer-by-

layer growth can be achieved. In this growth mode, adatoms have sufficient

mobility to find one another. Nucleated 2-D islands can grow and ultimately fill

in the initial starting surface. This growth mode usually shows an increase of

surface roughness with increasing coverage because the previously deposited

layer is never completely filled before the next layer nucleates.

41

(2) Kinetically rough growth: This type of growth occurs for relatively

high deposition rate and slow lateral adatoms diffusion, in which atoms migrate

only on the order of a few lattice sites before they incorporate into the growing

film. Growth under these conditions leads to a rough surface for which the

roughness amplitude increases with increasing film thickness.

(3) Step flow growth: A better way to ensure a smooth surface during

deposition is to grow in the step flow growth mode. This is achieved when

deposited atoms have sufficient time to migrate and incorporate into a step

before other atoms are deposited on the surface. This is desirable for keeping the

surface smooth. To maintain this condition, the deposition must be relatively

slow or the substrate temperature must be high enough for adatoms to diffuse far

enough to incorporate into steps before nucleating islands. In the following

experiment, this high temperature Ge film shows lower threading dislocations

and higher absorption coefficient compare to the Ge film grown at low

temperature.

3.2.3. Ge epitaxial growth on Si

In the case of epitaxial growth of Ge on Si with large lattice mismatch,

the Ge-Ge bond is weaker than the Si-Si bond, leading to a smaller surface

42

energy. Consequently, the system of Ge/Si is usually discussed as a classical

model for the Stranski-Krastanov growth mode. The critical thickness is

generally considered to be 5 nm [62]. In the kinetic model, given sufficient

mobility of Ge adatoms, preferential growth will occur in the relaxed region,

leading to the nucleation of three-dimensional (3-D) clusters. It has been

reported that for pure Ge deposited on Si (001), by the third ML, strain energy

can no longer be released by 2-D growth, and the growth mode changes from 2-

D to 3-D, accompanied with the increased surface roughness. At a later stage,

these 3-D structures relax to the Ge lattice constant and produce a high density

of misfit dislocations between the substrate/epilayer interface and islands in the

epilayers.

Previous research showed that the Ge-grown-on-Si process is surface-

reaction limited at temperatures below 450 ºC and is mass transport limited

above 450 ºC. This has been observed both in rapid thermal chemical deposition

(RPCVD) systems and in UHV/CVD systems [66][67]. It has also been reported

that at 330 ºC [68] (or 350 ºC [69]), Ge growth occurs in Stranski-Kroastanov-

related 2-D layer-by-layer mode. The major part of the relaxation process occurs

during the deposition of the first two monolayers and the relaxation occurs

primarily by the generation of misfit dislocations at the Ge/Si interface. Above

375 ºC, growth occurs by the 3-D kinetically rough mode, in which islands form

and the Ge surface roughness dramatically increases [69]. This is usually

43

accompanied by a high dislocation density, increased leakage current, and

degraded device performance. When the temperature increases above 600 ºC,

the step flow growth mode with reduced threading dislocation density and

continuous 2-D growth is observed [70][71][72].

3.3. Experiment

Based on the discussion above, the Ge growth temperature is of great

importance to the film roughness and misfit dislocation density. Ge grown at

lower temperature (under 350 ºC) or higher temperature (above 600 ºC) can

achieve smooth 2-D growth. In this section, Ge epitaxial growth in the

UHVCVD system has been studied under different temperatures and pressures.

First, Ge film characteristics are studied under various growth temperatures with

a constant chamber pressure of 12 mTorr. Later, the Ge film is studied at

different chamber pressures at 700 ºC.

The cold wall UHV-CVD system discussed in Chapter 2 was used for Ge

heteroepitaxial growth on Si. The base pressure of the main chamber was 1x10-9

Torr. Pure Si2H6 and GeH4 (diluted at 40% in Ar) were used as gas sources. The

substrates were n-type Si (001) wafers with resistivity in the range of 0.008 -

0.02 Ω-cm. Preceding the epitaxial growth, the wafers were cleaned in piranha

44

solution (H2SO4:H2O2 = 2:1) for 10 minutes to remove organic contamination

and then etched in HF (HF:H2O = 1:20) solution for 40 s to remove the native

surface oxide. After loading a wafer into the growth chamber, a 50 nm Si buffer

was grown at 750 ºC to form a clean “epi-ready” surface on the Si wafer. Then,

a 50-nm-thick low temperature Ge buffer layer was grown at 350 ºC. Following

the low temperature Ge growth, about 1-μm-thick Ge film was grown at

different temperatures. No annealing was performed on the top Ge layer.

Samples were examined using cross-sectional Transmission Electron

Microscopy (TEM). The Ge surface morphology was analyzed by Atomic Force

Microscopy (AFM) in the contact mode. Backside-illuminated mesa-structure

photodiodes were fabricated as described in Chapter 2. In order to illuminate

from the backside, the Si wafer was polished and 2000 Å of SiO2 was deposited

as an anti-reflecting coating.

3.4. Results and discussion

3.4.1. Ge growth ≤ 350 ºC

When the temperature is below 330 ºC no Ge film growth on Si occurs

because the thermal energy is insufficient to decompose the GeH4

45

precursor.Between 330 ºC – 350 ºC, the chemical reaction rate is low, which

causes a low growth rate. Usually, 1 hour growth only deposits a 50-nm-thick

Ge film. Hence, this condition is not suitable for the photodetector absorption

region growth which requires more than 1-μm-thick Ge film. However, growth

under this condition achieves a smooth surface (surface roughness rms is ~0.4

nm). In this temperature range, Ge growth occurs in the 2-D layer-by-layer

mode. This Ge layer relaxes most of the stress in the first few hundred

angstroms, and a subsequent Ge layer can be epitaxially grown without

generating many dislocations [68]. Even a few-hundred-angstrom-thick, low-

temperature Ge layer can be a good strain relaxation buffer layer between Ge

and Si. This can be used as a virtual substrate for a thick Ge film growth. In our

Ge growth experiments, this low temperature Ge buffer layer is always grown

before any other Ge layer growth. Previous researchers reported similar results;

Luan et al. [73] and Liu et al. [74] reported that a good quality Ge film with

more than 2-μm-thickness can be achieved by pre-depositing a 30 ~ 70-nm-thick

Ge buffer layer at 330 ºC – 350 ºC. Halwax et al. [75] also suggested that this

low temperature buffer layer has to be thicker than 27 nm to effectively reduce

the threading dislocation density in a Ge layer.

3.4.2. Ge growth at low temperature (370 ºC – 500 ºC)

46

Between 370 ºC – 500 ºC, the Ge growth rate is relatively low for a

photodetector absorption region. A 1-μm-thick Ge film usually takes 4 - 8 hours

to grow, and the growth rate varies with small changes in the growth conditions,

such as chamber temperature, pressure, etc. As the substrate temperature

increases, the Ge deposition rate increases exponentially.

Figures 3.2(a) - 3.2(d) show Ge surfaces grown at 400 ºC and 12 mTorr

for 1 hour, 2.5 hours, 7 hours, and 12 hours, respectively. The AFM measured

root-mean square (rms) surface roughness is 0.4, 2.2, 3.1, and 6.9 nm,

respectively. It is clear that surface roughness and island sizes increase with

growth time. In this temperature regime, the Ge growth is in the kinetically

rough growth mode. The slow lateral diffusion of adatoms migrate a short

distance before they incorporate into the epitaxial film. Hence growth under

such condition leads to a rough surface for which the roughness amplitude

increases with increasing film thickness.

47

Fig. 3.2: a) AFM surface morphology of samples grown at 400ºC 12mTorr for

(a) 1 hour, (b) 2.5 hours, (c) 7 hours, and (d) 12 hours.

3.4.3. Ge growth at high temperature ( > 600ºC )

When the Ge growth temperature exceeds above 600ºC, the step flow

growth condition is achieved. The growth rate increases slowly with increasing

temperature. It takes 1 hour to achieve around 1-μm-thick Ge at 12mTorr. The

AFM-measured surface morphologies grown at 600 ºC, 650 ºC, 700 ºC, and 750

ºC are shown in Fig. 3.3(a) - 3.3(d), respectively. At 600 ºC, the surface

(b)(a)

1μm 1μm (c) (d)

1μm 1μm

48

roughness rms is approximately 1nm, and it is 0.66, 0.50 and 0.48 nm at 650 ºC,

700 ºC and 750 ºC, respectively. Fig. 3.3(e) shows the correlation between the

surface roughness and growth temperatures, indicating that the Ge surface

roughness tends to saturate above 700 ºC. The surface roughness rms of Ge

grown at 400 ºC is also shown in Fig. 3.3(e) for comparison.

(d)

(a) (b)

(c)

1μm

1μm 1μm

1μm

49

Fig. 3.3: (a) Ge grown on Si for 1 hour at 600ºC, (b) 650ºC (c) 700ºC (d)

750ºC; (e) Ge surface roughness versus growth temperature.

3.4.4. Ge growth at different pressures

During Ge CVD growth, the chamber pressure is another factor that

affects Ge material quality. Having sufficient precursor to enable a chemical

reaction sets the pressure lower-limit of 12 mTorr of GeH4 (40% Ar) for most

growth. Figures 3.4(a) - 3.4(c) show the surface morphologies of 700 ºC Ge

grown at 3, 6 and 12 mTorr, respectively. Ge surface roughess is 0.7, 0.4, and

0.6 nm, respectively, and the growth rate reduces linearly with the chamber

pressure. It is also clear that more steps patterns on the Ge surface with

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

300 400 500 600 700 800

Substrate Temperature (ºC)

Surf

ace

Rou

ghne

ss (n

m) LT growth for reference

HT growth

50

decreasing pressure, which is due to insufficient Ge step coverage under low

chamber pressure. Hence, the chamber pressure is set to 12 mTorr for fast

growth rate and sufficient step coverage.

Fig. 3.4: Ge grown at 700 ºC in (a) 3 mTorr, (b) 6 mTorr, and (c) 12 mTorr.

3.4.5. Square pit formation at 500 ºC – 600 ºC

In the UHV-CVD growth, rough and hazy films were occasionally

observed when the growth temperature was between 500 ºC – 600 ºC.

Microscopic observation shows that in addition to island formation similar to

that of low temperature growth, many reverse-pyramid-shape square pits

appeared on Ge surfaces. For a 1-μm-thick Ge film, the square pits are 2μm -

5μm-wide, and ~ 0.75-μm-deep, square pits diameters increase with increasing

(a) (b) (c) (c)

51

Ge film thickness. Figures 3.5(a) and 3.5(b) show the Ge surface

morphologies at 550ºC and 600ºC, respectively. Most edges of the square pits

are along [110] directions, and their densities vary with different growth

conditions. Generally, pit density is higher at 550 ºC than at 600 ºC. It is also

observed that by increasing the growth temperature above 700 ºC, the square pit

density was reduced below 104 cm-2, which is less than 1 pit per 100 μm x 100

μm area. The Ge surfaces grown at 700ºC and 750ºC are shown in Fig. 3.5(c)

and 3.5(d), respectively. The purposed reason for the formation of square pits is

deficient adsorption of GexO1-x residues which form defect centers and induce

square pit defects on the as-grown Ge surface within this temperature regime

[76]. This is consistent with the GexO1-x adsorption temperatures reported by Oh

[77], which infers that the square pits can be reduced by decreasing the oxygen

concentration in the growth chamber.

52

Fig. 3.5: Square pits on Ge grown at (a) 550 ºC, (b) 600 ºC, (c) 700 ºC, and (d)

750 ºC.

3.5. Material and device characteristics for Ge grown at 400 ºC and 700

ºC

3.5.1. TEM comparison and discussion

(a) (b)

(c) (d)

53

Figures 3.6(a) and 3.6(b) show cross-sectional TEM micrographs of a

0.7-μm-thick Ge film grown at 400 ºC and a 0.92-μm-thick Ge film grown at

700 ºC, respectively. The TEM pictures clearly show that threading dislocations

propagate from the Ge/Si interface to the Ge surface for both films, but the 700

ºC Ge has lower dislocation density. The TEM pictures also show that the 700

ºC Ge has more 90º threading dislocations, while at 400 ºC, there are more 60º

dislocations. The formation of 90 º dislocations is suggested to be the

annihilation of 60º dislocations during high temperature growth or annealing

[62]. The theory of misfit dislocation and threading dislocation are interpreted in

Chapter 4.

Si substrate

0.2 μm

Ge/Si interface

Surface

Ge

Si substrate(a)

54

Fig. 3.6: (a) Cross section TEM picture for 0.7-μm-thick Ge film grown at 400

ºC, and (b) 0.92-μm-thick Ge grown at 700 ºC.

3.5.2. Current-voltage characteristics

Photodetectors were fabricated on the Ge films grown at 400 ºC and

700ºC. Figure 3.7(a) shows the current density versus voltage characteristics. At

1V reverse bias, the dark current density was 0.1 A/cm2 and 0.176 A/cm2 for the

400 ºC and 700 ºC Ge, respectively, and it was 1.188 A/cm2 and 0.875 A/cm2 at

5 V reverse bias. Hence, both Ge photodiodes exhibit high dark currents. Since

both Ge layers exhibit high misfit dislocations densities as indicated is by the

Ge/Si interface

Surface

Ge

Si substrate (b)

55

TEM pictures in the previous section, the dark current is primarily generation

current from dislocations in the Ge epitaxial layers.

Voltage (V)-10 -8 -6 -4 -2 0 2

Dar

k C

urre

nt D

ensi

ty (A

/cm

2 )

10-4

10-3

10-2

10-1

100

101

400 oC Ge700 oC Ge

Fig. 3.7: Photodiode current-voltage characteristics for Ge grown at 400ºC and

700ºC.

3.5.3. Capacitance characteristics

Capacitance-voltage (C-V) characteristics and Hall effect were measured

for both Ge materials grown at 700 ºC and 400 ºC. C-V characteristics were

measured using an LCR bridge. The capacitance per unit area is shown in Fig.

3.8 with the calculated depletion width shown in the inset. The C-V

56

measurement shows the 700ºC Ge epitaxial layer to be p-type with acceptor

concentration of 5x1015 cm-3, and the Hall measurement indicates that the

acceptor concentration is 1017 cm-3 in the 400 ºC Ge film. Both samples were

also submitted for secondary ion mass spectroscopy (SIMS) analysis to identify

any possible dopants that might have been introduced during the deposition. The

boron and phosphorous concentration in both Ge layers was at the instrumental

background. This indicates that the background doping was not the cause of the

acceptor concentrations. Instead, the p-type Ge is due to structural imperfection,

specifically the Ge-Si dislocated strain field. It has been reported that

structural defects in Ge lead to acceptor states near the valence band edge [78].

Figure 3.9 shows the localized energy states caused by these structural defects.

The lower p-type acceptor concentration of the 700 ºC Ge compared to 400 ºC

indicates the removal of these shallow hole traps by increasing the growth or

annealing temperature [79].

57

Fig. 3.8: Capacitance density versus voltage curve for a Ge-on-Si device.

Inset: Extracted depletion width at different voltages from C-V curves.

EC

EV

Eg = 0.67 eV

0.18 eV 1.

0.13 eV 3.0.15 eV 2.

Fig. 3.9: Localized energy levels due to structural defects [80].

Voltage (V)0 1 2 3 4 5 6C

apac

itanc

e D

ensi

ty (F

/cm

2 )

1e-8

1e-7

Voltage (V)0 1 2 3 4 5 6

Dep

letio

n W

idth

( μm

)0.0

0.2

0.4

0.6

0.8

1.0

58

3.5.4. Responsivity

The responsivity has been measured by illuminating through the

substrate with a 1.3 μm laser source. Fig. 3.10 shows that the responsivity

saturates at 0.53 A/W for the 700 ºC samples, and 0.27 A/W for the 400 ºC Ge.

Even considering the 0.2-μm-thick Ge thickness difference between two

materials, the Ge layer grown at 700 ºC still has higher absorption coefficient

than that at 400 ºC. King el al. reported minority carrier recombination lifetime

reduction by increasing the oxygen content in GeSi [81]. The SIMS data show

that the oxygen concentration is higher in the low temperature Ge than the high

temperature sample. The high oxygen concentration is suspected to be

responsible for the low absorption coefficient for low the temperature Ge film.

Fig. 3.11: Photodiode responsivities for Ge grown at 400 ºC and 700 ºC.

Voltage (V)0 1 2 3 4 5 6

Res

pons

ivity

(A/W

)

0.0

0.2

0.4

0.6

0.8

1.0

700ºC Ge

400ºC Ge

59

3.6. Conclusion

This chapter has discussed the basic epitaxial growth conditions for

growing Ge on Si at different temperatures and pressures in a UHV-CVD

system. The material characteristics and their photodiodes are compared for the

400 ºC and the 700 ºC Ge layers. The Ge epitaxial layer grown at high

temperature shows better surface roughness and absorption characteristics. The

Ge films that will be discussed in the next a few chapters are grown at high

temperature (500 ºC – 700 ºC) and 12 mTorr pressure.

60

Chapter 4

Effectiveness of SiGe layer in reducing dark current

4.1. Overview

This chapter discusses dislocation reduction methods in Ge epitaxial

growth on Si substrate. Since threading dislocations are known minority carrier

generation centers contributing to the dark current of a photodiode, the

mechanisms to create dislocations and the correlation between dislocation and

dark current are discussed first. Previous work related to dislocation reduction is

then reviewed. Finally, a method of utilizing two thin SiGe buffer layers is

introduced in this work in order to effectively reduce dislocations in Ge.

Photodiodes fabricated on materials using this growth technique demonstrate

reduced dark current. The origin of dark current and the effect of annealing the

SiGe buffer layers are also discussed.

4.2. Literature review of dislocation theory and its correlation to dark

current

4.2.1. Strain relaxation and dislocations

61

Strain accommodation mechanisms

In SiGe/Si and Ge/Si growth system, the key challenge is the lattice

mismatch between Si and Ge which generates strain during an epitaxial growth.

Hull discussed four strain accommodation mechanisms in Ref. 82:

(1) Elastic distortion of atomic bonds in the epitaxial layer: This mechanism

causes the stored elastic strain energy in the epitaxial layer to be accommodated

by the distortion of lattice bonds. But this is only effective up to the critical

thickness, beyond that thickness misfit dislocations will form.

(2) Interdiffusion across the epitaxial layer/substrate interface: This is significant

only for growth or annealing temperature of order of 800 ºC more than 1 hour,

and it is not a significant mechanism in the UHVCVD system.

(3) Roughening of the epitaxial layer: This will allow atomic bonds near the

surface to relax towards their equilibrium lengthened orientation. The basic

energetic competition in this process is between the surface energy of the

epitaxial layer (which is increased by roughness) and the elastic energy (which

is reduced by roughness). Surface roughness can occur in any epitaxial layer

thickness.

(4) Misfit dislocation by plastic relaxation of strain: This strain relief mechanism

is via generation of an interfacial dislocation array, which allows the epitaxial

62

layer to relax the elastic strain energy towards its bulk lattice parameter. This

mechanism occurs only for layer thickness greater than the critical thickness and

it is the most common strain relaxation mechanism for epitaxially depositing

SiGe-based heterostructures on Si beyond the critical thickness. For pure Ge

grown on Si, the critical thickness is generally less than 5 nm.

As discussed above, growing Ge on Si mainly causes two major

problems: (1) the introduction of high densities of misfit-dislocations and

subsequently threading-dislocations in the epilayers, and (2) high surface

roughness during the epitaxial growth. High surface roughness causes

fabrication difficulties when devices scaling down. High threading-dislocation

densities can degrade device performance and compromise device reliability.

Misfit dislocations are often accompanied by surface roughening.

Modeling by Tersoff and LeGoues revealed that a temperature dependent critical

strain (order of 1%) exists in the SiGe/Si growth system, above which strain

relief is dominated by dislocation injection into roughened surfaces, and below

which dislocation injection into planar surface is favored [83]. This is consistent

with general experimental observations that roughness of Ge/Si epilayers is

greater for higher Ge concentration and temperatures. The purposed reason is

that strain relaxed by surface roughening reduces the driving forces for

63

dislocation introduction, or reduces the energetic barriers for dislocation

nucleation [84][85][86].

Misfit dislocation and threading dislocations

Misfit dislocations are line defects caused by strain relaxation, and are

typically confined to the interface between the epi-layer and the Si substrate.

They are left in the epilayers and must terminate at an interface with a free

surface, or form a loop. If the defect density is relatively low or dislocations are

less of interactions, misfit dislocations tend to terminate at the nearest free

surface, which is in general the growth surface. This produces threading-

dislocations as the by product of misfit dislocations to traverse the epitaxial

layer from interface to surface, as illustrate in Fig. 4.1. Threading dislocations

can reduce carrier lifetime, carrier mobility and compromise device reliability.

They are also found to be the primary factor contributing to the leakage current

of Ge photodiodes on Si.

64

Fig. 4.1: Illustration of misfit dislocation (AB) and threading dislocation (BC)

geometry at a GexSi1-x/Si interface [87].

4.2.2. Threading-dislocation and the dark current

In a p-n junction photodiode, the sources of leakage current are: (1)

diffusion current, (2) bulk generation current, (3) surface leakage current, and

(4) tunneling current [88]. Diffusion current is due to the diffusion of thermally

generated minority carriers into the depletion region from the surrounding

undepleted p and n regions. The diffusion current is the saturation current in an

ideal p-n junction diode [89]. Bulk generation current is due to defect assisted

thermal generation in the depletion region, which is proportional to the area of

the mesa [90]. Surface leakage is caused by carrier generation at the intersection

of the depletion region and the surface, which is proportional to the perimeter of

A B

C

SU

EP h

65

the mesa [91] and can be reduced by proper surface passivation. Tunneling

current is due to band-to-band transitions or trap-assisted transition at high

electric field and is typically the dominant leakage current at a low temperature

or a high voltage, particularly for narrow bandgap semiconductors.

Surface leakage can be a significant dark current mechanism. However,

it can be greatly reduced by surface passivation. In photodiodes fabricated on Ge

epitaxially grown on Si, bulk generation is the dominant leakage current due to

high threading dislocations density. Ross reported an increase in dark current by

increasing the misfit dislocations by comparing metastable SiGe p-n junction

diodes with different threading dislocation density [92]. Kozodoy showed that

threading dislocation in GaN p-n junction diodes cause an increase in leakage

current and suggested the increase in leakage current can be associated with the

carrier generation at defect states related to threading dislocation [93]. In

addition, studies of the deep-level transient spectroscopy (DLTS) of dislocations

in Si and SiGe materials have revealed a linear correlation between dislocation

density and deep-trap density [94][95]. The cores of threading dislocations are

sites for deep traps that enhance both minority carrier generation and

recombination. Giovane and co-workers [96] showed that the contribution of

threading dislocations on the leakage current can be estimated by knowing the

number of traps per length of threading dislocations (NTD) and calculating the

defect state density (NT) using the following formula:

66

DTDT NNN ⋅= ; (1)

where NT is the defect state density, NTD is the number of traps per length of

dislocations, and ND is the dislocation density. When the capture cross section

(σn) of the defect states related to threading dislocations is known, the minority

carrier lifetime can be estimated by:

TDDthn NNv ⋅⋅⋅=

στ 1

; (2)

where vth is the carrier thermal velocity. With the estimation of minority-carrier

lifetime, the generation current density due to carrier generation at dislocation-

related defect states can be estimated by:

TDDthnii

gen NNvWnqWnqJ ⋅⋅⋅⋅⋅⋅=⋅⋅

= στ ; (3)

where ni is the intrinsic carrier concentration. For Ge and SiGe material system,

studies of dislocations in Si and SiGe materials showed that NTD = 106 cm-1, σn =

4x10-12 cm2, vth = 1.17x107 cm/s, and ni = 2.4x1013 cm-2 at 300 K. Given that the

threading dislocation density ND is 107cm-2 from our typical Ge epitaxial layers,

and the depletion width is 2 μm, the estimated generation current is 720 mA/cm-

2. This value is generally higher than the measured dark current and it sets the

upper limit for the dark current in a photodiode under this dislocation density.

67

4.2.3. Methods of dislocation reduction

Since threading dislocations are the primary source of the high leakage

current at room temperature, it is crucial to reduce the threading dislocation

density during growth. Many methods have been used to reduce the threading

dislocation densities during Ge epitaxial growth. Previously, relaxed Ge has

been grown by an UHV-CVD system on Si with thick graded Si1-xGex buffer

layers. The Ge concentration was continuously graded over 10μm. TEM

measurements showed that most of the dislocations were confined to the graded

buffer layer [97]. However, this method is not suitable for monolithic integration

with Si CMOS owing to the large thickness of the buffer region. Another

method of epitaxially growing Ge on Si has been reported by Luan et al. [98]. A

50-nm-thick low temperature Ge buffer layer was grown at 350 ºC, followed by

a high temperature (~600 ºC) Ge layer. In-situ cyclic annealing was performed

subsequently to reduce the dislocation density in the Ge layer. The low

temperature Ge buffer layer facilitated stress relief in the first few hundred

angstroms, and the overlying Ge layer exhibited significant reduction in

dislocation density. Furthermore, cyclic annealing enhanced the migration of

threading dislocations to further reduce the number of dislocations. The effect of

thermal annealing and the utility of a low temperature Ge buffer layer in

reducing the threading dislocation density have been further studied by Halbwax

et al. [99][100]. They reported that (1) a two hour anneal at 750 ºC can achieve

68

the same quality Ge film as a ten cycle anneal between 780 ºC and 900 ºC [99]

and (2) the low-temperature buffer layer has to be thicker than 27 nm to

effectively reduce the threading dislocation density in the Ge layer [100].

Reported photodetectors based on these materials can achieve dark current

density as low as 12 mA/cm2 at 1 V reverse bias for a 2.35-μm-thick Ge layer on

Si [101].

Recently, a method of utilizing two thin SiGe layers as intermediate

buffer prior to the growth of Ge in a UHV-CVD system has been reported [102].

By adjusting the SiGe compositions, when the stress field around a

heterojunction interface is strong enough, the dislocations can be bent and

traverse along the interface, thus reducing the threading dislocation density in

Ge. The stress field can be altered by adjusting the composition of the SiGe

buffer layer. The surface roughening caused by the non-uniform stress field can

block the dislocations as well [103]. From our experiments, this growth method

is more controllable than the other techniques. Hence this technique was studied

systematically in order to reduce the dark current in a photodiode.

4.3. Experiments

69

The epitaxial growths were carried out in an UHV-CVD system as

described in Chapter 2. The substrate was n-type Si with resistivity in the range

of 0.008 - 0.02 ohm-cm. Four samples were grown to study the SiGe buffer

layers. The first sample (sample A) was grown by depositing a 50-nm-thick Ge

layer at 350 ºC, followed by a 1-μm-thick Ge film at 600 ºC. The second

sample (sample B) was grown with 0.72-μm-thick Si0.50Ge0.50, and 0.46-μm-

thick Si0.40Ge0.60 buffer layers at 550 ºC preceding growth of a 2.6-μm-thick Ge

layer, as shown in Fig. 4.2. For sample B, immediately after growing each

individual buffer layer, the wafer was in situ annealed at 750 ºC for 15 minutes

to reduce the dislocation density. The third wafer (sample C) and the fourth

wafer (sample D) were used to study the effect of annealing the SiGe buffer

layers. Both samples have 0.18-μm-thick Si0.58Ge0.42, and 0.28-μm-thick

Si0.42Ge0.58 buffer layers grown at 500 ºC and 0.2-μm-thick Ge layers. In

sample C none of the layers were annealed. For sample D each SiGe buffer layer

was annealed at 750 ºC. Table 1 lists the growth conditions for these four

samples.

The surface morphologies of the films were checked using AFM in

contact mode. The composition of the Ge in the SiGe buffer layer was

characterized using secondary ion mass spectrometry (SIMS) and verified by X-

ray Diffraction (XRD). Cross-sectional TEM was used to image dislocations in

70

samples A and B. Mesa-structure photodiodes were fabricated as described in

chapter 2.

Ge 520ºC (2.62μm)

LT-Ge 350ºC (50nm)

Si0.40Ge0.60 570ºC (720nm) 850ºC Anneal

Si0.50Ge0.50 570ºC (460nm) 850ºC Anneal

Si buffer 700ºC (50 nm)

Si Substrate

Fig. 4.2: Film structure and growth conditions of sample B.

Table 4.1. Summary of growth condition for samples A, B, C and D.

1st SiGe buffer layer 2nd SiGe buffer layer Ge layer

Composition* Thickness Anneal* Composition* Thickness Anneal* Thickness

A - - 1.0 μm

B Si0.50Ge0.50 0.72 μm 15 min Si0.40Ge0.60 0.46 μm 15 min 2.6 μm

C Si0.58Ge0.42 0.18 μm - Si0.42Ge0.58 0.28 μm - 0.2 μm

D Si0.58Ge0.42 0.18 μm 15 min Si0.42Ge0.58 0.28 μm 15min 0.2 μm

* SiGe buffer layers are grown at 550 ºC, annealing condition is at is 750 ºC.

71

4.4. Material Characterization

4.4.1. AFM

The surface morphologies of the layers in samples A and B are shown in

Fig. 4.3(a) - 4.3(e). Figure 4.3(a) shows the Ge surface of sample A. The surface

roughness root-mean-square (rms) is 1.4 nm in a 30 μm x 30 μm scanning area.

Figure 4.3(b) shows the surface of the first SiGe buffer layer in sample B before

annealing. It clearly shows the cross hatch patterns on the as-grown SiGe

surface. These patterns come from the stress relaxation through 111

dislocation glide planes intersecting the (100) interface [104]. Figure 4.3(c)

shows the same SiGe layer after a 750 ºC anneal for 15 minutes. Islands formed

along with the periodic patterns on the film and the surface roughness increased.

Figure 4.3(d) shows the surface after the second SiGe growth and anneal.

Periodic cross hatch islands are arranged on the film, and the surface roughness

escalated compared to the first SiGe layer. Figure 4.3(e) shows the final Ge

surface, where coherent 3-D Ge islands anisotropically formed overlaying the

SiGe periodic patterns. The surface roughness rms of each stage was 0.7 nm, 2.6

nm, 3.2 nm, and 3.4 nm, respectively. The evolution of each SiGe and Ge layer

growth step shows increased island formation, a known strain field relaxation

mechanism during growth when the lattice mismatch is large. Our experiments

72

indicate that the surface roughness of the Ge does not directly relate to a vertical

p-n structure photodiode performance.

rms = 1.4nm

(a)

Rms = 0.7 nm30x30 μm2

(b)

Rms = 2.6 nm

(c)

(d)

rms = 3.4 nm

(e)

rms = 3.2 nm

73

Fig. 4.3: (a) AFM surface morphology of sample A; (b) Si0.50Ge0.50 surface of

sample B before annealing, (c) the Si0.50Ge0.50 surface of sample B after 750 ºC

15 minute anneal, (d) surface of Si0.40Ge0.60 buffer in sample B after 750 ºC 15

minute anneal, and (e) sample B Ge surface morphology.

4.4.2. Cross-sectional TEM

Cross-sectional TEM micrographs of samples A and B are shown in Fig.

4.4(a) and 4.4(b), respectively. The TEM of sample A shows that many sessile

pure-edge (90º) threading dislocations are generated from the Si/Ge interface,

and propagate to the Ge surface. It has been reported that films experiencing

high temperature growth have more sessile pure-edge threading dislocations

than those grown at low temperature. One explanation for the formation of pure-

edge dislocations is the annihilation of the 60º (glissile) dislocation during high

temperature growth [105]. In sample B, the TEM picture shows high dislocation

density in the SiGe buffer layers and a significantly reduced threading

dislocation density in the Ge layer. This is due to the fact that many threading

dislocations are bent or terminated in the SiGe layers and their heterojunction

interfaces.

74

Fig. 4.4: TEM micrographs of (a) sample A, (b) sample B.

4.5. Device Characterization and discussion

4.5.1. I-V characteristics

The current characteristics of photodiodes fabricated in these Ge on Si

layers are shown in Fig. 4.5. The dark current densities decreased from 0.179

Ge

Si (a)

Si

Ge

Si Dislocations

(b)

75

A/cm2 and 1.118 A/cm2 for sample A to 3.6 mA/cm2 and 8.4 mA/cm2 for

sample B at 1 V and 5 V reverse bias, respectively. The dark current of Ge on Si

photodiodes was reduced over an order of magnitude by incorporating the two

SiGe buffer layers.

Fig. 4.5: Current density versus voltage characteristics for sample A and

sample B.

4.5.2. Effect of annealing

The effect of annealing has also been investigated by comparing the dark

currents of photodiodes fabricated from samples C and D. Fig. 4.6 shows that

dark current associated with sample D was over one order of magnitude lower

than sample C, an indication of the benefit of annealing the SiGe buffer layers.

Voltage (V)-10 -8 -6 -4 -2 0 2D

ark

Cur

rent

Den

sity

(A/c

m2 )

10-4

10-3

10-2

10-1

100

101 w/o SiGe

with SiGe

76

Annealing has been shown to help dislocations glide [106]. During annealing of

each SiGe layer at high temperature, dislocations can move and be annihilated,

thus reducing their densities in the SiGe layers. It follows that the dark current

would be reduced as well.

Fig. 4.6: Current density verus voltage characteristics for sample C and sample D.

4.5.3. Low temperature IV characteristics

It is well known that defects and dislocations are generation centers that

cause leakage currents in minority carrier devices [107]. Low temperature

measurement can provide the information about activation energy in a device,

Voltage (V)-10 -8 -6 -4 -2 0 2

Dar

k C

urre

nt D

ensi

ty (A

/cm

2 )

10-4

10-3

10-2

10-1

100

101

102

Annealed

Not annealed

77

and giving an insight of the dark current. The dark current versus voltage was

measured from 136 K to 400 K and the extracted activation energies for samples

A and B were 0.38 eV and 0.31 eV (Fig. 4.7), respectively. Both activation

energies are close to half the bandgap of Ge. This suggests that, for both films at

room temperature, the dark current arises from the generation of the minority

carriers in the Ge layer. It appears that even though the SiGe buffer layers had

much higher dislocation densities than the Ge layer in sample B, dislocations in

the Ge film are still the dominant mechanism contributing to the dark current.

Therefore the concern on the dislocation in Si/Ge as the major source

contributing to the dark current is excluded. On the other hand, it approves that

SiGe buffer layers can effectively reduce the dark current in a photodiode.

Fig.

4.7: Arrhenius plot of sample A and sample B.

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

20 40 60 80 1001/kT (eV)

Cur

rent

(A)

-2V

0.38eV

240K400 136

0.31eV

0.06eV

0.12eV

Sample B ♦ Sample A

78

4.6. Conclusion

This chapter has demonstrated the effectiveness of SiGe buffer layers in

reducing the dark current of Ge photodetectors grown on Si substrate. By

inserting SiGe buffer layers before the Ge epitaxial growth, the threading

dislocation density in the Ge film can be greatly reduced with a concomitant

decrease in dark current. Measurements of the dark current versus temperature

indicated that the dark current is dominated by generation current in the Ge

layer.

79

Chapter 5

High performance Ge Photodetector on Si

5.1. Overview

This chapter discusses electrical and optical characteristics of

photodetectors fabricated on the Ge films utilizing the growth technique

discussed previously. Photodetectors are characterized in terms of I-V, C-V,

responsivity, and RF response. A backside-illuminated Ge-on-Si photodiode

with totaling 1.2-μm-thickness SiGe buffers was fabricated and achieved ultra-

low dark current. In order to improve the speed of the photodetectors, thinner

SiGe buffer layers were incorporated, and the 20-μm-diameter photodetectors

achieved 21 GHz bandwidth at 10 V reverse bias. Table 1 summarizes the

sample structures used for experiments in this chapter:

Table 5.1. Summary of structures for samples A, B, and B2.

A B B2

1st SiGe - Si0.50Ge0.50 0.72 μm Si0.58Ge0.42 0.18 μm

2nd SiGe - Si0.40Ge0.60 0.46 μm Si0.42Ge0.58 0.28 μm

Ge layer 1.0 μm 2.6 μm 1.7 μm

80

5.2. Ultra low dark current PD

From the discussions in the last chapter, it is clear that two SixGe1-x

buffer layers preceding the Ge growth can effectively reduce the dislocation

density in the Ge layer, and therefore reduce the dark current.. In this section,

the photodiodes fabricated on sample B in chapter 4 are characterized. Dark

current as low as 1.07 μA is achieved at 10 V reverse bias for 24-μm-diameter

mesa devices. At 1.3 μm wavelength, the responsivity is 0.37 A/W at 0 V and

0.57 A/W above 2 V reverse bias. The 3 dB bandwidth is 8.1 GHz at a reverse

bias of 10 V.

5.2.1. Experimental procedure

The Ge epitaxial growth was introduced in chapter 4. In short, prior to

the growth of the Ge layer, two different composition SiGe buffer layers were

grown at 550 °C. The buffer region consisted of 0.72-μm-thick Si0.50Ge0.50 and

0.46-μm-thick Si0.40Ge0.60 layers. Immediately after growing each buffer layer,

the wafer was in-situ annealed for 15 minutes at 750 °C to further reduce the

dislocation density. Then the reactor temperature was set to 550 °C and a 2.6-

μm-thick Ge layer was deposited. Secondary ion mass spectroscopy (SIMS)

showed that impurity densities in the heteroepitaxy SiGe and Ge films were

below the detection limits (Fig. 5.1(a)). Backside-illuminated mesa-structure

81

photodiodes were fabricated as described in Chapter 2. Fig. 5.1(b) shows the

schematic of the device structure.

n+- Si substrate

Si0.50Ge0.50

Ge

Si0.40Ge0.60

Al P-

Al N-Contact

(b)

Depth (μm)0 1 2 3 4

conc

entr

atio

n (a

tom

s/cc

)

1014

1015

1016

1017

1018

1019

1020

1021

Ge

Con

cent

ratio

n (%

)

0

20

40

60

80

100

O

P

B Si

Ge

(a)

82

Fig. 5.1: (a) Secondary ion mass spectroscopy of the Ge epitaxial film with 1-

μm-thick SiGe buffer layers; (b) Cross sectional schematic of the Ge on Si

photodiode structure.

5.2.2. Measurement results and discussion

(a) Current Voltage Characteristics IV

Fig. 5.2(a) shows the current voltage curves for 24-μm, 48-μm and 100-

μm-diameter mesas. For 24μm-diameter devices, the dark current is 0.06 μA,

0.27 μA and 1.07 μA at reverse biases of 1 V, 3 V and 10 V, respectively. Fig.

5.2(b) shows the dark current versus mesa diameter. The square symbols on the

dash-dotted line show the calculated dark current including contributions from

bulk leakage current (proportional to area) and surface leakage current

(proportional to diameter) which follow the equation:

22

2

2 dJdJI sbdark ππ ⋅+⎟⎠⎞

⎜⎝⎛⋅= ; (1)

The triangle symbols on the dashed line were calculated assuming only

bulk leakage current. At 1 V reverse bias, the dark current can be fit to the

quadratic curve very well, which indicates that bulk leakage dominates. At high

bias voltage, the surface leakage current becomes more prominent, but the bulk

component still dominates. It appears, therefore, that the dark current is mainly

83

attributable to the defects in the epitaxial layer. The dark current density is 12

mA/cm2 at -1 Vand 28mA/cm2 at -2 V. This is lower than a heterojunction

photodetector fabricated without the SiGe buffer layers [108], but higher than

devices fabricated on optimized graded buffer layers [109].

-10 -8 -6 -4 -2 0 210-9

10-8

10-7

10-6

10-5

10-4

10-3

Voltage (V)

Dar

k C

urre

nt (A

)

100 μm-diam48 μm-diam

24 μm-diam

(a)

-20 0 20 40 60 80 100 120 140 1600

1

2

3

4

5

6

Diameter (μm)

Cur

rent

(μA

)

(b)

Bias=-2V

Bias=-1V

Measured dark current Calculated based onJtotal=Jbulk×π(d/2)2

+Jsurface×2πdCalculated based onJtotal=Jbulk×π(d/2)2

84

Fig. 5.2: a) I-V characteristics of Ge mesa diodes of different diameters. Dark

circle and solid line: 24 μm; dark square on solid line: 48 μm; dark triangle on

solid line: 100 μm. b) dark current versus area at 1 V and 2 V reverse bias; circle

on solid line: measured data; square on dash dotted line: fit from bulk

leakage/area and surface leakage/diameter; triangle on dashed line: fit to square

of the diameter. At –1 V, the bulk current density is 12 mA/cm2, the surface

current density is 0.318 μA/cm; and at –2 V, the bulk current density is 28

mA/cm2, the surface current density is 0.7 μA/cm.

(b) Responsivity

The responsivity was measured by illuminating through the substrate

with a 1.3 μm laser source. After deposition of a 2000 Å SiO2 anti-reflecting

coating, 88% of the incident light is estimated to be transmitted into the device.

The measured responsivity is 0.37 A/W at 0V and 0.57 A/W above 2 V reverse

bias (Fig. 5.3). Fig. 5.3 also shows the responsivity for frontside illumination

and it is lower than that of the backside. This will be discussed in detail in the

next section.

85

Fig. 5.3: Responsivity for backside illumination and frontside illumination.

(c) Capacitance characteristics

Capacitance-voltage characteristics were measured using an LCR bridge

at 1 MHz. The capacitance per unit area is shown in Fig. 5.4(a) with the

calculated depletion width shown in Fig. 5.4(b). At 4 V reverse bias, the

depletion region reaches ~1 μm from the Si/Ge interface, corresponding to the

interface between the Si1-xGex buffer regions and the thick Ge layer in the

photodiode. This is observed as a kink in the CV curve in Fig. 5.4(a). Above 6

V reverse bias, the depletion width penetrates into the Ge layer and stops at ~2

00.10.20.30.40.50.60.70.80.9

1

0 2 4 6 8 10

Voltage (V)

Res

pons

ivity

(A/W

)

Backside IlluminationFrontside Illumination

0.57A/W

0.46A/W

86

μm from the Si/Ge interface. As discussed in chapter 3, the structural defects in

Ge epitaxial layers result in shallow acceptor states near the valence band edge,

which makes the film unintentionally p-doped [110][111]. The calculated

effective doping concentrations were 1015 and 1016 cm-3 at the second SiGe/Ge

interface and in the Ge film, respectively.

Reverse Bias (V)0 2 4 6 8 10

Cap

acita

nce

dens

ity (F

/cm

2 )

10-8

10-7

Reverse Bias (V)0 2 4 6 8 10

Dep

letio

n w

idth

( μm

)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

n+- Si substrate

p- Ge

p- Si1-xGex

p- Si1-yGey

SiGe buffer

87

Fig. 5.4: (a) Capacitance voltage characteristics, (b) extracted depletion width

versus voltage for sample B.

(d) RF characteristics

The impedances were measured with a network analyzer. For 100-μm-

diameter devices, at reverse bias of 3 V, the device capacitance is 1.4 pF and the

impedance is 18 Ω; the calculated RC limited bandwidth is 6.3 GHz. When

voltage is increased to 6 V reverse bias, the capacitance is 569 fF and the

calculated RC bandwidth is 17.6 GHz. For 24-μm-diameter devices, the

estimated RC bandwidth is 36 GHz at 3 V and 44 GHz above 6 V reverse bias.

RF response measurements were made using a network analyzer and a

1.3μm laser. The laser modulation frequency was swept from 130 MHz to

20GHz and the photodetectors were biased on-wafer using microwave probes.

As shown in Fig. 5.5(a) the bandwidths are 4.0 GHz at -3V, 6.0 GHz at -5 V, 7.8

GHz at -7 V and 8.1 GHz at -10 V for 24-μm-diameter devices. This indicates

that the device speed is limited by the carrier transit time. Fig. 5.5(b) shows that

the bandwidth saturates when biased > 5 V, which is consistent with the C-V

measurement in Fig. 5.4(a) and 4(b).

88

Fig. 5.5: (a): RF response for 24-μm-diameter devices at different biases.

Frequency (Hz)1e+8 1e+9 1e+10

RF

Ban

dwid

th (d

B)

-18

-15

-12

-9

-6

-3

0

3

λ=1.31 μm

-3dB BW = 8.1GHz

-10V

Voltage (V)0 5 10 15 20

-3dB

Ban

dwid

th (G

Hz)

0

2

4

6

8

10

4.0GHz

6.0GHz

7.8GHz 8.1GHz 8.1GHz

24μm-diam

89

5.3. The advantages of backside illumination

The responsivity and speed of the photodiodes discussed above were

measured by backside illumination. This has many advantages relative to front

side illumination because, in this structure, the p--n+ junction is located at the Si

and SiGe interface. Consequently, the electric field is high in the SiGe buffer

layers, and the Ge layer is not fully depleted. At -6V reverse bias, for example,

the edge of the depletion region extends 1μm into the Ge layer as depicted in

Fig. 5.4(b). As the absorption coefficients of the SiGe layers containing 55%

and 65% Ge are two orders of magnitude lower than that of 100% Ge, most

electron hole pairs are generated in the Ge [112]. For frontside illumination,

electron hole pairs are generated near the surface. Therefore electrons must

transit most of the Ge layer thickness in order to be collected. This reduces the

efficiency because many of the electrons recombine at the surface or before

reaching the depletion layer. For backside illumination, on the other hand,

electron hole pairs are generated in and close to depletion region. This results in

a higher collection efficiency [113]. It is worth noting that in both frontside and

backside illumination, electrons are the minority carriers in the SiGe and Ge

epitaxial layers. Many of the photogenerated electrons diffuse to the depletion

region. The excess hole density, on the other hand, decays within the dielectric

relaxation time, which is estimated as εε0ρp ~ 150 fs and can be neglected

compared to the electron transit time (~20 ps).

90

For backside illumination, the responsivity is enhanced by reflections

from the top contact which increases the optical path length effectively. This has

two beneficial effects. The thickness of the Ge can be reduced to decrease the

transit time for increased bandwidth and since the contact covers most of the top

of the mesa, the contact resistance will be reduced.

Since the electron hole pairs are generated in and close to depletion

region for back side illumination, the speed of the photodiode is improved as

well. This is reduced diffusion distance for the fact that electrons compared to

front side illumination.

5.4. Ultra high speed photodetectors

The bandwidth of the photodetectors described in the last section is

limited by the electron transit time in the thick SiGe and Ge layers. This

indicates that in order to improve the speed and responsivity of Ge

photodetectors on Si, thinner SiGe layers are needed. For this purpose, another

sample with 0.18-μm-thick Si0.58Ge0.42, and 0.28-μm-thick Si0.42Ge0.58 buffer

layers preceding a 1.7-μm-thick Ge layer was grown and obtained 0.62 A/W

responsivity and bandwidth of 21.5 GHz at 1.31 μm, resulting in an efficiency-

bandwidth product of 12.6 GHz.

91

5.4.1. Device structure

After depositing a 50-nm-thick Si buffer at 750 ºC to form a clean “epi-

ready” surface, 0.18-μm-thick Si0.52Ge0.48, and 0.28-μm-thick Si0.38Ge0.62 buffer

layers were grown at 500 ºC. Immediately after growing each individual buffer

layer, the wafer was in situ annealed at 750 ºC for 15 min to reduce the

dislocation density. Following the SiGe buffer layers, a 50-nm-thick Ge layer

was grown at 350 ºC. Finally the reactor temperature was increased to 600 ºC

and a 1.70-μm-thick Ge film was grown. TEM was used to observe the

dislocation distribution and estimate the threading dislocation density of the

epitaxial layers, and is shown in. Fig. 5.6. The Ge surface morphology was

analyzed by atomic force microscopy (AFM) in the tapping mode; the surface

root mean square roughness is 4.7 nm. Backside-illuminated mesa-structure

photodiodes were fabricated as described in chapter 2.

92

Fig. 5.6: Cross sectional TEM micrograph of the sample with two thin SiGe

buffer layers (sample B2).

5.4.2. Measurement and discussion

(a) Current Voltage characteristics

Fig. 5.7 shows the current voltage characteristics for 20-, 40-, and 100-

μm-diameter devices. For the 20-μm-diameter device, the dark current was 0.57,

1.25 and 2.41 μA at reverse biases of 1, 5 and 10 V, respectively. The dark

current versus area can be fit with a quadratic curve well, which indicates that

bulk leakage from generation-recombination dominates in the devices. The rapid

Si0.42Ge0.58

Ge

Si substrate

Si0.58Ge0.42

0.5 μm

Surface

93

increase in dark current from 0 - 0.1 V reverse bias results from the high density

of dislocations at the Si/SiGe interface and in the SiGe buffer layers. The defect

traps contribute to dark current as generation recombination centers [114][115].

Fig. 5.7: Current versus voltage characteristics of 20-, 40-, and 100-μm-

diameter Ge mesa diodes.

(b) Capacitance Voltage Characteristics

The capacitance per unit area is shown in Fig. 5.8 with the calculated

depletion width shown in the inset. From 0 - 0.1 V reverse bias, the depletion

width quickly penetrates into the Ge layer. Above 2 V reverse bias, the depletion

width extends deep into the Ge layer and stops close to the Ge surface. The

Bias (V)-10 -8 -6 -4 -2 0 2

Dar

k C

urre

nt (A

)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

100-μm-diam40-μm-diam20-μm-diam

94

calculated effective doping concentrations were 1016 cm-3 and 1015 cm-3 at the

second SiGe/Ge interface and in the Ge film, respectively.

Reverse Bias (V)0 2 4 6 8 10

Cap

acita

nce

dens

ity (F

/cm

2 )

10-8

10-7

Reverse Bias (V)0 2 4 6 8 10

Dep

letio

n w

idth

( μm

)0.0

.5

1.0

1.5

2.0

Fig. 5.8: Capacitance density - voltage curve on sample B2. Inset: Extracted

depletion width at different voltages from C-V curves.

(c) Responsivity

The responsivity was measured by illuminating through the silicon

substrate with 1.31 or 1.55 μm laser sources. Backside illumination was chosen

to increase the photo response and the speed of the devices [113]. The focused

spot diameter was 8μm which was smaller than the measured device sizes. 200

nm SiO2 was deposited as anti-reflecting coating. Fig. 5.9 shows the measured

95

responsivity at 1.31 μm. Without anti-reflecting coating, the responsivity

saturates at 0.46 A/W and with an anti-reflecting coating, the responsivity

increases to 0.62 A/W. At 1.55 μm, the responsivity is 0.28 A/W with an anti-

reflecting coating. The responsivity curves also indicate that the photogenerated

electron hole pairs can be efficiently collected when biased > 0.1 V.

Reverse Bias (V)0 2 4 6 8 10

Res

pons

ivity

(A/W

)

0.0

.2

.4

.6

.8

1.0

λ = 1.31μm with AR Coating

λ = 1.31μm without AR Coating0

0

0

0

0

0

0

0

Fig. 5.9: Responsivity for backside illuminated devices on sample B2, with

and without a SiO2 anti-reflective coating.

(d) RF response

The RF response was measured with an optical component analyzer at

1.31 μm and with a small-signal heterodyne method at 1.55 μm [116] (refer to

chapter 2). Figures 5.10(a) and 5.10(b) show the measured -3 dB bandwidth for

96

20- and 40-μm-diameter devices. At 1.31 μm, 3 dB bandwidths of 20.5 GHz and

21.5 GHz are achieved at 5 V and 10 V reverse bias, respectively, for the 20-

μm-diameter devices. For 40-μm-diameter devices, the bandwidths are 18.5

GHz and 19.5 GHz at 5 V and 10 V reverse bias, respectively. Fig. 5.10 (c)

shows the 3dB bandwidth versus bias for 20-μm-diameter devices at 1.31μm.

The bandwidth is above 18.3 GHz when reverse biased above 2V. At 1.55 μm,

the 20-μm-diameter device exhibits bandwidths of 17 GHz and 16 GHz at 5 V

and 10 V reverse bias, respectively. And for the 40-μm-diameter devices, the

bandwidth saturates at ~ 14 GHz for bias > 5 V. The measured bandwidth at

1.31 μm was higher than at 1.55 μm. This is due to the fact that the absorption

coefficient at 1.31 μm is higher than at 1.55 μm. Thus more electron-hole pairs

are generated close to the SiGe/Ge heterojunction. On average, electrons travel a

shorter distance to the electrode for 1.31 μm excitation than for 1.55 μm. Thus

the device speed at 1.31 μm was higher. For the 20-μm-diameter photodiodes at

1.31 μm the bandwidth-efficiency product is 12.6 GHz.

The RC limited bandwidth was estimated by measuring the S11

parameters with a network analyzer. The measured capacitance for the 20-μm-

diameter device is ~ 18 fF and the total resistance is ~ 90 Ω, yielding an

estimated RC-bandwidth of 62 GHz. The RC bandwidth for the 40-μm-diameter

97

device is 24 GHz, which indicates that the bandwidth for these two photodiodes

is transit-time limited.

Frequency (GHz)5 10 15 20 25

RF

Res

pons

e (d

B)

-15

-12

-9

-6

-3

0

3

6

20-μm-diam, -10V

20-μm-diam, -5V

40-μm-diam, -10V

40-μm-diam, -5V

Dot: Measured DataLine: Fitting curve

(b)

Frequency (GHz)5 10 15 20 25

RF

Res

pons

e (d

B)

-15

-12

-9

-6

-3

0

3

620-μm-diam, -10V

20-μm-diam, -5V

40-μm-diam, -10V

40-μm-diam, -5V

Dot: Measured DataLine: Fitting curve

1.31μm RF response

(a)

98

Fig. 5.10: (a) RF response at 1.31 μm for 20-μm-diameter and 40-μm-

diameter devices at 10 V and 5 V reverse bias, respectively. (b) RF response at

1.55 μm for 20-μm-diameter and 40-μm-diameter devices at 10 V and 5 V

reverse bias, respectively. (c) RF response verses reverse bias at 1.31 μm for 20-

μm-diameter devices.

5.5. Comparison of the Ge-on-Si photodiodes

Fig. 5.11 and Fig. 5.12 summarize the responsivity and the bandwidth,

respectively of samples B (thick SiGe buffer layers), B2 (thin SiGe buffer

layers) and sample A (no SiGe buffer layer) discussed in chapter 4. It is clear

Reverse Bias (V)0 2 4 6 8 10

-3dB

Ban

dwid

th (G

Hz)

0

5

10

15

20

25

20-μm-Diameter (c)

(c)

99

that the dark current can be greatly reduced by incorporating two SiGe buffer

layers, the bandwidth and the voltage at which the responsivity saturates can be

greatly improved by using thinner SiGe buffer layers. However, the dark current

of sample B2 was 0.57μA at 1 V reverse bias for a 20-μm-diameter device,

which was higher than that of sample B. Hence, the thinner SiGe buffer layers

sacrifice the device dark current to achieve higher bandwidth and saturation of

the responsivity at lower voltage compared to the thicker SiGe buffer layers. We

anticipate that by optimizing the thicknesses and compositions of the SiGe

buffer layers, the dark current, responsivity and speed of Ge photodiodes can be

further improved.

Voltage (V)0 1 2 3 4 5

Res

pons

ivity

(A/W

)

0.0

0.2

0.4

0.6

0.8

1.0Sample B2Sample BSample A

Fig. 5.11: Responsivity of sample A, sample B and sample B2.

100

Fig. 5.12: RF response at 1.31μm for a 20-μm-diameter device in sample A

(no SiGe buffer layer) and sample B2 (thin SiGe buffer layers) at 3 reverse bias,

and in sample B (thick SiGe buffer layers) at 10V reverse bias.

5.6. Conclusion

In this chapter, two Ge-on-Si photodetectors have been discussed. The

first backside-illuminated Ge-on-Si photodiode with two thick SiGe buffers was

fabricated and achieved dark current as low as 0.06 μA and 1.07 μA at reverse

bias of 1V and 10V for 24μm-diameter mesa devices. At wavelength of 1.3 μm,

the responsivity was 0.57 A/W above 2 V reverse bias, and the 3 dB bandwidth

was 8 GHz at reverse bias of 10V. In order to improve the speed, the second

photodiode with thinner SiGe buffer layers was introduced. The responsivity

Frequency (GHz)5 10 15 20 25

RF

Ban

dwid

th (d

B)

-12

-9

-6

-3

0

3

6

Sample B2

Sample B

Sample A

19.5GHz at -3V

19.5GHz at -3V

8.1GHz at -10V

101

was 0.62 A/W and 0.28 A/W at 1.31 μm and 1.55 μm, respectively. The

maximum 3 dB bandwidth of 20-μm-diameter devices was 21.5 GHz at 1.31 μm

and 17 GHz at 1.55 μm. This yields a bandwidth-efficiency of 12.6 GHz at 1.31

μm. In addition, the advantages of backside illumination have been illustrated

and measured characteristics of photodiodes discussed in this chapter and

chapter 4 have been presented.

102

Chapter 6

Planar Interdigitated Ge Photodiode on Si

6.1. Overview

This chapter discusses planar interdigitated p-i-n Ge photodiodes on Si.

The advantages of the planar structure are first discussed. This is followed by a

description of the planar p-i-n photodiode fabrication. The process sequence

includes ion implantation, metallization, and surface passivation in sequence.

Subsequently, the performance of the planar Ge p-i-n photodiodes is discussed

in terms of dark current, quantum efficiency, and 3-dB bandwidth. At a

wavelength of 1.3 μm, 0.8 A/W responsivity was achieved for p-i-n photodiodes

fabricated on 2.6μm-thick Ge material with two SiGe buffer layers.

6.2. Planar p-i-n photodiode structure and fabrication

6.2.1. Device structure

The photodiodes discussed in the previous chapters are vertical

structures in which the p-n junctions are formed at the Si/SiGe interfaces. A

disadvantage of this structure is that there is a high density of dislocations in the

SiGe layers in the high field region proximate to the p-n junction. This results in

103

increased leakage current and reduced photo responsivity. Also the vertical mesa

structure is not practical for monolithic integration because both device contacts

are not available from the top surface. The planar interdigitated structure solves

these problems by forming the junction and the contactson the Ge epitaxial layer

surface, which has fewer dislocations than the regions near the SiGe buffer

layers. The metal-semiconductor-metal (MSM) photodetector is a planar

structure that has been widely used owing to its relative ease of fabrication and

low capacitance. However, MSM photodetectors tend to exhibit low quantum

efficiency due to contact shadowing and high dark current compared to PINs. In

addition, the MSMs require a Schottky metallization process, which may not be

compatible with higher temperature Si CMOS process. The planar interdigitated

p-i-n photodiode has interdigitated p+- and n+- contacts formed on the top

portion of the epi-layer, which is relatively defect free [ 117 ][ 118 ]. Its

compatibility with Si CMOS technology makes this architecture a good

candidate for photodetectors in monolithic integrated Si based optical receivers

[119].

Previously, Oh reported interdigitated p-i-n photodiodes fabricated on

bulk Ge. These photodiodes achieved 67% quantum efficiency and 3 GHz

bandwidth at 1.3 μm. Interdigitated Ge-on-Si photodetectors were also

fabricated with a 10-μm-thick graded buffer layer [118]; bandwidths as high as

3.8 GHz were achieved and the quantum efficiency was 49% at 1.31 μm [120].

104

Recently, Dehlinger reported planar p-i-n photodiodes fabricated on Ge-on-

oxide Bandwidth of 29 GHz with the quantum efficiency of 34% at 850 nm, and

3.4% at 1.3 μm, respectively, was achieved [121].

In this chapter, planar interdigitated photodiodes fabricated on the Ge

epitaxial films, described in chapter 4, are discussed. Interdigitated n+ and p+

fingers were formed by ion implanting phosphorus and boron, respectively. The

device fabrication is discussed in this section. The electrical and optical

characteristics are compared in the following sections.

6.2.2. Device fabrication

Planar p-n interdigitated photodiodes

Schematic top and cross-sectional views of the interdigitated photodiode

fabricated on Ge are shown in Fig. 6.1. Initially, n+-fingers were formed using

ion implantation. Interdigitated patterns with various width and spacing were

defined by photoresist. The wafer was implanted with phosphorous at an energy

of 60 keV and a dose of 2 x 1015 cm-2 to form the n+-fingers [122]. After

implantation, the photoresist was removed and then ash-cleaned by reactive ion

etching (RIE) in the oxygen plasma at 400 mTorr 30 W for 10 minutes. Then the

p-finger patterns were defined by photoresist, another p+ ion implantation was

performed with boron at 35 keV energy and 2 x 1015 cm-2 dose. After the

implantation, another ash clean was performed. This was followed by an

105

activation anneal performed in a rapid thermal annealing furnace at 450 ºC for

1 minute. The annealing tube was purged with ultra-high purity nitrogen gas for

at least 5 minutes before annealing to minimize any undesirable oxidation.

Afterwards, a SiO2 layer (2000 Å) was deposited on top of the active area for

passivation and anti-refection coating. Another contact bar mask was used for

the ohmic contact at the end of n- and p-fingers. Finally, Al pads were formed

by thermal evaporation for high-speed measurement, thus completing the

fabrication process. Figure 6.2 shows the complete interdigitated p-i-n

photodetector having 1 μm finger width and 2 μm spacing with 51×64 μm2

active area.

Fig. 6.1: Planar Ge photodiodes with interdigitated p+- and n+-fingers

fabricated on Ge-on-Si substrate. (a) Top view and (b) Cross-sectional view

1 μm

AR coating

n+

Ge

n+

Light (λ = 1.3 μm)

holes electrons

Si (100) substrate

p+ p+n+-Ge Al

Ge

p+-Ge Al

Si0.58Ge0.42

Si0.42Ge0.58 0.28 μm

0.18 μm

(a) (b)

106

pn n

Fig. 6.2: Completed interdigitated PIN photodetector [123].

6.3. Interdigitated Ge photodiode characteristics

In this section, the electrical and optical characteristics are discussed for

the planar p-i-n photodiodes fabricated on the 1.7-μm-thick Ge film with two

thin SiGe buffer layers discussed in chapter 5 (sample B2). The IV, responsivity,

speed and photoresponse contour characteristics are presented.

6.3.1. IV characteristics

Figure 6.3 shows the current voltage curves for the 51×64 μm2 devices

with 5μm finger spacing and 2μm finger width for the p-i-n photodiodes. The

dark currents were 3.5 μA and 4.3 μA at reverse biases of 1 V and were 4.8 μA

107

and 5.6 μA at 5 V reverse bias, respectively. These values are about 20 times

larger than those obtained in interdigitated bulk Ge PINs [ 124 ]. The

measurement also shows that the dark current is not linearly proportional to the

device area as it is for the vertical photodiodes. The relatively high dark current

was due to the low bandgap energy, the high surface field in this structure, and

the absence of a good passivation material for Ge. For the interdigitated

structure described in this work, the electric field intensity at the surface is very

high and the Ge surface was not effectively passivated. The poor passivation for

the Ge surface induces point defects at the surface, which act as recombination

and generation centers of carriers, leading to surface leakage current [125].

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-10 -8 -6 -4 -2 0 2Voltage (V)

Cur

rent

(A)

p-i-n

108

Fig. 6.3: Current versus voltage characteristics of the planner interdigitated

device in 51x64 μm2 area.

6.3.2. Responsivity

Figure 6.4 shows the responsivity for the planar p-i-n photodiodes. For

this structure, there is no shielding of the incident light by the electrodes. The

200-nm-thick SiO2 surface passivation layer also acts as a partial AR coating,

which transmits 88% of the incident signal. The responsivity saturates at 0.65

A/W when biased > 1V.

0

0.2

0.4

0.6

0.8

1

0 2 4 6 8 10Voltage (V)

Res

pons

ivity

(A/W

)

p-i-n

Fig. 6.4: Responsivity of p-i-n photodiodes with 1μm finger width and 5μm

finger spacing.

109

6.3.3. Speed

RF response for planar photodiodes was measured using a lightwave

component analyzer and a 1.3 μm laser. The bandwidth of the PINs with 1 μm

finger width and 2 μm finger spacing was 1 GHz above 5 V as shown in Fig.

6.6. This is lower than the estimated transit-time-limited bandwidth (> 4 GHz).

Impedance measurements show that the capacitance of the device is 1pF and the

resistance was 15 Ω, which yields an RC bandwidth of 1 GHz. Like an MOS

structure, the large-area contact pad on top of the 200-nm-thick SiO2 dielectric

causes a large parasitic capacitance on the n+: Si substrate. In order to reduce

this parasitic capacitance, either the dielectric layer thickness or the substrate

doping concentration needs to be improved. Better performance can be achieved

by depositing the Ge/SiGe epitaxial layers on a moderately doped Si substrate.

At the same time, a thicker insolating layer can be used. For example, a 7-μm-

thick SU8 polymer layer deposited on the SiO2 dielectric layer can reduce the

contact pad capacitance from 1 pF to 100 fF, resulting in a significant

improvement in the RC limited bandwidth. With reduced parasitic capacitance,

the bandwidth can be further improved by reducing the finger spacing.

110

Fig. 6.5: RF response of the photodiode with 1μm finger width and 2μm finger

spacing.

6.3.4. Raster scan photoresponse contours

The spatial photo-response profiles of the planar interdigitated

photodiodes were measured by the raster-scanning technique. A 1.3-µm-

wavelength laser beam with a beam-waist ~5μm was scanned across the device,

generating photocurrent associated with the spatial position of the beam. The

photocurrent and beam spot location data are saved as three-dimensional plots of

photocurrent versus x- and y- position. Fig. 6.7 shows the spatial response of a

-54-51-48-45-42-39-36-33-30-27-24-21-18-15-12

-9-6-30

1.E+08 1.E+09 1.E+10Frequency (Hz)

RF

Res

pons

e (d

B) 1GHz

0.9GH

0.7GH

10V

1V

5V

7V

3V

111

51x64µm2-area device at 1 V and 5 V reverse bias. The interdigitated fingers are

clearly observed.

(a) (b)

Fig. 6.6: Raster scanned photoresponse for a planner p-i-n interdigitated

device at (a) 1V and (b) 5V reverse bias.

6.4. High responsivity planar photodiodes with thick Ge layers

The photodiodes discussed above were fabricated on a 1.7-μm-thick Ge

epitaxial layer with thin SiGe buffer layers (sample B2 in chapter 5). The

highest responsivity was 0.62 A/W. Planar photodiodes were also fabricated on

the 2.6-μm-thick Ge film discussed in chapter 5 (sample B in chapter 5). We

demonstrated that by utilizing a thicker Ge layer, higher responsivity was

X position

Y p

ositi

on

0 20 40 60 80 100 1200

10

20

30

40

50

60

70

80

1

2

3

4

5

6

7

8

9

10

11x 10

-65V Contour Plot1V Contour Plot

Fin

X position

Y p

ositi

on

0 20 40 60 80 1000

10

20

30

40

50

60

70

80

1

2

3

4

5

6

7

8

9

10

11x 10

-6

(c) (d)

112

achieved. The responsivity of the p-i-n photodiodes fabricated on the 2.6-μm-

thick Ge film is shown in Fig. 6.7, and achieved 0.83 A/W. For comparison, the

responsivity for the vertical photodiode fabricated on the same material is also

shown in Fig. 6.7. It is clear that the responsivity for the planar structure is much

higher than that of the vertical photodiodes because the planar photodiodes

operate near the epitaxial Ge surface, where fewer dislocations are formed and

more generated electron hole pairs are collected before recombination. Hence,

the collection efficiency of the planar structure is higher than that of the vertical

devices for the Ge-on-Si photodetectors.

0

0.2

0.4

0.6

0.8

1

0 2 4 6 8 10Voltage (V)

Res

pons

ivity

(A/W

) Planar PIN PD

Vertical PN PD

113

Fig. 6.7: Responsivity of the photodiode fabricated on the 2.6-μm-thick Ge

film for the planar structure with 1 μm finger width and 5 μm finger spacing,

and for the vertical structure.

6.5. Conclusion

In this chapter, the electrical and optical characteristics of planar

interdigitated p-i-n photodiodes have been presented. In the planar photodiode,

the dark current mainly originates from the surface generation, which results in

higher dark current; however, the collection efficiency is higher than that of

vertical structures. 0.83 A/W responsivity was achieved for a device fabricated

on a 2.6-μm-thick Ge grown on the thick SiGe buffer layers. A comparison of

these p-i-n photodiodes with previously reported results is in Table 1:

Table 6.1: Comparison of the planar and the vertical Ge photodiodes:

QE 3dB BW Reference

PIN on bulk Ge 67% 1.8GHz at 5V 1

PIN on thick SiGe 49% 3.5GHz at -3V 4

PIN on B 79% 1GHz at 5V This work Planar

PIN on B2 59% 1GHz at 5V This work

Device on B 54% 8.1GHz at 10V Chapter 5 Vertical

Device on B2 59% 21GHz at 10V Chapter 5

114

Chapter 7

Summary and future work: Process integration of Ge-on-Si with Si MOSFETs

7.1. Summary

This thesis presents research on Ge photodiodes grown on Si substrate. It

starts with the descriptions of the epitaxial growth techniques that I have used to

achieve high quality Ge films in an UHV-CVD system. It was shown that the Ge

epitaxial layers grown at high temperature (500 ºC – 700 ºC) had smoother

surfaces. The mechanisms that create dislocations in the Ge epitaxial layers have

been studied in order to achieve low dark current and high responsivity for the

photodiodes. It has been shown conclusively that the Ge epitaxial film quality

can be improved by incorporating SiGe buffer layers with appropriate

composition and thickness, and as a result, the photodiodes have achieved low

dark current, high responsivity, and high speed. Specifically, three types of Ge-

on-Si photodetectors were presented. The first backside-illuminated Ge-on-Si

photodiode with two thick SiGe buffer layers was fabricated and achieved dark

current as low as 0.06 μA and 1.07 μA at reverse bias of 1 V and 10 V,

respectively, for 24μm-diameter mesa devices. At wavelength of 1.3 μm, the

responsivity was 0.57 A/W above 2 V reverse bias, and the 3 dB bandwidth was

115

8 GHz at reverse bias of 10 V. In order to improve the speed, a second

photodiode structure with thinner SiGe buffer layers was fabricated. The

responsivity was 0.62 A/W and 0.28 A/W at 1.31 μm and 1.55 μm, respectively.

The maximum 3 dB bandwidth for 20-μm-diameter devices was 21.5 GHz at

1.31 μm and 17 GHz at 1.55 μm. This yielded a bandwidth-efficiency of 12.6

GHz at 1.31 μm. Finally, planar interdigitated photodiodes were studied and the

electrical and optical characteristics were compared with the vertical structure

photodiodes. In the planar photodiode, the dark current mainly originated from

surface generation, which resulted in higher dark current than the vertical

structures; however, the collection efficiency was higher than the vertical

structure. 0.83 A/W responsivity was achieved for the device with a 2.6-μm-

thick Ge layer grown on the thick SiGe buffer layers.

7.2. Future work

The long term goal of the project is to monolithically integrate Ge

photodetectors with Si optical receivers. With the current Ge photodetector,

monolithic integration of the Ge photodiode with a Si-based optical receiver can

proceed. In preparing for the future work, different factors need to be

considered: (1) Thermal budget: Ge has a melting point of 934 ºC which limits

the post-deposition process temperature to 600 ºC to avoid oxidization and

116

degradation of Ge film. (2) Process sequence: In previous research the Ge was

grown on Si directly in the UHVCVD system prior to other fabrication. But for

monolithic integration, the process sequence may need to be altered to achieve

the best device performance for both transistors and detectors.

7.2.1. Preliminary work

Photodiode and MOSFET monolithic integration

In the early stage of my research, the monolithic integration processes

for Ge photodiodes and Si MOSFETs was investigated to demonstrate the

integratibility of Ge on Si. Many traditional Si CMOS fabrication processes

need temperature higher than 900ºC, which degrades the Ge. The modified

fabrication processes should either decrease the thermal budget required for

fabricating Si MOSFETs or design a fabrication sequence where the Ge layers

are protected from the high temperature processes. The goal of this approach

will be to demonstrate the integration of Ge on Si photodetectors with Si CMOS

process technology.

The process that I developed started with a 0.7-μm-thick Ge film first

epitaxially grown at 400 ºC on Si using the UHVCVD system (the low

temperature film in chapter 3). The photodiode active region was first defined

117

and protected by a low temperature oxide (LTO). Then the Ge was etched with

H2O2 until all the Ge film on the Si was removed since H2O2 does not attack the

Si surface. The final Si roughness was in the range of 0.5nm which is

comparable to the fresh Si surface. This process limited the choice of material

and only Ge films directly grown on Si can be used. After cleaning the wafer, a

50Å-thick HfO2 film was deposited in a CVD chamber and a 1500Å-thick TaN

gate metal was sputtered on the Si surface. Afterward, the source/drain (S/D)

patterns were defined by a MOSFET ring mask, and RIE etched to remove the

metal gate and dielectric layer in the S/D region. The photoresist and the LTO

were then removed. This was followed by an ion implantation of phosphorus

with 50 keV energy and 2x1015 cm-2 onto the S/D region and the active regions

of the photodiodes. After the implantation, the wafer was cleaned and activated

at 600ºC for 1minute, which was estimated to achieve activation of 60% of the

dopant. The transistor region was protected by PECVD oxide prior to the

photodiode fabrication on the Ge active region. Finally, both the MOSFET S/D

contact region and the photodiode contacting layer were deposited by Al and

annealed at 450 ºC for 5 minutes to achieve ohmic contacts. The performance

of the photodiode is shown in Fig. 7.1. The dark current of the photodiode was

higher than the photodetector with SiGe buffer layers due to the direct epitaxy of

Ge on Si and the low responsivity is because of degradation of Ge film after ion

implantation and subsequent annealing. It can be anticipated that by using the

118

techniques discussed in chapter 3 and chapter 4, higher performance of the

photodiode can be achieved.

Fig. 7.1: (a) I-V characteristics of 50-μm-diameter photodiodes fabricated on

selective area growth. (b) Responsivity of the photodiode experienced the same

process with Si MOSFET.

The IV and CV characteristics of the MOSFETs were characterized as

well. Figure 7.2(a) and 7.2(b) shows the drain current characteristics versus gate

voltage and drain voltage. The drain current saturates at higher drain voltage due

to the high S/D resistance. This indicates that 600 ºC is not sufficient to achieve

good MOSFET performance.

Voltage (V)-5 -4 -3 -2 -1 0 1

Dar

k C

urre

nt (A

)

10-8

10-7

10-6

10-5

10-4

10-3100 μm

80 μm

50 μm

IV Characteristics

Voltage (V)0 1 2 3

Res

pons

ivity

(A/W

)

0.00

0.05

0.10

0.15

0.20

Responsivity

0.08A/W

λ=1.3μm

(a) (b)

119

In this preliminary work, monolithic integration has been demonstrated.

However, the performance of the photodiode and the MOSFETs are not

satisfactory due to insufficient activation of the S/D and thermal degradation of

the Ge. In the future work, a better process sequence needs to be designed.

Fig. 7.2: (a) Id-Vg and (b) Id-Vd characteristics of the MOSFETs in the

demonstrated chip.

Selective area epitaxial growth

It was clear that the previous integration design sacrificed the device

performance of both the photodiode and the MOSFET. The standard Si

fabrication needs high temperature processes, such as rapid thermal annealing,

field oxidation, gate oxidation, etc. Hence, it is more appealing to finish the high

VG (V)0.0 0.5 1.0 1.5 2.0

Gm

(μ S)

0

1000

2000

3000

4000

5000

I D ( μ

A/ μ

m)

10-5

10-4

10-3

10-2

10-1

100

101

VD (V)0.0 0.5 1.0 1.5 2.0

I D ( μ

Α/μ

m)

0

5

10

15

20

25

W/L = 807.97/2μm VG - VT = 0 --> 2.0 V

VDS = 100mV

2923μS

S.S=69.8mV/dec VT = 0.525V

(a) (b)

120

temperature process prior to the Ge epitaxial growth. Selective epitaxial growth

may be suitable for this application. In this preliminary work, devices have been

fabricated on selective epitaxial growth (SEG) of Ge layers on Si. Luan et al.

described the process of reducing the dislocation density by growing Ge on

patterned Si/SiO2 wafers [126]. The SiO2 sidewall can form a dislocation sink

and annihilate dislocations as they glide to the SiO2 sidewall. Additionally, for

further integration with electronic circuits, the SiO2 forms a protective layer over

the pre-fabricated Si preamplifier and related circuitry during the selective

regrowth of Ge on Si. A 500 nm Ge layer was selectively grown on a SiO2

patterned Si wafer. The threading dislocation density was then measured using

the etch pit density (EPD) method. Figure 7.3(a) shows the etch pits in the

selectively grown area. The estimated EPD was approximately 2x106 cm-2

which was much lower than full-surface Ge directly grown on Si. Photodiodes

were also fabricated on the SEG wafer. The detector dark currents were more

than two orders lower than that of Ge directly grown on Si without SEG (as

shown in Fig. 7.3(b)), but because the Ge layer thickness was only 500 nm, the

responsivity of the device was only 0.15 A/W. Further work needs to be done to

achieve high performance photodetectors fabricated on Ge films selectively

grown on Si.

121

Fig. 7.3: (a) Etch pits on a 50-μm-diameter selective- area- growth mesa. (b)

Blue line: I-V characteristics of 50-μm-diameter photodiodes fabricated on

selective area growth; red line: I-V characteristics of a 40-μm-diameter device

fabricated on full-surface Ge without selective area growth.

7.2.2. Future work

With the design consideration and preliminary work described above, the

following process is proposed for monolithic integration of Ge photodiode with

the preamplifier circuit. Figure 7.4 illustrates the cross-sectional view of the

integrated Ge photodiode and MOSFET profile. The process starts with a

moderately p-type doped Si substrate.

(1) The Si preamplifier circuit fabrication

120804-3Voltage (V)

-10 -8 -6 -4 -2 0 2

()

10-9

10-8

10-7

10-6

10-5

10-4

10-3

50μm-diam SEG

40μm-diam no SEG

122

1) Field oxide growth and transistor active region patterning

2) Gate oxide and poly gate deposition

3) MOSFET gate, S/D region, photodiode active region patterning.

4) Self aligned phosphorus ion implantation on the S/D and

photodiode active region; Dopant activation

(2) Photodiode fabrication

5) LTO protection of the preamplifier circuit, and the photodiode

active region patterning

6) Selective epitaxial growth of Ge in the photodiode activation

region using UHVCVD

7) N-type ion implantation of the epitaxial region for the Ge layer

8) Photodiode mesa etch

9) Photodiode surface passivation

(3) Final integration

10) LTO removal and Al metal deposition on the MOSFETs S/D and

Ge photodiode contacting layer as ohmic contact

11) 400 ºC forming gas and sintering.

p-Si substrate

Ge photodiode p+

i-Ge

n+

Si pre-amplifier

n+ n+ p+

123

Fig. 7.4: Schematics cross-sectional view of Ge photodiode integrated with Si

MOSFET.

124

Appendix: Publications

1. Zhihong Huang, J. Oh, and J. C. Campbell, “Backside Illuminated High Speed Ge Photodetector Fabricated on Si Substrate Using Thin SiGe Buffers,” Appl. Phys. Lett., vol. 85, pp.3286, 2004.

2. Zhihong Huang, J. E. Carey, M. Liu, X. Guo, E. Mazur, and J. C. Campbell, “Microstructured Silicon Photodetector,” accepted to Appl. Phys. Lett.

3. Zhihong Huang, N. Kong, X. Guo, N. Duan, M. Liu, A. L. Beck, S. K. Banerjee, and J. C. Campbell, J. C. Campbell, et al., “21 GHz Bandwidth Germanium on Silicon Photodiode Using Thin SiGe Buffers,” accepted to Selected Topics in Journal of Quantum Electronics.

4. Zhihong Huang, J. Oh, S. K. Banerjee, J. C. Campbell, “Effectiveness of SiGe buffer layers in reducing the dark currents of Ge-on-Si photodetectors,” unpublished.

5. X. Guo, A. L. Beck, Zhihong Huang, N. Duan and J. C. Campbell, “Performance of Low Dark Current 4H-SiC Avalanche Photodiodes with Thin Multiplication Layer,” submitted to IEEE Journal of Quantum Electronics.

6. Zhihong Huang, N. Kong, J. Oh, S.K. Banerjee, and J.C. Campbell, “Effectiveness of SiGe Buffers in Reducing Dark Currents of Ge-on-Si Photodetectors,” Electronic Material Conference, 2006.

7. Zhihong Huang, N. Kong, J. Oh, S. K. Banerjee, and J. C. Campbell, “Interdigitated Photodoide Fabricated on High Quality Ge with Thin SiGe Buffer Layers,” IEEE LEOS Summer Topical, 2006.

8. J. C. Campbell, J. Oh, and Zhihong Huang, “Si-Based Optical Receivers,” Proc. SPIE Int. Soc. Opt. Eng. 5703, 50, Feb. 2005.

125

9. J. C. Campbell, Z. Huang, N. Kong, J. Oh “Si and Si-Compatible Photodetectors,” 2nd International Conference on Group IV Photonics, Antwerp, Belgium, September, 2005.

10. J. C. Campbell, J. Oh, Zhihong Huang, and S. Csutak, “Si-based optical receivers,” Photonics West 2005: Optoelectronic Integrated Circuits IX, San Jose, CA, January 25-26, 2005.

11. J. C. Campbell, J. Oh, Z. Huang, S. Csutak, “Si-based optical receivers,” 2004 Joint International Meeting - 206th Meeting of the Electrochemical Society/2004 Fall Meeting of the Electrochemical Society of Japan, p1442, Oct 3-8, 2004.

12. Q. Mo, H. Chen, Zhihong Huang, et al., "Room-Temperature Continuous-Wave Operation of GaAs-Based Vertical Cavity Surface Emitting Laser Based on p-type GaAs/Air Mirror," Electro. Lett., vol. 39, pp.525-526, 2003.

13. H. Chen, Q. Mo, Zhihong Huang, et al. “Room-temperature CW operation of 980nm air-gap VCSELs,” Conference on Laser and Electro-Optics, pp.1139-1141, 2003.

14. D. G. Deppe, O. B. Shchekin, Q. Mo, H. Chen, Zhihong Huang,“Novel Semiconductor Laser Based on Quantum Dots” IEEE Laser & Electro-Optics Society, pp.167-168, Aug 2003.

15. Zhihong Huang, N. Kong, J. Oh, and J. C. Campbell, “Si based optical receivers,” MARCO IFC 2005 Annual Review, Oct. 2005

16. Zhihong Huang, J. Oh, and J. C. Campbell, “Ge-on-Si photodiodes in Si based optical receivers,” MARCO IFC / SPRC Workshop, Dec. 2004

17. Z. Huang, J. Oh, and J. C. Campbell, “Si based optical receivers,” MARCO IFC 2004 Annual Review, Oct. 2004

18. J. Oh, Z. Huang, and J. C. Campbell, “Si based optical receivers,” MARCO IFC 2004 Annual Review, Oct. 2003

126

Bibliography

[1] O. Qasaimeh, Z. Ma, P. Bhattacharya, E. T. Croke, “ Monolithically

Integrated Multicannel SiGe/Si pin-HBT photoreceiver Arrays,” IEEE J. of

Lightwave Tech., vol. 18, no. 11, pp.1548-1553, 2000.

[2] S. M. Csutak, J. D. Schaub; W. E. Wu, and J. C. Campbell, “High-speed

monolithically integrated silicon optical receiver fabricated in 130-nm CMOS

technology,” IEEE J. Lightwave. Technol., vol.20 , no9. pp.1724-1729, Sept.

2002.

[3] S. M. Csutak, J. D. Schaub; W. E. Wu, and J. C. Campbell, “High-speed

monolithically integrated silicon optical receiver fabricated in 130-nm CMOS

technology,” IEEE Photon. Technol. Lett., vol.14 , no. pp.516-518, Apr. 2002.

[4] R.E. Jones, S.G. Thomas, S. Bharatan, R. Thoma, C. Jasper, T. Zirkle, N.V.

Edwards, R. Liu, X.D. Wang, Q. Xie, C. Rosenblad, J. Ramm, G. Isella, H. von

Kanel, Jungwoo Oh, and J.C.Campbell, "Fabrication and Modeling of Gigahertz

Photodetectors in Heteroepitaxial Ge-on-Si Using a Graded Buffer Layer

Deposited by Low Energy Plasma Enhanced CVD," IEDM Tech. Dig.,pp. 793-

796,2002.

[5] J. D. Schaub, R. Li, C. L. Schow, J. C. Campbell, G. W. Neudeck and J.

Denton, "Resonant-Cavity-Enhanced High-Speed Si Photodiode Grown by

Epitaxial Lateral Overgrowth," IEEE Photon. Technol. Lett., vol. 11, pp.1647-

1649, 1999.

[6] S. Demiguel, X. Li, N. Li, H. Chen, J. C Campbell, W. Jian, and A. Anselm,

“Analysis of partially depleted absorber waveguide photodiodes,” J. Lightwav.

Techno., vol.23, Iss.8, pp. 2505-2512, 2005.

127

[7] H. Zimmermann, “Integrated Silicon Optoelectronics”, Springer series in

photonics, pp.145-159, 2000.

[ 8 ] J. I. Pankove, “Optical process in semiconductor,” Courier Dover

Publications Inc, New York, 1975.

[9] S. Richard, F. Aniel, and G. Fishman, “Energy-band structure of Ge, Si, and

GaAs: A thirty-band k·p method,” Phys.Rev. B, Vol.70, 235204, 2004.

[10] E. A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J.

Michel, Y.-J Mii, and B. E. Weir, “Totally relaxed GexSi1–x layers with low

threading dislocation densities grown on Si substrates”, Appl. Phys. Lett. Vol.

59, pp. 811-813,1991.

[11] M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A.

Fitzgerald, “Controlling threading dislocation densities in Ge on Si using graded

SiGe layers and chemical-mechanical polishing,” Appl. Phys. Lett., vol. 72, pp.

1718-1720, 1998.

[12] S. Iwanari and K. Takayanagi, Jpn. J. Appl. Phys. 30, L1978 (1991).aH. A.

van der Vegt, H. M. van Pinxteren, M. Lohmeier, E. Vlieg, and J. M.C Thornton,

Phys. Rev. Lett. 68, 3335 (1992).

[13] H. Nakahara and M. Ichikawa, Appl. Phys. Lett. 61, 1531 (1992).

[14] A. Sakai and T. Tatsumi, “Ge growth on Si using atomic hydrogen as a

surfactant.” Appl. Phys. Lett. 64, 52, 1994.

[15] M. Cope& M. C. Reuter, E. Kaxiras, and R. M.-Tromp, Phys. Rev. Lett. 63,

632 (1989).

[16] M. Horn-von Hoegen, F. K. LeGoues, M. Copel, M. C. Reuter, and R.

M.Tromp, Phys. Rev. Lett. 67, 1130 (1991).

128

[17] J. M. C. Thornton, A. A. Wiiliams, J. E. Macdonald, R. G. van Silfhout, J.F.

van der Veen, M. Finney, and Norris, J. Vat. Sci. Technol. B 9, 214-6 (1991).

[18] H. J. Osten, J. Klatt, G. Lippert, E. Bugiel, and S. Hinrich, Appl. Phys.L&t.

60, 2522 (1992).

[19] S. Higuchi and Y. Nakanishi, Surf. Sci. Lett. 254, LA65 (1991).

[20] K. Sakamoto, K. Kyoya, K. Miki, H. Matsuhata, and T. Sakamoto, Jpn. J.

Appl. Phys. 32, L204 (1993).

[21] M. Hornvonhoegen, “Surfactants-Perfect heteroepitaxy of Ge on Si (111).”

Appl. Phys. A-MATER 59 (5): 503-515, 1994.

[22] J. L. Liu, S. Tong, Y. H. Luo, J. Wan, and K. L. Wang, “High-quality Ge

films on Si substrate using Sb surfactant-mediated graded SiGe buffers,” Appl.

Phys. Lett., vol. 79, pp. 3431-3433, 2001.

[23] J. L. Liu, Z. Yang, and K. L. Wang, “Sb surfactant-mediated SiGe graded

layers for Ge photodiodes integrated on Si,” J. Appl. Phys., vol.97, 024504,

2006.

[24] J. C. C. Fan, B. Y. Tsaur, R. P. Gale, F. M. Davis, « Reducint dislocations

in semiconductors utilizing repeated thermal cycling during multistage epitaxial

growth,” US Patent 4632712 (1986).

[25] Hsin-Chiao Luan, Desmond R. Lim, Kevin K. Lee, Kevin M. Chen, Jessica

G. Sandland, Kazumi Wada, and Lionel C. Kimerling “High-quality Ge

epilayers on Si with low threading –dislocation densities” Appl. Phys. Lett.,

vol.75, pp.2909, Nov. 1999.

[26] M. Halbwax, D. Bouchier, V. Yam, D. Debarre, Lam H. NguyenHalwax,

and Y. Zheng, “Kinetics of ge growth at low temperature on Si(001) by

129

ultrahigh vacuum chemical vapor deposition,” J. Appl. Phys., vol.97, 064907,

2005.

[27] M. Halbwax, M. Rouviiere, Y. Zheng, D. Debarre, Lam H. Nguyen, J-L.

Cercus, C. Clerc, V. Yam, S. Laval, E. Cassan, and D. Bouchier, “UHV-CVD

growth and annealing of thin fully relaxed Ge films on (001) Si,” Optical

Material, vol.27, pp.822-826, 2005.

[28] G. Luo, T. –H. Yang, E. Y. Chang, C.-Y. Chang and K. Chao “Growth of

high-quality Ge epitaxial layers on Si (100)” Jpn. J. Appl. Phys,. Vol. 42, pp.

L517-L519, 2003.

[29] T. H. Yang, G. L. Luo, E. Y. Chang, Y. C. Hsieh, and C. Y. Chang,

“Interface-blocking mechanism for reduction of threading dislocations in SiGe

and Ge epitaxial layers on Si.100. substrates,” J. Vac. Sci. Technol. B, vol. 22,

no.5, pp.L17-L19, 2004.

[30] G.R. Booker, J.M. Titchmarsh, J. Fletcher, D.B. Darby, M. Hockly, and M.

AL-Jassim, “Nature, origin and effect of dislocations in epitaxial semiconductor

layers,” Journal of Crystal Growth, vol.45, pp. 407-425, 1978.

[31] S. Luryi, A. Kastalsky, and J. C. Bean, “New infrared detector on a silicon

chip,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1135-1139, 1984.

[32] S. B. Samavendam, M.T. Currie, T.A. Langdo, and E. A. Fitzgerald “High-

quality germanium photodiodes integrated on silicon substrates using optimized

relaxed graded buffers” Appl. Phys. Lett., vol73, pp.2125-2127, Oct 1998.

[33] J. Oh, J. C. Campbell, S. G. Thomas, S. Bharatan, R. Thoma, C. Jasper, et.

al, “Interdigited Ge p-i-n photodetectors fabricated on a Si substrate using

graded SiGe Buffer layers” IEEE Photon. Technol. Lett., vol.38, pp.1238, Sept.

2002.

130

[34] D. Buca, S. Winnerl, S. Lenk, S. Mantl, and Ch. Buchal, “Metal–

germanium–metal ultrafast infrared detectors,” J. Appl. Phys., vol. 92, pp.7599-

7581, 2002.

[35] M. Jutzi, M. Berroth, G. Wohl, M. Öehme, and E. Kasper, “Ge-on-Si

vertical incidence photodiodes with 39-GHz bandwidth,” IEEE Photon. Technol.

Lett., vol.17, no.9, pp.1510-1512, July 2005.

[36] L. Colace, G. Masini, G. Assanto, H. C. Luan, K. Wada, and L. C.

Kimerling, “Efficient high-speed near infrared Ge photodetectors integrated on

Si substrates,” Appl. Phys. Lett., vol. 76, pp. 1231-1233, 2000.

[37] S. Fama, L. Colace, G. Masini, G. Assanto, and H. C. Luan, “High

performance germanium-on-silicon detectors for optical communications,” Appl.

Phys. Lett., vol.81, no.4, pp.686-588, July 2002.

[38] G. Dehlinger, S. J. Koester, J. D. Schaub, J. O. Chu, Q. C. Ouyang, and A.

Grill, “High-speed germanium-on-SOI Lateral PIN photodiodes,” IEEE Photon.

Technol. Lett., vol.16, no.11, pp.2547-2549, Nov. 2004.

[39] J. Liu, D. D. Cannon, K. Wada, Y. Ishikawa, S. Jongthammanurak, D. T.

Danielson, J. Michel, and L. C. Kimerling, “Tensile strained Ge p-i-n

photodetectors on Si platform for C and L band telecommunications,” Appl.

Phys. Lett., vol.87, 011110, July 2005.

[40] O. I. Dosunmu, D. D. Cannon, M. K. Emsley, L. C. Kimerling, and M. S.

Ünlü, “High-speed resonant cavity enhanced Ge photodetectors on reflecting Si

substrates for 1550-nm operation,” IEEE Photon. Technol. Lett., vol.17, no.1,

pp.175-177, Jan. 2005.

131

[41] S.S. Murtaza, H. Nie, J C. Campbell, J.C. Bean, and L.J. Peticolas,

“Shortwavelength, high-speed, Si-based resonant-cavity photodetector,” IEEE

Photonics Tech. Lett., vol. 8, no. 7, pp. 927-929, 1996.

[42] D.C. Diaz, C.L. Schow, J. Qi, J.C. Campbell, J.C. Bean, and L.J. Peticolas,

“Si/SiO2 resonant cavity photodetector,” Appl. Phys. Lett., vol. 69, no. 19, pp.

2798-2800, 1996.

[43] J.C. Bean, J. Qi, C.L. Schow, R. Li, H. Nie, J. Schaub, and J.C. Campbell,

“High-speed polysilicon resonant-cavity photodiode with SiO2-Si Bragg

reflectors,” IEEE Photonics Tech. Lett., vol. 9, no. 6, pp. 806-808, 1997.

[44] G.W. Neudeck, J. Denton, J. Qi, J.D. Schaub, R. Li, and J.C. Campbell,

“Selectivve epitaxial growth Si resonant-cavity photodetector,” IEEE Photonics

Tech. Lett., vol. 10, no. 1, pp. 129-131, 1998.

[45] J. D. Schaub, R. Li, C. L. Schow, J. C. Campbell, G. W. Neudeck and J.

Denton, "Resonant-Cavity-Enhanced High-Speed Si Photodiode Grown by

Epitaxial Lateral Overgrowth," IEEE Photon. Technol. Lett., vol. 11, pp.1647-

1649, 1999.

[ 46 ] C. L. Schow, R. Li, J.D. Schaub, J.C. Campbell, “Design and

implementation of high-speed planar Si photodiodes fabricated on SOI

substrates,” IEEE Journal of Quantum Electron., vol. 35, pp. 1478 – 1482, 1999.

[47] J. D. Schaub, D. M. Kuchta, D. L. Rogers, Min Yang, K. Rim, S. Zier, and

M. Sorna, “Multi Gb/s, high-sensitivity all silicon 3.3V optical receiver using P-

I-N lateral trench photodetector,” Optical fiber Communication Conference and

Exhibits, OFC 2001, pp. PD19_1-PD_19-3, 2001.

132

[48] C. L. Schow, J. D. Schaub, R. Li, J. Qi, and J. C. Campbell, “ A

Monolithically Integrated 1-Gb/s Silicon photoreceiver,” IEEE Photon. Tech.

Lett., vol. 11, pp.120-121, 1999.

[49] R. Li, J. D. Schaub, S. M. Csutak, and J. C. Campbell, “A High-speed

Monolithic Silicon Photoreceiver Fabricated on SOI,” IEEE Photon. Tech. Lett.,

vol. 12, pp.1046-1048, 2000.

[50] S. M. Csutak., J. D. Schaub, W.E. Wu, and J.C. Campbell, “High-speed

monolithically integrated silicon optical receiver fabricated in 130-nm CMOS

technology”, IEEE Photon. Technol. Lett., vol. 14, pp.516-518, 2002.

[51] S. M. Csutak., J. D. Schaub, W.E. Wu, R. Shimer, and J.C. Campbell,

“CMOS-compatible high-speed planar silicon photodiodes fabricated on SOI

substrates”, IEEE J. Quantum Electron. vol. 38, pp.193 - 196, 2002.

[52] C. L. Schow, J. D. Schaub, R. Li, J. Qi, and J. C. Campbell, “ A

Monolithically Integrated 1-Gb/s Silicon photoreceiver,” IEEE Photon. Tech.

Lett., vol. 11, pp.120-121, 1999.

[53] R. Jones, S. Thomas, S. Bharatan, R.Thoma, C. Jasper, T. Zirkle, G.

Edwards, R. Liu, X. Wang, Q. Xie, C. Rosenblad, J. Ramm, G. Isella, H.von

Kanel, Jungwoo Oh, Joe Campbell, "Gigahertz photodetectors fabricated in

heteroepitaxial Ge-on-Si for use in integrated receivers," American Physical

Society, March Meeting, 2003.

[54] M. Jutzi, , M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-

Gb/s CMOS Optical Integrated Receiver With a Spatially Modulated

Photodetector,” IEEE Photon. Tech. Lett., vol.17, no.6, 2005.

133

[55] L. Schares, C. L. Schow, S. J. Koester, G. Dehlinger, R. Hohn, and F. E.

Doany, “A 17-Gb/s low-power optical receiver using a Ge-on-SOI photodiode

with a 0.13μm CMOS IC,” IEEE LEOS, 2005.

[56] S. Verdonckt-Vanderbroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P.

J. Restle, J. M. C. Stork, and J. B. Johnson, “ SiGechannel heterojunction

pMOSFETs,” IEEE Trans. Electron Devices, vol. 41, pp.90-100, 1994.

[57] M. L. Hammond, “Epitaxial silicon reactor technology-A review,” Solid

State Tech., pp. 159-164, 1988.

[58] J. F. O'Hanlon, “A User's Guide to Vacuum Technology,” John Wiley and

Sons, New York, 1980.

[59] B. S. Meyerson, “UHV/CVD Grwoth of Si and Si:Ge Alloys: Chemistry,

Physics, and Device Applicatins,” Proceed. Of the IEEE, vol. 80, No. 10, Oct

1992.

[60] B. S. Meyerson, “Low-temperature Si and Si:Ge epitaxy by ultrahigh-

vacuum/ chemical vapor deposition: Process fundamentals,”IBM J. Res.

Develop. Vol.44, No. 1-2, 2000.

[61] J. Oh, “Planar Ge Photodetectors on Si Substrates for Si/Ge-based Optical

Receivers,” Ph.D. dissertation, 2004.

[62] R. Hull, and J. C. Bean, “Germanium Silicon: Physics and Materials,”

Semiconductor and Semimetals, vol.56, Academic Press, 1999.

[63] E. Bauer, Z. Kristallogr. 110, 372 (1958).

[64] M. Copel, M. C. Reuter, Efthimios Kaxiras, and R. M. Tromp, “Surfactants

in epitaxial growth”, Phys. Rev. Lett., vol.63, pp.632, 1989.

134

[65] Z. Y. Zhang, and M. G. Lagally, Science, vol.276, pp.377, 1997.

[66] M .C. Oxturk, D. T. Grier, J. J. Wortman, M. A. Littlejohn, Y. Zhong, D.

Batchelor, and P. Russell, “Rapid thermal chemical vapor deposition of

germanium on silicon and silicon dioxide and new applications of Ge in ULSI

technologies,” Journal of Electronic Materials, vol.19, pp.1129, 1990.

[67] B. Cunningham, J. O. Chu, and S. Skabar, “Heteroepitaxial growth of Ge

on (100) Sibyultrahigh vacuum, chemical vapor deposition,” Applied Phys.

Letter., vol.59, pp..3547, 1991.

[68] M. Halbwax, M. Rouviere, Y. Zheng, D. Debarre, Lam H. Nguye, J-L.

Cercus a, C. Clerc, V. Yam, S. Laval, E. Cassan, D. Bouchier,” UHV-CVD

growth and annealing of thin fully relaxed Ge films on (001)Si,” Optical

Materials, vol.27, pp.822–826, 2005.

[ 69 ] S. Akbar, J. O. Chu, B. Cunningham, “Heteroepitaxial growth of

germanium on silicon by UHV/CVD,” US Patent 259918, 1993.

[70] E. P. Kvam and F. Namavar, “Reduced dislocation density in Ge/Si

epilayers,” Appl. Physic. Lett., vol.58, pp.2357, 1991.

[71] D. P. Malta, J. B. Posthill, R. J. Markunas, T. P. Humphreys, “Low-defect-

density germanium on silicon obtained by a novel growth phenomenon,” Appl.

Physic. Lett., vol.60, pp.844, 1992.

[72] D. P. Malta J. B. Posthill, R. J. Markunas, T. P. Humphreys, and N. R.

Parish, “Low-defect-density Ge on Si for large-lattice-mismatched

semiconductor integration and strain-engineered devices,” Materials Research

Society Symposia Proceedings, vol.263, pp.491, 1992.

135

[73] H. -C. Luan, “Ge Photodetectors for Si Microphotonics,” PhD. Dissertation,

MIT, 2001.

[74] J. Liu, D. D. Cannon, K. Wada, Y. Ishikawa, S. Jongthammanurak, D. T.

Danielson, J. Michel, and L. C. Kimerling, “Tensile strained Ge p-i-n

photodetectors on Si platform for C and L band telecommunications,” Appl.

Phys. Lett., vol.87, 011110, July 2005.

[75] M. Halbwax, D. Bouchier, V. Yam, D. Debarre, Lam H. NguyenHalwax,

and Y. Zheng, “Kinetics of ge growth at low temperature on Si(001) by

ultrahigh vacuum chemical vapor deposition,” J. Appl. Phys., vol.97, 064907,

2005.

[76] L. Di Gaspare, E. Palange, G. Capellini, and F. Evangelisti, “Strain

relaxation b pit formation in epitaxial SiGe alloy films grown on Si (001),” J.

Appl. Phys., vol.88, pp.120, July 2000.

[77] J. Oh, and J. C. Campbell, “Thermal Desorption of Ge Native Oxides and

the Loss of Ge from the Surface,” Journal of Electronic Materials, Volume

33, Number 4, 1 April 2004, pp. 364-367(4)

[78]Y. Ohmachi, T. Nishioka, and Y. Shinoda, “The heteroepitaxy of Ge on

Si(100) by vacuum evaporation,” J. Appl. Phys., vol.54, pp.5466, 1983.

[79] S. A. Ringel, P. N. Grillot, Proc. Mater. Res. Soc. Symp., vol.442, pp.313,

1997.

[80] J. Oh, “Planar Ge Photodetectors on Si Substrates for Si/Ge-based Optical

Receivers,” Ph.D. Dissertation, the University of Texas at Austin, 2004.

[81] C. A. King, J. L. Hoyt, and J. F. Gibbons, IEEE Trans. Electron Dev.,

vol.36, pp.2093, 1989.

136

[82] R. Hull, “Misfit strain and accommodation in SiGe Heterostructures,” in

Semiconductors and semimetals, R. Hull and J. C. Bean, Eds., “Germanium

Silicon: Physics and Materials,” Semiconductor and Semimetals, vol.56,

Academic Press, 1999.

[83] J. Tersoff, and F. K. LeGoues, Phys. Rev. Lett., vol.72, pp.3570, 1994.

[84] J. W. P. Hsu, E. A. Fitzgerald, Y. H. Xie, and P. J. Silverman, Appl. Phys.

Letter, vol.65, pp.344, 1994.

[85] A. G. Cullis, A. J. Pidduck, and M. T. Emery, Phys. Rev. Lett., vol75,

pp.2368, 1995.

[86] E. A. Fitzgerald, P. d. Kirchner, R. Proano, G. D. Petit, J. M. Woodall, D. G.

Ast, Appl. Phs. Lett., vol.52, pp.1496, 1997.

[87] R. Hull and J. C. Bean, Critical Review in Solid State and Material Science

vol.17, pp507, 1992.

[ 88 ] IT. P. Pearsall and M. A. Pollack, “Compound semiconductor

photodiodes,” in Semiconductors and semimetals, R. K. Williardson and A. C.

Beer, Eds., vol22, Lightwave communication technology, Part D, Photodetectors,

W. T. Tsang, vol. Ed. New York: Academic, 173, 1985.

[89] B. G. Streetman, S. K. Banerjee, Solid State Eelectronic Devices, 5th

Edition, Prentice Hall, 2000.

[90] S. M. Sze, Physics of semiconductor devices, 2nd Edition, New York:

Wiley, 1981.

[91] X. G. Zheng, “Long-wavelength, high-speed avalanche photodiodes and

APD Arrays,” PhD. Dissertation, 2003.

137

[92] F. M. ross, R. Hull, D. Bahnck, J. C. Bean, L. J. Peticolas, and C. A. King,

Appl. Phys. Lett. vol.62, pp. 1426, 1993.

[93] P. Kozodoy, J. P. Ibbetson, H. Marchand, P. T. Fini, S. Keller, J. S. Speck,

S. P. DenBaars, and U. K. Mishra, Appl. Phys. Lett., vol.73, pp.975, 1998.

[94] J. R. Patel, and L. C. Kimerling, Cryst. Res. Technol. Vol. 16, pp.187, 1981.

[95] P. N. Grillot, S. A. Ringel, E. A. Fitzgerald, G. P. Watson, and Y. H. Xie, J.

Appl. Phys, vol.77, pp. 7248, 1995.

[96] L. M. Giovane, H.-C Luan, A. M. Agarwal, and L. C. Kimerling,

“Correlation between leakage current density and threading dislocation density

in SiGe p-i-n diodes grown on relaxed graded buffer layers,” Appl. Phys. Lett.,

vol.78, pp.541, 2001.

[97] J. Oh, J. C. Campbell, S. G. Thomas, S. B., R. Thoma, C. Jasper, R. E.

Jones and T. E. Zirkle, “Interdigited Ge p-i-n photodetectors fabricated on a Si

substrate using graded SiGe Buffer layers,” IEEE Photon. Technol. Lett., vol.38,

no.9, pp.1238-1241, Sep.2002.

[98] Hsin-Chiao Luan, Desmond R. Lim, Kevin K. Lee, Kevin M. Chen, Jessica

G. Sandland, Kazumi Wada, and Lionel C. Kimerling “High-quality Ge

epilayers on Si with low threading –dislocation densities” Appl. Phys. Lett.,

vol.75, pp.2909, Nov. 1999.

[99] M. Halbwax, D. Bouchier, V. Yam, D. Debarre, Lam H. NguyenHalwax,

and Y. Zheng, “Kinetics of ge growth at low temperature on Si(001) by

ultrahigh vacuum chemical vapor deposition,” J. Appl. Phys., vol.97, 064907,

2005.

138

[100] M. Halbwax, M. Rouviiere, Y. Zheng, D. Debarre, Lam H. Nguyen, J-L.

Cercus, C. Clerc, V. Yam, S. Laval, E. Cassan, and D. Bouchier, “UHV-CVD

growth and annealing of thin fully relaxed Ge films on (001) Si,” Optical

Material, vol.27, pp.822-826, 2005.

[101] J. Liu, D. D. Cannon, K. Wada, Y. Ishikawa, S. Jongthammanurak, D. T.

Danielson, J. Michel, and L. C. Kimerling, “Tensile strained Ge p-i-n

photodetectors on Si platform for C and L band telecommunications,” Appl.

Phys. Lett., vol.87, 011110, July 2005.

[102] G. Luo, T. –H. Yang, E. Y. Chang, C.-Y. Chang and K. Chao “Growth of

high-quality Ge epitaxial layers on Si (100)” Jpn. J. Appl. Phys,. Vol. 42, pp.

L517-L519, 2003.

[103] G.R. Booker, J.M. Titchmarsh, J. Fletcher, D.B. Darby, M. Hockly, and M.

AL-Jassim, “Nature, origin and effect of dislocations in epitaxial semiconductor

layers,” Journal of Crystal Growth, vol.45, pp. 407-425, 1978.

[104] R. Hull, and J. C. Bean, “Germanium Silicon: Physics and Materials,”

Semiconductor and Semimetals, vol.56, Academic Press, 1999.

[ 105 ] H. -C. Luan, “Ge Photodetectors for Si Microphotonics,” PhD.

Dissertation, MIT, 2001.

[106] M. Tamura, Y. Yodo, T. Sayito, J. Palmer, “Rearrangement of misfit

dislocations in GaAs on Si by post-growth annealing,” Journal of Cristal growth,

vol.150, pp.654, 1995.

[107] L. M. Giovane, H. –C. Luan, A. M. Agarwal, and L. C. Kimerling,

“Correlation between leakage current density and threading dislocation density

139

in SiGe p-i-n diodes grown on relaxed graded buffer layers,” Appl. Phys. Lett.,

vol.78, pp.541, Jan. 2001.

[108] L. Colace, G. Masini, and G. Assanto “Efficient high-speed near-infrared

Ge photodetectors integrated on Si substrates” Appl. Phys. Lett., vol.76,

pp.1231-1233, Mar. 2000.

[109] S. B. Samavendam, M.T. Currie, T.A. Langdo, and E. A. Fitzgerald

“High-quality germanium photodiodes integrated on silicon substrates using

optimized relaxed graded buffers” Appl. Phys. Lett., vol73, pp.2125-2127, Oct

1998.

[110] Y. Ohmachi, T. Nishioka, and Y. Shinoda, J. Appl. Phys. 54, 5466 (1983)

[111] B. W. Sloop, and C. Tiller, “Electrical properties of epitaxial Ge films

deposited on (111) CaF2 substrate,” J. Appl. Phys., vol.38, pp.140-148, 1967.

[112] J. Humlicek, F. Lukes, and E. Schmidt, Handbook of optical constants of

solids II, Academic Press, New York, p.607, 1991.

[113] X. Li, S. Demiguel, N. Li, J.C. Campbell, D.L. Tulchinsky, and K.J.

Williams, “Backside illuminated high saturation current partially depleted

absorber photodetectors,” IEEE Electron. Lett., vol.39, pp.1466-1467, Oct. 2003.

[114] X. Guo, A. L. Beck, X. Li, and J. C. Campbell, “Study of reverse dark

current in 4H-SiC avalance photodiodes,” IEEE Journal of Quantum Electronics,

vol.41, no.4, pp.562-567, Apr. 2005.

[115] G. Karve, S. Wang, F. Ma, X. Li, and J. C. Campbell “Origin of dark

counts In0.53Ga0.47As/ In0.52Al0.48As avalanche photodiodes,” Appl. Phys.

Lett., vol.82, 063505 1-3, Feb 2005.

140

[ 116 ] X. Li, “High-Speed and High-Saturation-Current partially depleted

absorber photodetectors,” Ph. D Dissertation, The University of Texas at Austin,

2004.

[ 117 ] C. L. Schow, R. Li, J.D. Schaub, J.C. Campbell, “Design and

implementation of high-speed planar Si photodiodes fabricated on SOI

substrates,” IEEE Journal of Quantum Electron., vol. 35, pp. 1478 – 1482, 1999.

[118] J. Oh, S. Csutak, and J. C. Campbell, “High-Speed Interdigitated Ge PIN

Photodetectors,” IEEE Photon. Technol. Lett., vol. 14, pp. 369-371, 2002.

[119] S. M. Csutak., J. D. Schaub, W.E. Wu, and J.C. Campbell, “High-speed

monolithically integrated silicon optical receiver fabricated in 130-nm CMOS

technology”, IEEE Photon. Technol. Lett., vol. 14, pp.516-518, 2002.

[120] Z. Huang, N. Kong, and J. C. Campbell, “21 GHz Bandwidth Germanium

on Silicon Photodiode Using Thin SiGe Buffers,” unpublished.

[121] G. Dehlinger, S. J. Koester, J. D. Schaub, J. O. Chu, Q. C. Ouyang, and A.

Grill, “High-speed germanium-on-SOI Lateral PIN photodiodes,” IEEE Photon.

Technol. Lett., vol.16, no.11, pp.2547-2549, Nov. 2004.

[122] J. Oh, J. C. Campbell, S. G. Thomas, S. Bharatan, R. Thoma, and C.

Jasper, “Interdigited Ge p-i-n photodetectors fabricated on a Si substrate using

graded SiGe Buffer layers” IEEE Photon. Technol. Lett., vol.38, pp.1238, Sept.

2002.

[123] J. Oh, “Planar Ge Photodetectors on Si Substrates for Si/Ge-based Optical

Receivers,” Ph.D. dissertation, 2004.

[124]J. Oh, S. Csutak, and J. C. Campbell, "High-speed interdigitated Ge PIN

photodetectors," IEEE Photon. Technol. Lett. vol. 14, pp.369-371, 2002.

141

[125] Z. Huang, J. Oh, and J. C. Campbell, “Back-side-illuminated high speed

Ge photodetector fabricated on Si substrate using thin SiGe buffer layers,” Appl.

Phys. Lett., vol.85, no.15, pp.2386, Oct. 2004.

[126] G. Luo, T. -H. Yang, E. -Y. Chang, C. -Y. Chang, and K. -A. Chao,

“Growth of high-quality Ge epitaxial layers on Si (100),” Jpn. J. Appl. Phys.,

vol.42, pp.L517-519, 2003.

142

VITA

Zhihong Huang (黄志宏) was born in Beijing, China on May 16, 1977,

the daughter of Xianli Huang (黄宪立) and Shujie Ye (叶淑洁). She received

the degree of Bachelor of Science in Astronomy from Beijing University, P. R.

China, in 1999, and the Master of Science in Engineering from the University of

Texas at Austin in 2002. In August 2000, she entered the graduate program in

Astronomy at the University of Texas at Austin, and in May 2001, she joined the

Microelectronics Research Center (MRC) to pursue her Ph.D. in Electrical

Engineering.

Permanent address: Rm. 106, Xinwai Dajie Jia No. 28,

Beijing 100088

P. R. China

This dissertation was typed by author.