cosc 2150: computer organization

Cosc 2150:Computer Organization

Chapter 4: CPU

CPU Basics

• The computer’s CPU fetches, decodes, and executes program instructions.

• The two principal parts of the CPU are the datapath and the control unit.—The datapath consists of an arithmetic-logic

unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory.

—Various CPU components perform sequenced operations according to signals provided by its control unit.

CPU Basics

• Registers hold data that can be readily accessed by the CPU.

• They can be implemented using D flip-flops.—A 32-bit register requires 32 D flip-flops.

• The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit.

• The control unit determines which actions to carry out according to the values in a program counter register and a status register.

The Bus

• The CPU shares data with other system components by way of a data bus.—A bus is a set of wires that simultaneously

convey a single bit along each line.• Two types of buses are commonly found in computer

systems: point-to-point, and multipoint buses.

These are point-to-point buses:

The Bus (2)

• Buses consist of data lines, control lines, and address lines.

• While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the bus.

• Address lines determine the location of the source or destination of the data.

• Different type of connection for different type of unit—Memory—Input/Output—CPU

Computer Modules

Memory Connection

• Receives and sends data• Receives addresses (of locations)• Receives control signals

—Read—Write—Timing

Input/Output Connection(1)

• Similar to memory from computer’s viewpoint

• Output—Receive data from computer—Send data to peripheral

• Input—Receive data from peripheral—Send data to computer

Input/Output Connection(2)

• Receive control signals from computer• Send control signals to peripherals

—e.g. spin disk

• Receive addresses from computer—e.g. port number to identify peripheral

• Send interrupt signals (control)

CPU Connection

• Reads instruction and data• Writes out data (after processing)• Sends control signals to other units• Receives (& acts on) interrupts

Buses

• There are a number of possible interconnection systems

• Single and multiple BUS structures are most common

• e.g. Control/Address/Data bus (PC)• e.g. Unibus (DEC-PDP)

What is a Bus?

• A communication pathway connecting two or more devices

• Usually broadcast • Often grouped

—A number of channels in one bus—e.g. 32 bit data bus is 32 separate single bit

channels

• Power lines may not be shown

Data Bus

• Carries data—Remember that there is no difference between

“data” and “instruction” at this level

• Width is a key determinant of performance—8, 16, 32, 64 bit

Address bus

• Identify the source or destination of data• e.g. CPU needs to read an instruction

(data) from a given location in memory• Bus width determines maximum memory

capacity of system—e.g. 8080 has 16 bit address bus giving 64k

address space

Control Bus

• Control and timing information—Memory read/write signal—Interrupt request—Clock signals

Bus Interconnection Scheme

Big and Yellow?

• What do buses look like?—Parallel lines on circuit boards—Ribbon cables—Strip connectors on mother boards

– e.g. PCI

—Sets of wires

Physical Realization of Bus Architecture

Single Bus Problems

• Lots of devices on one bus leads to:—Propagation delays

– Long data paths mean that co-ordination of bus use can adversely affect performance

– If aggregate data transfer approaches bus capacity

• Most systems use multiple buses to overcome these problems

Traditional (ISA)(with cache)

ISA bus

• ISA (Industrial Standard Architecture)—First Open system bus architecture for PCs

– 8 bit and 16 bit buses

—8 bit– 4.77 MHz, 20 address lines (1M address space)

—16 bit (introduced with the 286)– 8.33 MHz, 24 address lines (16M address space)

• EISA (Extended ISA)—Introduced in 88-89—16/32 bit data lines, 24/32 bit address,

8.33MHz—Backward compatible with ISA, roughly twice

the space of ISA

High Performance Bus

Bus Types

• Dedicated—Separate data & address lines

• Multiplexed—Shared lines—Address valid or data valid control line—Advantage - fewer lines—Disadvantages

– More complex control– Ultimate performance

Bus Arbitration

• More than one module controlling the bus• e.g. CPU and DMA controller• Only one module may control bus at one

time• Arbitration may be centralised or

distributed

Centralised or Distributed Arbitration

• Centralised—Single hardware device controlling bus access

– Bus Controller– Arbiter

—May be part of CPU or separate

• Distributed—Each module may claim the bus—Control logic on all modules

Timing

• Co-ordination of events on bus• Synchronous

—Events determined by clock signals—Control Bus includes clock line—A single 1-0 is a bus cycle—All devices can read clock line—Usually sync on leading edge—Usually a single cycle for an event

Synchronous Timing Diagram

PCI Bus

• Peripheral Component Interconnection• Intel released to public domain• 33/100/133/266/333+ MHz clock,

independent of processor• 32 or 64 bit data and address lines (128

bit soon)—50 lines—Supports up to 16 slots and ISA slots

– Normally, 2 ISA slot, 1 of which is a “shared” slot with PCI

—PCI Express x16 adapters and PCI Express x1 adapters

PCI examples

• PCI 32 bit slot

• AGP slot

• PCI Express x16 slot

• PCI Express x1 slot

PCI Bus Lines (required)

• Systems lines—Including clock and reset

• Address & Data—32 time mux lines for address/data—Interrupt & validate lines

• Interface Control• Arbitration

—Not shared—Direct connection to PCI bus arbiter

• Error lines

PCI Bus Lines (Optional)

• Interrupt lines—Not shared

• Cache support• 64-bit Bus Extension

—Additional 32 lines—Time multiplexed—2 lines to enable devices to agree to use 64-bit

transfer

PCI Commands

• Transaction between initiator (master) and target

• Master claims bus• Determine type of transaction

—e.g. I/O read/write

• Address phase• One or more data phases

Clocks

• Every computer contains at least one clock that synchronizes the activities of its components.

• A fixed number of clock cycles are required to carry out each data movement or computational operation.

• The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out.

• Clock cycle time is the reciprocal of clock frequency.—An 800 MHz clock has a cycle time of 1.25 ns.

• Clock speed should not be confused with CPU performance.

• The CPU time required to run a program is given by the general performance equation:

—We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock cycle.

We will return to this important equation in later chapters.

Clocks (2)

The Input/Output Subsystem

• A computer communicates with the outside world through its input/output (I/O) subsystem.

• I/O devices connect to the CPU through various interfaces.

• I/O can be memory-mapped-- where the I/O device behaves like main memory from the CPU’s point of view.

• Or I/O can be instruction-based, where the CPU has a specialized I/O instruction set.

We study I/O in detail in chapter 7.

Memory Organization

• Computer memory consists of a linear array of addressable storage cells that are similar to registers.

• Memory can be byte-addressable, or word-addressable, where a word typically consists of two or more bytes.

• Memory is constructed of RAM chips, often referred to in terms of length width.

• If the memory word size of the machine is 16 bits, then a 4M 16 RAM chip gives us 4 megabytes of 16-bit memory locations.

• How does the computer access a memory location corresponds to a particular address?

• We observe that 4M can be expressed as 2 2 2 20 = 2 22 words.

• The memory locations for this memory are numbered 0 through 2 22 -1.

• Thus, the memory bus of this system requires at least 22 address lines.—The address lines “count” from 0 to 222 - 1 in

binary. Each line is either “on” or “off” indicating the location of the desired memory element.

Memory Organization

Memory Organization

• Physical memory usually consists of more than one RAM chip.

• Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips

• With low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest.

• Accordingly, in high-order interleaving, the high order address bits specify the memory bank.The next slide illustrates these two ideas.

Low-Order Interleaving

High-Order Interleaving

Memory Organization

Memory Organization

• Example: Suppose we have a memory consisting of 16 2K x 8 bit chips.

– Memory is 32K = 25 210 = 215

– 15 bits are needed for each address.

– We need 4 bits to select the chip, and 11 bits for the offset into the chip that selects the byte.

Memory Organization

• In high-order interleaving the high-order 4 bits select the chip.

• In low-order interleaving the low-order 4 bits select the chip.

Computer Components:Top Level View

Instruction Cycle with Interrupts

Data Flow (Instruction Fetch)

• Depends on CPU design• In general:

• Fetch—PC contains address of next instruction—Address moved to MAR—Address placed on address bus—Control unit requests memory read—Result placed on data bus, copied to MBR,

then to IR—Meanwhile PC incremented by 1—IR is examined

Data Flow (Fetch Diagram)

Indirect Cycle

• Added to fetch• May require memory access to fetch

operands• Indirect addressing requires more memory

accesses• Can be thought of as additional instruction

subcycle

The next slide shows a flowchart of this process.

Instruction Cycle State Diagram

Data Flow (Data Fetch)

• If indirect addressing, indirect cycle is performed—Right most N bits of MBR transferred to MAR—Control unit requests memory read—Result (address of operand) moved to MBR

Data Flow (Indirect Diagram)

Data Flow (Execute)

• May take many forms• Depends on instruction being executed• May include

—Memory read/write—Input/Output—Register transfers—ALU operations

• In other words:—do what the instruction says to do.

Interrupts

• Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

• Program—e.g. overflow, division by zero

• Timer—Generated by internal processor timer—Used in pre-emptive multi-tasking

• I/O—from I/O controller

• Hardware failure—e.g. memory parity error

Transfer of Control via Interrupts

Program Flow Control

Data Flow (Interrupt)

• Simple• Predictable• Current PC saved to allow resumption

after interrupt• Process:

—Contents of PC copied to MBR—Special memory location (e.g. stack pointer)

loaded to MAR—MBR written to memory—PC loaded with address of interrupt handling

routine

• Next instruction (first of interrupt handler) can be fetched

Data Flow (Interrupt Diagram)

Multiple Interrupts

• Disable interrupts—Processor will ignore further interrupts whilst

processing one interrupt—Interrupts remain pending and are checked

after first interrupt has been processed—Interrupts handled in sequence as they occur

• Define priorities—Low priority interrupts can be interrupted by

higher priority interrupts—When higher priority interrupt has been

processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts – Nested

A Discussion on Assemblers

• Mnemonic instructions, such as LOAD M(104), are easy for humans to write and understand.

• They are impossible for computers to understand.

• Assemblers translate instructions that are comprehensible to humans into the machine language that is comprehensible to computers—We note the distinction between an assembler

and a compiler: In assembly language, there is a one-to-one correspondence between a mnemonic instruction and its machine code. With compilers, this is not usually the case.


• Assemblers create an object program file from mnemonic source code in two passes.

• During the first pass, the assembler assembles as much of the program as it can, while it builds a symbol table that contains memory references for all symbols in the program.

• During the second pass, the instructions are completed using the values from the symbol table.

• Consider our example program at the right. —Note that we have

included two directives HEX and DEC that specify the radix of the constants.

• The first pass, creates a symbol table and the partially-assembled instructions as shown.


• After the second pass, the assembly is complete.


A Discussion on Decoding

• A computer’s control unit keeps things synchronized, making sure that bits flow to the correct components as the components are needed.

• There are two general ways in which a control unit can be implemented: hardwired control and microprogrammed control. —With microprogrammed control, a small

program is placed into read-only memory in the microcontroller.

—Hardwired controllers implement this program using digital logic components.

• We note that the signal pattern just described is the same whether our machine used hardwired or microprogrammed control.

• In hardwired control, the bit pattern of machine instruction in the IR is decoded by combinational logic.

• The decoder output works with the control signals of the current system state to produce a new set of control signals.


A block diagram of a hardwired control unit is shown on the following slide.

65

Hardwired Control Unit

Sample Instruction Decoder


• In microprogrammed control, instruction microcode produces control signal changes.

• Machine instructions are the input for a microprogram that converts the 1s and 0s of an instruction into control signals.

• The microprogram is stored in firmware, which is also called the control store.

• A microcode instruction is retrieved during each clock cycle.

This is how a generic microprogrammed control unit might look.

Microprogrammed Control Unit

• If IAS were microprogrammed, the microinstruction format might look like this:

• MicroOp1 and MicroOp2 contain binary codes for each instruction. Jump is a single bit indicating that the value in the Dest field is a valid address and should be placed in the microsequencer.


• A sample table of some Micro Operations:


• Some Micro Operations for the Fetch.


Control Unit

• It’s important to remember that a microprogrammed control unit works like a system-in-miniature.

• Microinstructions are fetched, decoded, and executed in the same manner as regular instructions.

• This extra level of instruction interpretation is what makes microprogrammed control slower than hardwired control.

• The advantages of microprogrammed control are that it can support very complicated instructions and only the microprogram needs to be changed if the instruction set changes (or an error is found).

Real World Architectures

• We will look at an Intel architecture, which is a CISC machine and MIPS, which is a RISC machine.—CISC is an acronym for complex instruction set

computer.—RISC stands for reduced instruction set

computer.

We delve into the “RISC versus CISC” argument in Chapter 9.


• The classic Intel architecture, the 8086, was born in 1979. It is a CISC architecture.

• It was adopted by IBM for its famed PC, which was released in 1981.

• The 8086 operated on 16-bit data words and supported 20-bit memory addresses.

• Later, to lower costs, the 8-bit 8088 was introduced. Like the 8086, it used 20-bit memory addresses.What was the largest memory that the 8086 could address?


• The 8086 had four 16-bit general-purpose registers that could be accessed by the half-word.

• It also had a flags register, an instruction register, and a stack accessed through the values in two other registers, the base pointer and the stack pointer.

• The 8086 had no built in floating-point processing.

• In 1980, Intel released the 8087 numeric coprocessor, but few users elected to install them because of their high cost.


• In 1985, Intel introduced the 32-bit 80386.—It also had no built-in floating-point unit.

• The 80486, introduced in 1989, was an 80386 that had built-in floating-point processing and cache memory.—DX had floating-point, the SX did not.

• The 80386 and 80486 offered downward compatibility with the 8086 and 8088.

• Software written for the smaller-word systems was directed to use the lower 16 bits of the 32-bit registers.


• Intel’s Pentium 4 introduced a brand new NetBurst architecture.

• Speed enhancing features include:—Hyperthreading—Hyperpipelining—Wider instruction pipeline—Execution trace cache (holds decoded

instructions for possible reuse) multilevel cache and instruction pipelining.

• Intel, along with many others, is marrying many of the ideas of RISC architectures with microprocessors that are largely CISC.


• The MIPS family of CPUs has been one of the most successful in its class.

• In 1986 the first MIPS CPU was announced.

• It had a 32-bit word size and could address 4GB of memory.

• Over the years, MIPS processors have been used in general purpose computers as well as in games.

• The MIPS architecture now offers 32- and 64-bit versions.


• MIPS was one of the first RISC microprocessors.

• The original MIPS architecture had only 55 different instructions, as compared with the 8086 which had over 100.

• MIPS was designed with performance in mind: It is a load/store architecture, meaning that only the load and store instructions can access memory.

• The large number of registers in the MIPS architecture keeps bus traffic to a minimum. How does this design affect performance?

Chapter 4 Conclusion

• The major components of a computer system are its control unit, registers, memory, ALU, and data path.

• A built-in clock keeps everything synchronized.

• Control units can be microprogrammed or hardwired.

• Hardwired control units give better performance, while microprogrammed units are more adaptable to changes.

cosc 2150: computer organization

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peripheralsend data

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